35 #define reg_write(a, v) writel(v, a)  macro
146 	reg_write(&regs->ctrl, reg_ctrl);  in spi_cfg_mxc()
148 	reg_write(&regs->ctrl, reg_ctrl);  in spi_cfg_mxc()
202 	reg_write(&regs->ctrl, reg_ctrl);  in spi_cfg_mxc()
204 	reg_write(&regs->cfg, reg_config);  in spi_cfg_mxc()
211 	reg_write(&regs->intr, 0);  in spi_cfg_mxc()
212 	reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);  in spi_cfg_mxc()
234 	reg_write(&regs->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN);  in spi_xchg_single()
236 	reg_write(&regs->cfg, mxcs->cfg_reg);  in spi_xchg_single()
240 	reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);  in spi_xchg_single()
257 		reg_write(&regs->txdata, data);  in spi_xchg_single()
278 		reg_write(&regs->txdata, data);  in spi_xchg_single()
283 	reg_write(&regs->ctrl, mxcs->ctrl_reg |  in spi_xchg_single()
298 	reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);  in spi_xchg_single()
381 	reg_write(&regs->rxdata, 1);  in mxc_spi_claim_bus_internal()
388 	reg_write(&regs->period, MXC_CSPIPERIOD_32KHZ);  in mxc_spi_claim_bus_internal()
389 	reg_write(&regs->intr, 0);  in mxc_spi_claim_bus_internal()