209 	int (*reg_write)(struct qcom_swrm_ctrl *ctrl, int reg, int val);  member
454 	ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_WR_CMD], val);  in qcom_swrm_cmd_fifo_wr_cmd()
494 	ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_CMD], val);  in qcom_swrm_cmd_fifo_rd_cmd()
511 				ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD,  in qcom_swrm_cmd_fifo_rd_cmd()
513 				ctrl->reg_write(ctrl,  in qcom_swrm_cmd_fifo_rd_cmd()
713 				ctrl->reg_write(ctrl,  in qcom_swrm_irq_handler()
740 				ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1);  in qcom_swrm_irq_handler()
749 				ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1);  in qcom_swrm_irq_handler()
756 				ctrl->reg_write(ctrl,  in qcom_swrm_irq_handler()
766 				ctrl->reg_write(ctrl,  in qcom_swrm_irq_handler()
787 		ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR],  in qcom_swrm_irq_handler()
828 	ctrl->reg_write(ctrl, SWRM_MCP_FRAME_CTRL_BANK_ADDR(0), val);  in qcom_swrm_init()
831 	ctrl->reg_write(ctrl, SWRM_ENUMERATOR_CFG_ADDR, 1);  in qcom_swrm_init()
836 		ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],  in qcom_swrm_init()
842 	ctrl->reg_write(ctrl, SWRM_MCP_CFG_ADDR, val);  in qcom_swrm_init()
845 		ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);  in qcom_swrm_init()
846 		ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL,  in qcom_swrm_init()
849 		ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);  in qcom_swrm_init()
850 		ctrl->reg_write(ctrl, SWRM_V2_0_CLK_CTRL,  in qcom_swrm_init()
853 		ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START);  in qcom_swrm_init()
858 		ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR,  in qcom_swrm_init()
862 		ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR,  in qcom_swrm_init()
867 	ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR, SWRM_COMP_CFG_ENABLE_MSK);  in qcom_swrm_init()
870 	ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR,  in qcom_swrm_init()
873 	ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR],  in qcom_swrm_init()
878 		ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],  in qcom_swrm_init()
883 	ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR,  in qcom_swrm_init()
941 	return ctrl->reg_write(ctrl, reg, val);  in qcom_swrm_pre_bank_switch()
950 	return ctrl->reg_write(ctrl, SWRM_DP_BLOCK_CTRL_1(p_params->num),  in qcom_swrm_port_params()
971 	ret = ctrl->reg_write(ctrl, reg, value);  in qcom_swrm_transport_params()
978 		ret = ctrl->reg_write(ctrl, reg, value);  in qcom_swrm_transport_params()
986 		ret = ctrl->reg_write(ctrl, reg, value);  in qcom_swrm_transport_params()
994 		ret = ctrl->reg_write(ctrl, reg, value);  in qcom_swrm_transport_params()
1003 		ret = ctrl->reg_write(ctrl, reg, value);  in qcom_swrm_transport_params()
1007 		ret = ctrl->reg_write(ctrl, reg, value);  in qcom_swrm_transport_params()
1015 		ret = ctrl->reg_write(ctrl, reg, pcfg->bp_mode);  in qcom_swrm_transport_params()
1037 	return ctrl->reg_write(ctrl, reg, val);  in qcom_swrm_port_enable()
1524 		ctrl->reg_write = qcom_swrm_ahb_reg_write;
1530 		ctrl->reg_write = qcom_swrm_cpu_reg_write;
1682 		ctrl->reg_write(ctrl, SWRM_COMP_SW_RESET, 0x01);
1700 			ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
1701 			ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL,
1704 			ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
1705 			ctrl->reg_write(ctrl, SWRM_V2_0_CLK_CTRL,
1708 			ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START);
1710 		ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR],
1715 			ctrl->reg_write(ctrl,
1718 		ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
1743 			ctrl->reg_write(ctrl,
1746 		ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],