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Searched refs:pci_set_long (Results 1 – 25 of 27) sorted by relevance

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/openbmc/qemu/hw/ide/
H A Dvia.c143 pci_set_long(pci_conf + 0x40, 0x0a090600); in via_ide_reset()
145 pci_set_long(pci_conf + 0x44, 0x00c00068); in via_ide_reset()
147 pci_set_long(pci_conf + 0x48, 0xa8a8a8a8); in via_ide_reset()
149 pci_set_long(pci_conf + 0x4c, 0x000000ff); in via_ide_reset()
151 pci_set_long(pci_conf + 0x50, 0x07070707); in via_ide_reset()
153 pci_set_long(pci_conf + 0x54, 0x00000004); in via_ide_reset()
155 pci_set_long(pci_conf + 0x60, 0x00000200); in via_ide_reset()
157 pci_set_long(pci_conf + 0x68, 0x00000200); in via_ide_reset()
159 pci_set_long(pci_conf + 0xc0, 0x00020001); in via_ide_reset()
204 pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0); in via_ide_realize()
H A Dich.c144 pci_set_long(sata_cap + SATA_CAP_BAR, in pci_ich9_ahci_realize()
H A Dpiix.c121 pci_set_long(pci_conf + 0x20, 0x1); /* BMIBA: 20-23h */ in piix_ide_reset()
/openbmc/qemu/hw/pci/
H A Dpcie_aer.c113 pci_set_long(dev->w1cmask + offset + PCI_ERR_UNCOR_STATUS, in pcie_aer_init()
117 pci_set_long(dev->config + offset + PCI_ERR_UNCOR_MASK, in pcie_aer_init()
119 pci_set_long(dev->wmask + offset + PCI_ERR_UNCOR_MASK, in pcie_aer_init()
123 pci_set_long(dev->config + offset + PCI_ERR_UNCOR_SEVER, in pcie_aer_init()
125 pci_set_long(dev->wmask + offset + PCI_ERR_UNCOR_SEVER, in pcie_aer_init()
131 pci_set_long(dev->config + offset + PCI_ERR_COR_MASK, in pcie_aer_init()
133 pci_set_long(dev->wmask + offset + PCI_ERR_COR_MASK, in pcie_aer_init()
138 pci_set_long(dev->config + offset + PCI_ERR_CAP, in pcie_aer_init()
141 pci_set_long(dev->wmask + offset + PCI_ERR_CAP, in pcie_aer_init()
145 pci_set_long(dev->config + offset + PCI_ERR_CAP, in pcie_aer_init()
[all …]
H A Dmsi.c135 pci_set_long(dev->config + msi_address_lo_off(dev), msg.address); in msi_set_message()
239 pci_set_long(dev->wmask + msi_address_lo_off(dev), in msi_init()
242 pci_set_long(dev->wmask + msi_address_hi_off(dev), 0xffffffff); in msi_init()
248 pci_set_long(dev->wmask + msi_mask_off(dev, msi64bit), in msi_init()
288 pci_set_long(dev->config + msi_address_lo_off(dev), 0); in msi_reset()
290 pci_set_long(dev->config + msi_address_hi_off(dev), 0); in msi_reset()
294 pci_set_long(dev->config + msi_mask_off(dev, msi64bit), 0); in msi_reset()
295 pci_set_long(dev->config + msi_pending_off(dev, msi64bit), 0); in msi_reset()
343 pci_set_long(dev->config + msi_mask_off(dev, msi64bit), irq_state); in msi_set_mask()
348 pci_set_long(dev->config + msi_pending_off(dev, msi64bit), pending); in msi_set_mask()
[all …]
H A Dshpc.c193 pci_set_long(shpc->config + SHPC_INT_LOCATOR, int_locator); in shpc_interrupt_update()
222 pci_set_long(shpc->config + SHPC_SLOTS_33, nslots); in shpc_reset()
223 pci_set_long(shpc->config + SHPC_SLOTS_66, 0); in shpc_reset()
230 pci_set_long(shpc->config + SHPC_SERR_INT, SHPC_INT_DIS | in shpc_reset()
495 pci_set_long(d->config + d->shpc->cap + SHPC_CAP_DWORD_DATA, data); in shpc_cap_update_dword()
513 pci_set_long(config + SHPC_CAP_DWORD_DATA, 0); in shpc_cap_add_config()
517 pci_set_long(d->wmask + config_offset + SHPC_CAP_DWORD_DATA, 0xffffffff); in shpc_cap_add_config()
675 pci_set_long(shpc->config + SHPC_BASE_OFFSET, offset); in shpc_init()
680 pci_set_long(shpc->wmask + SHPC_SERR_INT, in shpc_init()
685 pci_set_long(shpc->w1cmask + SHPC_SERR_INT, in shpc_init()
H A Dpci_bridge.c298 pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0); in pci_bridge_disable_base_limit()
299 pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0); in pci_bridge_disable_base_limit()
335 pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0); in pci_bridge_reset()
336 pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0); in pci_bridge_reset()
H A Dpcie_sriov.c96 pci_set_long(dev->config + addr, type); in pcie_sriov_pf_init_vf_bar()
102 pci_set_long(dev->wmask + addr, wmask & 0xffffffff); in pcie_sriov_pf_init_vf_bar()
103 pci_set_long(dev->cmask + addr, 0xffffffff); in pcie_sriov_pf_init_vf_bar()
H A Dpcie.c95 pci_set_long(exp_cap + PCI_EXP_DEVCAP, devcap); in pcie_cap_v1_fill()
97 pci_set_long(exp_cap + PCI_EXP_LNKCAP, in pcie_cap_v1_fill()
243 pci_set_long(exp_cap + PCI_EXP_DEVCAP2, in pcie_cap_init()
250 pci_set_long(dev->wmask + PCI_CONFIG_SPACE_SIZE, 0); in pcie_cap_init()
1050 pci_set_long(dev->config + pos, header); in pcie_ext_cap_set_next()
1079 pci_set_long(dev->config + offset, PCI_EXT_CAP(cap_id, cap_ver, 0)); in pcie_add_capability()
1149 pci_set_long(dev->config + offset + PCI_ARI_CAP, (nextfn & 0xff) << 8); in pcie_ari_init()
H A Dmsix.c60 pci_set_long(table_entry + PCI_MSIX_ENTRY_DATA, msg.data); in msix_set_message()
230 pci_set_long(dev->msix_table + addr, val); in msix_table_mmio_write()
361 pci_set_long(config + PCI_MSIX_TABLE, table_offset | table_bar_nr); in msix_init()
362 pci_set_long(config + PCI_MSIX_PBA, pba_offset | pba_bar_nr); in msix_init()
H A Dpci.c403 pci_set_long(dev->config + pci_bar(dev, r), region->type); in pci_reset_regions()
1357 pci_set_long(pci_dev->config + addr, type); in pci_register_bar()
1364 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff); in pci_register_bar()
1365 pci_set_long(pci_dev->cmask + addr, 0xffffffff); in pci_register_bar()
/openbmc/qemu/hw/usb/
H A Dvt82c686-uhci-pci.c18 pci_set_long(pci_conf + 0x40, 0x00001000); in usb_uhci_vt82c686b_realize()
20 pci_set_long(pci_conf + 0x80, 0x00020001); in usb_uhci_vt82c686b_realize()
22 pci_set_long(pci_conf + 0xc0, 0x00002000); in usb_uhci_vt82c686b_realize()
/openbmc/qemu/hw/isa/
H A Dlpc_ich9.c138 pci_set_long(c + ICH9_CC_D31IR, ICH9_CC_DIR_DEFAULT); in ich9_cc_reset()
139 pci_set_long(c + ICH9_CC_D30IR, ICH9_CC_D30IR_DEFAULT); in ich9_cc_reset()
140 pci_set_long(c + ICH9_CC_D29IR, ICH9_CC_DIR_DEFAULT); in ich9_cc_reset()
141 pci_set_long(c + ICH9_CC_D28IR, ICH9_CC_DIR_DEFAULT); in ich9_cc_reset()
142 pci_set_long(c + ICH9_CC_D27IR, ICH9_CC_DIR_DEFAULT); in ich9_cc_reset()
143 pci_set_long(c + ICH9_CC_D26IR, ICH9_CC_DIR_DEFAULT); in ich9_cc_reset()
144 pci_set_long(c + ICH9_CC_D25IR, ICH9_CC_DIR_DEFAULT); in ich9_cc_reset()
145 pci_set_long(c + ICH9_CC_GCS, ICH9_CC_GCS_DEFAULT); in ich9_cc_reset()
604 pci_set_long(d->config + ICH9_LPC_PMBASE, ICH9_LPC_PMBASE_DEFAULT); in ich9_lpc_reset()
605 pci_set_long(d->config + ICH9_LPC_RCBA, ICH9_LPC_RCBA_DEFAULT); in ich9_lpc_reset()
[all …]
H A Dvt82c686.c108 pci_set_long(s->dev.config + 0x48, (v & 0xff80UL) | 1); in pm_write_config()
115 pci_set_long(s->dev.config + 0x90, (v & 0xfff0UL) | 1); in pm_write_config()
184 pci_set_long(s->dev.config + 0x48, 1); in via_pm_reset()
186 pci_set_long(s->dev.config + 0x90, 1); in via_pm_reset()
813 pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0); in vt82c686b_isa_reset()
882 pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0); in vt8231_isa_reset()
/openbmc/qemu/hw/pci-host/
H A Dgt64120.c1218 pci_set_long(d->wmask + PCI_BASE_ADDRESS_0, 0xfffff008); /* SCS[1:0] */ in gt64120_pci_realize()
1219 pci_set_long(d->wmask + PCI_BASE_ADDRESS_1, 0xfffff008); /* SCS[3:2] */ in gt64120_pci_realize()
1220 pci_set_long(d->wmask + PCI_BASE_ADDRESS_2, 0xfffff008); /* CS[2:0] */ in gt64120_pci_realize()
1221 pci_set_long(d->wmask + PCI_BASE_ADDRESS_3, 0xfffff008); /* CS[3], BootCS */ in gt64120_pci_realize()
1222 pci_set_long(d->wmask + PCI_BASE_ADDRESS_4, 0xfffff000); /* ISD MMIO */ in gt64120_pci_realize()
1223 pci_set_long(d->wmask + PCI_BASE_ADDRESS_5, 0xfffff001); /* ISD I/O */ in gt64120_pci_realize()
1237 pci_set_long(d->config + PCI_BASE_ADDRESS_0, 0x00000008); in gt64120_pci_reset_hold()
1238 pci_set_long(d->config + PCI_BASE_ADDRESS_1, 0x01000008); in gt64120_pci_reset_hold()
1239 pci_set_long(d->config + PCI_BASE_ADDRESS_2, 0x1c000000); in gt64120_pci_reset_hold()
1240 pci_set_long(d->config + PCI_BASE_ADDRESS_3, 0x1f000000); in gt64120_pci_reset_hold()
[all …]
H A Dpnv_phb.c235 pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0x1); /* Hack */ in pnv_phb_root_port_reset_hold()
236 pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0xffffffff); in pnv_phb_root_port_reset_hold()
/openbmc/qemu/hw/vfio/
H A Digd.c429 pci_set_long(vdev->pdev.config + offset, data); in vfio_igd_quirk_bdsm_write()
701 pci_set_long(vdev->pdev.config + IGD_GMCH, gmch); in vfio_probe_igd_bar4_quirk()
702 pci_set_long(vdev->pdev.wmask + IGD_GMCH, 0); in vfio_probe_igd_bar4_quirk()
703 pci_set_long(vdev->emulated_config_bits + IGD_GMCH, ~0); in vfio_probe_igd_bar4_quirk()
707 pci_set_long(vdev->pdev.config + IGD_BDSM, 0); in vfio_probe_igd_bar4_quirk()
708 pci_set_long(vdev->pdev.wmask + IGD_BDSM, ~0); in vfio_probe_igd_bar4_quirk()
709 pci_set_long(vdev->emulated_config_bits + IGD_BDSM, ~0); in vfio_probe_igd_bar4_quirk()
H A Dpci-quirks.c1205 pci_set_long(vdev->pdev.config + IGD_ASLS, 0); in vfio_pci_igd_opregion_init()
1206 pci_set_long(vdev->pdev.wmask + IGD_ASLS, ~0); in vfio_pci_igd_opregion_init()
1207 pci_set_long(vdev->emulated_config_bits + IGD_ASLS, ~0); in vfio_pci_igd_opregion_init()
1665 pci_set_long(vdev->pdev.config + pos, 0x53484457); /* SHDW */ in vfio_add_vmd_shadow_cap()
/openbmc/qemu/docs/devel/migration/
H A Dcompatibility.rst365 pci_set_long(dev->w1cmask + offset + PCI_ERR_UNCOR_STATUS,
367 + pci_set_long(dev->config + offset + PCI_ERR_UNCOR_MASK,
369 + pci_set_long(dev->wmask + offset + PCI_ERR_UNCOR_MASK,
372 pci_set_long(dev->config + offset + PCI_ERR_UNCOR_SEVER,
419 pci_set_long(dev->w1cmask + offset + PCI_ERR_UNCOR_STATUS,
421 - pci_set_long(dev->config + offset + PCI_ERR_UNCOR_MASK,
423 - pci_set_long(dev->wmask + offset + PCI_ERR_UNCOR_MASK,
427 + pci_set_long(dev->config + offset + PCI_ERR_UNCOR_MASK,
429 + pci_set_long(dev->wmask + offset + PCI_ERR_UNCOR_MASK,
433 pci_set_long(dev->config + offset + PCI_ERR_UNCOR_SEVER,
/openbmc/qemu/include/hw/pci/
H A Dpci.h469 pci_set_long(uint8_t *config, uint32_t val) in pci_set_long() function
577 pci_set_long(config, val & ~mask); in pci_long_test_and_clear_mask()
585 pci_set_long(config, val | mask); in pci_long_test_and_set_mask()
636 pci_set_long(config, (~mask & val) | (mask & rval)); in pci_set_long_by_mask()
/openbmc/qemu/hw/ipack/
H A Dtpci200.c591 pci_set_long(c + 0x40, 0x48014801); in tpci200_realize()
592 pci_set_long(c + 0x48, 0x00024C06); in tpci200_realize()
593 pci_set_long(c + 0x4C, 0x00000003); in tpci200_realize()
/openbmc/qemu/hw/i386/
H A Damd_iommu.c1594 pci_set_long(pdev->config + s->capab_offset, AMDVI_CAPAB_FEATURES); in amdvi_pci_realize()
1595 pci_set_long(pdev->config + s->capab_offset + AMDVI_CAPAB_BAR_LOW, in amdvi_pci_realize()
1597 pci_set_long(pdev->config + s->capab_offset + AMDVI_CAPAB_BAR_HIGH, in amdvi_pci_realize()
1599 pci_set_long(pdev->config + s->capab_offset + AMDVI_CAPAB_RANGE, in amdvi_pci_realize()
1601 pci_set_long(pdev->config + s->capab_offset + AMDVI_CAPAB_MISC, 0); in amdvi_pci_realize()
1602 pci_set_long(pdev->config + s->capab_offset + AMDVI_CAPAB_MISC, in amdvi_pci_realize()
/openbmc/qemu/hw/audio/
H A Dvia-ac97.c443 pci_set_long(pci_dev->config + PCI_INTERRUPT_PIN, 0x03); in via_ac97_realize()
502 pci_set_long(pci_dev->config + PCI_INTERRUPT_PIN, 0x03); in via_mc97_realize()
/openbmc/qemu/hw/cxl/
H A Dcxl-component-utils.c387 pci_set_long(pdev->config + offset + PCIE_DVSEC_HEADER1_OFFSET, in cxl_component_create_dvsec()
/openbmc/qemu/hw/virtio/
H A Dvirtio-pci.c710 pci_set_long(buf, val); in virtio_address_space_read()
2079 pci_set_long((uint8_t *)&cfg_mask->cap.offset, ~0x0); in virtio_pci_device_plugged()
2080 pci_set_long((uint8_t *)&cfg_mask->cap.length, ~0x0); in virtio_pci_device_plugged()
2081 pci_set_long(cfg_mask->pci_cfg_data, ~0x0); in virtio_pci_device_plugged()

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