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/openbmc/linux/drivers/cxl/
H A DKconfig3 tristate "CXL (Compute Express Link) Devices Support"
9 CXL is a bus that is electrically compatible with PCI Express, but
10 layers three protocols on that signalling (CXL.io, CXL.cache, and
11 CXL.mem). The CXL.cache protocol allows devices to hold cachelines
12 locally, the CXL.mem protocol allows devices to be fully coherent
13 memory targets, the CXL.io protocol is equivalent to PCI Express.
23 The CXL specification defines a "CXL memory device" sub-class in the
29 Say 'y/m' to enable a driver that will attach to CXL memory expander
32 Type 3 CXL Device in the CXL 2.0 specification for more details.
40 Enable CXL RAW command interface.
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/openbmc/qemu/docs/system/devices/
H A Dcxl.rst1 Compute Express Link (CXL)
3 From the view of a single host, CXL is an interconnect standard that
4 targets accelerators and memory devices attached to a CXL host.
9 for real hardware and will dominate more general introductions to CXL.
10 It will also completely ignore the fabric management aspects of CXL
13 CXL shares many concepts and much of the infrastructure of PCI Express,
14 with CXL Host Bridges, which have CXL Root Ports which may be directly
15 attached to CXL or PCI End Points. Alternatively there may be CXL Switches
16 with CXL and PCI Endpoints attached below them. In many cases additional
20 CXL elements are built upon an equivalent PCIe devices.
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/openbmc/qemu/qapi/
H A Dcxl.json5 # = CXL devices
11 # CXL has a number of separate event logs for different types of
34 # Inject an event record for a General Media Event (CXL r3.0
38 # @path: CXL type 3 device canonical QOM path
42 # @flags: Event Record Flags. See CXL r3.0 Table 8-42 Common Event
46 # lower bits include some flags. See CXL r3.0 Table 8-43 General
50 # information. See CXL r3.0 Table 8-43 General Media Event
53 # @type: Type of memory event that occurred. See CXL r3.0 Table 8-43
58 # to occur. See CXL r3.0 Table 8-43 General Media Event Record,
85 # Inject an event record for a DRAM Event (CXL r3.0 8.2.9.2.1.2).
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/openbmc/linux/Documentation/driver-api/cxl/
H A Dmemory-devices.rst8 A Compute Express Link Memory Device is a CXL component that implements the
9 CXL.mem protocol. It contains some amount of volatile memory, persistent memory,
17 CXL Bus: Theory of Operation
20 logical device, the CXL subsystem is tasked to take PCIe and ACPI objects and
21 assemble them into a CXL.mem decode topology. The need for runtime configuration
22 of the CXL.mem topology is also similar to RAID in that different environments
26 and disable any striping in the CXL.mem topology.
28 Platform firmware enumerates a menu of interleave options at the "CXL root port"
29 (Linux term for the top of the CXL decode topology). From there, PCIe topology
38 Here is a sample listing of a CXL topology defined by 'cxl_test'. The 'cxl_test'
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/openbmc/linux/Documentation/admin-guide/perf/
H A Dcxl.rst4 CXL Performance Monitoring Unit (CPMU)
7 The CXL rev 3.0 specification provides a definition of CXL Performance
10 CXL components (e.g. Root Port, Switch Upstream Port, End Point) may have
12 the devices. The specification provides event definitions for all CXL protocol
14 CXL devices (e.g. DRAM events).
19 The CPMU driver registers a perf PMU with the name pmu_mem<X>.<Y> on the CXL bus
28 In common with other CXL bus devices, the id has no specific meaning and the
29 relationship to specific CXL device should be established via the device parent
30 of the device on the CXL bus.
/openbmc/linux/drivers/misc/cxl/
H A DKconfig3 # IBM Coherent Accelerator (CXL) compatible devices
11 config CXL config
12 tristate "Support for IBM Coherent Accelerators (CXL)"
18 Accelerators (CXL). CXL is otherwise known as Coherent Accelerator
/openbmc/linux/tools/testing/cxl/test/
H A Dmock.c150 EXPORT_SYMBOL_NS_GPL(__wrap_devm_cxl_setup_hdm, CXL);
165 EXPORT_SYMBOL_NS_GPL(__wrap_devm_cxl_add_passthrough_decoder, CXL);
182 EXPORT_SYMBOL_NS_GPL(__wrap_devm_cxl_enumerate_decoders, CXL);
197 EXPORT_SYMBOL_NS_GPL(__wrap_devm_cxl_port_enumerate_dports, CXL);
212 EXPORT_SYMBOL_NS_GPL(__wrap_cxl_await_media_ready, CXL);
229 EXPORT_SYMBOL_NS_GPL(__wrap_cxl_hdm_decode_init, CXL);
245 EXPORT_SYMBOL_NS_GPL(__wrap_cxl_dvsec_rr_decode, CXL);
269 EXPORT_SYMBOL_NS_GPL(__wrap_devm_cxl_add_rch_dport, CXL);
286 EXPORT_SYMBOL_NS_GPL(__wrap_cxl_rcd_component_reg_phys, CXL);
290 MODULE_IMPORT_NS(CXL);
/openbmc/linux/Documentation/ABI/testing/
H A Dsysfs-bus-cxl17 Memory Device Output Payload in the CXL-2.0
28 Payload in the CXL-2.0 specification.
38 Payload in the CXL-2.0 specification.
47 capability. Mandatory for CXL devices, see CXL 2.0 8.1.12.2
66 (RO) Reading this file will display the CXL security state for
116 firmware for CXL devices. The interfaces under this are
125 (RO) CXL device objects export the devtype attribute which
135 (RO) CXL device objects export the modalias attribute which
145 (RO) CXL port objects are enumerated from either a platform
147 port with CXL component registers. The 'uport' symlink connects
[all …]
H A Dsysfs-bus-nvdimm51 Description: (RO) Show the id (serial) of the device. This is CXL specific.
57 Description: (RO) Shows the CXL bridge device that ties to a CXL memory device
/openbmc/linux/drivers/cxl/core/
H A Dpmem.c52 EXPORT_SYMBOL_NS_GPL(to_cxl_nvdimm_bridge, CXL);
58 EXPORT_SYMBOL_NS_GPL(is_cxl_nvdimm_bridge, CXL);
81 EXPORT_SYMBOL_NS_GPL(cxl_find_nvdimm_bridge, CXL);
163 EXPORT_SYMBOL_NS_GPL(devm_cxl_add_nvdimm_bridge, CXL);
187 EXPORT_SYMBOL_NS_GPL(is_cxl_nvdimm, CXL);
196 EXPORT_SYMBOL_NS_GPL(to_cxl_nvdimm, CXL);
290 EXPORT_SYMBOL_NS_GPL(devm_cxl_add_nvdimm, CXL);
H A Dport.c428 EXPORT_SYMBOL_NS_GPL(to_cxl_root_decoder, CXL);
462 EXPORT_SYMBOL_NS_GPL(is_endpoint_decoder, CXL);
468 EXPORT_SYMBOL_NS_GPL(is_root_decoder, CXL);
474 EXPORT_SYMBOL_NS_GPL(is_switch_decoder, CXL);
484 EXPORT_SYMBOL_NS_GPL(to_cxl_decoder, CXL);
493 EXPORT_SYMBOL_NS_GPL(to_cxl_endpoint_decoder, CXL);
502 EXPORT_SYMBOL_NS_GPL(to_cxl_switch_decoder, CXL);
548 EXPORT_SYMBOL_NS_GPL(is_cxl_port, CXL);
557 EXPORT_SYMBOL_NS_GPL(to_cxl_port, CXL);
831 EXPORT_SYMBOL_NS_GPL(devm_cxl_add_port, CXL);
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H A Dregs.c109 EXPORT_SYMBOL_NS_GPL(cxl_probe_component_regs, CXL);
177 EXPORT_SYMBOL_NS_GPL(cxl_probe_device_regs, CXL);
235 EXPORT_SYMBOL_NS_GPL(cxl_map_component_regs, CXL);
269 EXPORT_SYMBOL_NS_GPL(cxl_map_device_regs, CXL);
347 EXPORT_SYMBOL_NS_GPL(cxl_find_regblock_instance, CXL);
365 EXPORT_SYMBOL_NS_GPL(cxl_find_regblock, CXL);
388 EXPORT_SYMBOL_NS_GPL(cxl_count_regblock, CXL);
403 EXPORT_SYMBOL_NS_GPL(cxl_map_pmu_regs, CXL);
472 EXPORT_SYMBOL_NS_GPL(cxl_setup_regs, CXL);
545 EXPORT_SYMBOL_NS_GPL(cxl_rcd_component_reg_phys, CXL);
H A Dsuspend.c18 EXPORT_SYMBOL_NS_GPL(cxl_mem_active_inc, CXL);
24 EXPORT_SYMBOL_NS_GPL(cxl_mem_active_dec, CXL);
H A Dpci.c102 EXPORT_SYMBOL_NS_GPL(devm_cxl_port_enumerate_dports, CXL);
210 EXPORT_SYMBOL_NS_GPL(cxl_await_media_ready, CXL);
418 EXPORT_SYMBOL_NS_GPL(cxl_dvsec_rr_decode, CXL);
495 EXPORT_SYMBOL_NS_GPL(cxl_hdm_decode_init, CXL);
641 EXPORT_SYMBOL_NS_GPL(read_cdat_data, CXL);
659 EXPORT_SYMBOL_NS_GPL(cxl_cor_error_detected, CXL);
751 EXPORT_SYMBOL_NS_GPL(cxl_error_detected, CXL);
H A Dmemdev.c252 EXPORT_SYMBOL_NS_GPL(cxl_trigger_poison_list, CXL);
331 EXPORT_SYMBOL_NS_GPL(cxl_inject_poison, CXL);
395 EXPORT_SYMBOL_NS_GPL(cxl_clear_poison, CXL);
489 EXPORT_SYMBOL_NS_GPL(is_cxl_memdev, CXL);
508 EXPORT_SYMBOL_NS_GPL(set_exclusive_cxl_commands, CXL);
523 EXPORT_SYMBOL_NS_GPL(clear_exclusive_cxl_commands, CXL);
940 EXPORT_SYMBOL_NS_GPL(devm_cxl_setup_fw_upload, CXL);
994 EXPORT_SYMBOL_NS_GPL(devm_cxl_add_memdev, CXL);
1038 EXPORT_SYMBOL_NS_GPL(devm_cxl_sanitize_setup_notifier, CXL);
H A Dmbox.c280 EXPORT_SYMBOL_NS_GPL(cxl_internal_send_cmd, CXL);
837 EXPORT_SYMBOL_NS_GPL(cxl_enumerate_cmds, CXL);
1034 EXPORT_SYMBOL_NS_GPL(cxl_mem_get_event_records, CXL);
1124 EXPORT_SYMBOL_NS_GPL(cxl_dev_state_identify, CXL);
1277 EXPORT_SYMBOL_NS_GPL(cxl_mem_create_range_info, CXL);
1303 EXPORT_SYMBOL_NS_GPL(cxl_set_timestamp, CXL);
1353 EXPORT_SYMBOL_NS_GPL(cxl_mem_get_poison, CXL);
1387 EXPORT_SYMBOL_NS_GPL(cxl_poison_state_init, CXL);
1406 EXPORT_SYMBOL_NS_GPL(cxl_memdev_state_create, CXL);
/openbmc/linux/drivers/scsi/cxlflash/
H A DKconfig3 # IBM CXL-attached Flash Accelerator SCSI Driver
8 depends on PCI && SCSI && (CXL || OCXL) && EEH
/openbmc/linux/drivers/dax/
H A DKconfig48 tristate "CXL DAX: direct access to CXL RAM regions"
52 CXL RAM regions are either mapped by platform-firmware
55 after boot by the CXL driver. In the latter two cases a device-dax
/openbmc/libcper/specification/document/
H A Dcper-json-specification.tex1895 % CXL Protocol error section.
1896 \section{CXL Protocol Error Section}
1898 …on describes the JSON format for a single CXL Protocol Error Section from a CPER record. The GUID …
1900 validationBits & object & A CXL Protocol Validation structure as defined in Subsection \ref{subsect…
1902 agentType.value & uint64 & The raw value of the detecting CXL agent type.\\
1903 agentType.name & string & The human readable name, if available, of the CXL agent type.\\
1907 deviceID & object & A CXL Device ID structure, as defined in Subsection \ref{subsection:cxlprotocol…
1909 …rial & uint64 (\textbf{optional}) & The CXL device serial number. Only included if the detecting d…
1911 …CXL device's PCIe capability structure. This could either be a PCIe 1.1 Capability Structure (36-b…
1913 dvsecLength & int & Length (in bytes) of the CXL DVSEC structure.\\
[all …]
/openbmc/bmcweb/redfish-core/include/generated/enums/
H A Dlog_entry.hpp20 CXL, enumerator
61 {LogEntryType::CXL, "CXL"},
H A Dpcie_function.hpp44 CXL, enumerator
83 {FunctionProtocol::CXL, "CXL"},
H A Dprotocol.hpp47 CXL, enumerator
92 {Protocol::CXL, "CXL"},
H A Dprocessor.hpp68 CXL, enumerator
154 {SystemInterfaceType::CXL, "CXL"},
H A Dlog_service.hpp21 CXL, enumerator
117 {LogEntryTypes::CXL, "CXL"},
/openbmc/linux/Documentation/powerpc/
H A Dcxlflash.rst2 Coherent Accelerator (CXL) Flash
18 On Linux, Coherent Accelerator (CXL) kernel services present CAPI
24 CXL provides a mechanism by which user space applications can
26 kernel/device driver stack. The CXL Flash Adapter Driver enables a
29 The CXL Flash Adapter Driver is a kernel module that sits in the
31 protocol drivers) for the IBM CXL Flash Adapter. This driver is
63 The CXL Flash Adapter Driver establishes a master context with the
84 discovers all LUNs attached to the CXL Flash adapter and instantiates
115 Applications intending to get access to the CXL Flash from user
131 CXL Flash Driver LUN IOCTLs
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