Lines Matching refs:CXL

3 	tristate "CXL (Compute Express Link) Devices Support"
9 	  CXL is a bus that is electrically compatible with PCI Express, but
10 	  layers three protocols on that signalling (CXL.io, CXL.cache, and
11 	  CXL.mem). The CXL.cache protocol allows devices to hold cachelines
12 	  locally, the CXL.mem protocol allows devices to be fully coherent
13 	  memory targets, the CXL.io protocol is equivalent to PCI Express.
23 	  The CXL specification defines a "CXL memory device" sub-class in the
29 	  Say 'y/m' to enable a driver that will attach to CXL memory expander
32 	  Type 3 CXL Device in the CXL 2.0 specification for more details.
40 	  Enable CXL RAW command interface.
42 	  The CXL driver ioctl interface may assign a kernel ioctl command
52 	  If developing CXL hardware or the driver say Y, otherwise say N.
55 	tristate "CXL ACPI: Platform Support"
61 	  published by a platform's ACPI CXL memory layout description.  See
62 	  Chapter 9.14.1 CXL Early Discovery Table (CEDT) in the CXL 2.0
63 	  specification, and CXL Fixed Memory Window Structures (CEDT.CFMWS)
64 	  (https://www.computeexpresslink.org/spec-landing). The CXL core
72 	tristate "CXL PMEM: Persistent Memory Support"
77 	  support for persistent memory attached via CXL. This support is
78 	  managed via a bridge driver from CXL to the LIBNVDIMM system
80 	  provisioning the persistent memory capacity of CXL memory expanders.
85 	tristate "CXL: Memory Expansion"
89 	  The CXL.mem protocol allows a device to act as a provider of "System
94 	  Say 'y/m' to enable a driver that will attach to CXL.mem devices for
95 	  memory expansion and control of HDM. See Chapter 9.13 in the CXL 2.0
109 	bool "CXL: Region Support"
116 	  Enable the CXL core to enumerate and provision CXL regions. A CXL
117 	  region is defined by one or more CXL expanders that decode a given
118 	  system-physical address range. For CXL regions established by
121 	  range. Otherwise, platform-firmware managed CXL is enabled by being
127 	bool "CXL: Region Cache Management Bypass (TEST)"
130 	  CXL Region management and security operations potentially invalidate
132 	  invalidate the affected cachelines. The CXL Region driver attempts
145 	tristate "CXL Performance Monitoring Unit"
149 	  Support performance monitoring as defined in CXL rev 3.0
150 	  section 13.2: Performance Monitoring. CXL components may have
151 	  one or more CXL Performance Monitoring Units (CPMUs).