Lines Matching refs:CXL

17 		Memory Device Output Payload in the CXL-2.0
28 		Payload in the CXL-2.0 specification.
38 		Payload in the CXL-2.0 specification.
47 		capability. Mandatory for CXL devices, see CXL 2.0 8.1.12.2
66 		(RO) Reading this file will display the CXL security state for
116 		firmware for CXL devices. The interfaces under this are
125 		(RO) CXL device objects export the devtype attribute which
135 		(RO) CXL device objects export the modalias attribute which
145 		(RO) CXL port objects are enumerated from either a platform
147 		port with CXL component registers. The 'uport' symlink connects
148 		the CXL portX object to the device that published the CXL port
157 		(RO) CXL port objects are instantiated for each upstream port in
158 		a CXL/PCIe switch, and for each endpoint to map the
159 		corresponding memory device into the CXL port hierarchy. When a
160 		descendant CXL port (switch or endpoint) is enumerated it is
161 		useful to know which 'dport' object in the parent CXL port
163 		the device representing the downstream port of a CXL switch that
172 		(RO) CXL port objects are enumerated from either a platform
174 		port with CXL component registers. The 'dportY' symlink
176 		may target in its decode of CXL memory resources.  The 'Y'
186 		(RO) CXL decoder objects are enumerated from either a platform
187 		firmware description, or a CXL HDM decoder register set in a
188 		PCIe device (see CXL 2.0 section 8.2.5.12 CXL HDM Decoder
214 		(RO) CXL HDM decoders have the capability to lock the
238 		(RO) When a CXL decoder is of devtype "cxl_decoder_root", it
251 		(RO) When a CXL decoder is of devtype "cxl_decoder_switch", it
274 		(RW) When a CXL decoder is of devtype "cxl_decoder_endpoint" it
294 		(RO) When a CXL decoder is of devtype "cxl_decoder_endpoint",
305 		(RW) When a CXL decoder is of devtype "cxl_decoder_endpoint" it
390 		values are determined by the CXL spec and the participating
437 		(RO) A region is a contiguous partition of a CXL root decoder