driver-api/cxl/memory-devices.rst

8 A Compute Express Link Memory Device is a CXL component that implements the
9 CXL.mem protocol. It contains some amount of volatile memory, persistent memory,
17 CXL Bus: Theory of Operation
20 logical device, the CXL subsystem is tasked to take PCIe and ACPI objects and
21 assemble them into a CXL.mem decode topology. The need for runtime configuration
22 of the CXL.mem topology is also similar to RAID in that different environments
26 and disable any striping in the CXL.mem topology.
28 Platform firmware enumerates a menu of interleave options at the "CXL root port"
29 (Linux term for the top of the CXL decode topology). From there, PCIe topology
38 Here is a sample listing of a CXL topology defined by 'cxl_test'. The 'cxl_test'
39 module generates an emulated CXL topology of 2 Host Bridges each with 2 Root
184 'struct cxl_port' object. A 'cxl_port' is a device that can decode CXL.mem to
191 metadata that determine RAID set assembly. CXL Port topology and CXL Port link
192 status is metadata for CXL.mem set assembly. The CXL Port topology is enumerated
193 by the arrival of a CXL.mem device. I.e. unless and until the PCIe core attaches
194 the cxl_pci driver to a CXL Memory Expander there is no role for CXL Port
196 the Linux PCI core to tear down switch-level CXL resources because the endpoint
249 ...which queries the CXL topology to ask "given CXL Memory Expander with a kernel
251 participate". A given expander can participate in multiple CXL.mem interleave
317 This section covers the driver infrastructure for a CXL memory device.
319 CXL Memory Device
331 CXL Port
336 CXL Core
365 CXL Regions
376 CXL IOCTL Interface