| /openbmc/linux/arch/arm/mm/ |
| H A D | proc-sa110.S | diff 8799ee9f49f6171fd58f4d64f8c067ca49006a5d Thu Jun 29 12:24:21 CDT 2006 Russell King <rmk@dyn-67.arm.linux.org.uk> [ARM] Set bit 4 on section mappings correctly depending on CPU
On some CPUs, bit 4 of section mappings means "update the
cache when written to". On others, this bit is required to
be one, and others it's required to be zero. Finally, on
ARMv6 and above, setting it turns on "no execute" and prevents
speculative prefetches.
With all these combinations, no one value fits all CPUs, so we
have to pick a value depending on the CPU type, and the area
we're mapping.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| H A D | proc-arm720.S | diff 8799ee9f49f6171fd58f4d64f8c067ca49006a5d Thu Jun 29 12:24:21 CDT 2006 Russell King <rmk@dyn-67.arm.linux.org.uk> [ARM] Set bit 4 on section mappings correctly depending on CPU
On some CPUs, bit 4 of section mappings means "update the
cache when written to". On others, this bit is required to
be one, and others it's required to be zero. Finally, on
ARMv6 and above, setting it turns on "no execute" and prevents
speculative prefetches.
With all these combinations, no one value fits all CPUs, so we
have to pick a value depending on the CPU type, and the area
we're mapping.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| H A D | proc-arm922.S | diff 8799ee9f49f6171fd58f4d64f8c067ca49006a5d Thu Jun 29 12:24:21 CDT 2006 Russell King <rmk@dyn-67.arm.linux.org.uk> [ARM] Set bit 4 on section mappings correctly depending on CPU
On some CPUs, bit 4 of section mappings means "update the
cache when written to". On others, this bit is required to
be one, and others it's required to be zero. Finally, on
ARMv6 and above, setting it turns on "no execute" and prevents
speculative prefetches.
With all these combinations, no one value fits all CPUs, so we
have to pick a value depending on the CPU type, and the area
we're mapping.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| H A D | proc-arm1022.S | diff 8799ee9f49f6171fd58f4d64f8c067ca49006a5d Thu Jun 29 12:24:21 CDT 2006 Russell King <rmk@dyn-67.arm.linux.org.uk> [ARM] Set bit 4 on section mappings correctly depending on CPU
On some CPUs, bit 4 of section mappings means "update the
cache when written to". On others, this bit is required to
be one, and others it's required to be zero. Finally, on
ARMv6 and above, setting it turns on "no execute" and prevents
speculative prefetches.
With all these combinations, no one value fits all CPUs, so we
have to pick a value depending on the CPU type, and the area
we're mapping.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| H A D | proc-arm1026.S | diff 8799ee9f49f6171fd58f4d64f8c067ca49006a5d Thu Jun 29 12:24:21 CDT 2006 Russell King <rmk@dyn-67.arm.linux.org.uk> [ARM] Set bit 4 on section mappings correctly depending on CPU
On some CPUs, bit 4 of section mappings means "update the
cache when written to". On others, this bit is required to
be one, and others it's required to be zero. Finally, on
ARMv6 and above, setting it turns on "no execute" and prevents
speculative prefetches.
With all these combinations, no one value fits all CPUs, so we
have to pick a value depending on the CPU type, and the area
we're mapping.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| H A D | proc-arm925.S | diff 8799ee9f49f6171fd58f4d64f8c067ca49006a5d Thu Jun 29 12:24:21 CDT 2006 Russell King <rmk@dyn-67.arm.linux.org.uk> [ARM] Set bit 4 on section mappings correctly depending on CPU
On some CPUs, bit 4 of section mappings means "update the
cache when written to". On others, this bit is required to
be one, and others it's required to be zero. Finally, on
ARMv6 and above, setting it turns on "no execute" and prevents
speculative prefetches.
With all these combinations, no one value fits all CPUs, so we
have to pick a value depending on the CPU type, and the area
we're mapping.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| H A D | proc-sa1100.S | diff 8799ee9f49f6171fd58f4d64f8c067ca49006a5d Thu Jun 29 12:24:21 CDT 2006 Russell King <rmk@dyn-67.arm.linux.org.uk> [ARM] Set bit 4 on section mappings correctly depending on CPU
On some CPUs, bit 4 of section mappings means "update the
cache when written to". On others, this bit is required to
be one, and others it's required to be zero. Finally, on
ARMv6 and above, setting it turns on "no execute" and prevents
speculative prefetches.
With all these combinations, no one value fits all CPUs, so we
have to pick a value depending on the CPU type, and the area
we're mapping.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| H A D | proc-arm1020e.S | diff 8799ee9f49f6171fd58f4d64f8c067ca49006a5d Thu Jun 29 12:24:21 CDT 2006 Russell King <rmk@dyn-67.arm.linux.org.uk> [ARM] Set bit 4 on section mappings correctly depending on CPU
On some CPUs, bit 4 of section mappings means "update the
cache when written to". On others, this bit is required to
be one, and others it's required to be zero. Finally, on
ARMv6 and above, setting it turns on "no execute" and prevents
speculative prefetches.
With all these combinations, no one value fits all CPUs, so we
have to pick a value depending on the CPU type, and the area
we're mapping.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| H A D | proc-arm1020.S | diff 8799ee9f49f6171fd58f4d64f8c067ca49006a5d Thu Jun 29 12:24:21 CDT 2006 Russell King <rmk@dyn-67.arm.linux.org.uk> [ARM] Set bit 4 on section mappings correctly depending on CPU
On some CPUs, bit 4 of section mappings means "update the
cache when written to". On others, this bit is required to
be one, and others it's required to be zero. Finally, on
ARMv6 and above, setting it turns on "no execute" and prevents
speculative prefetches.
With all these combinations, no one value fits all CPUs, so we
have to pick a value depending on the CPU type, and the area
we're mapping.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| H A D | proc-arm920.S | diff 8799ee9f49f6171fd58f4d64f8c067ca49006a5d Thu Jun 29 12:24:21 CDT 2006 Russell King <rmk@dyn-67.arm.linux.org.uk> [ARM] Set bit 4 on section mappings correctly depending on CPU
On some CPUs, bit 4 of section mappings means "update the
cache when written to". On others, this bit is required to
be one, and others it's required to be zero. Finally, on
ARMv6 and above, setting it turns on "no execute" and prevents
speculative prefetches.
With all these combinations, no one value fits all CPUs, so we
have to pick a value depending on the CPU type, and the area
we're mapping.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| H A D | proc-arm926.S | diff 8799ee9f49f6171fd58f4d64f8c067ca49006a5d Thu Jun 29 12:24:21 CDT 2006 Russell King <rmk@dyn-67.arm.linux.org.uk> [ARM] Set bit 4 on section mappings correctly depending on CPU
On some CPUs, bit 4 of section mappings means "update the
cache when written to". On others, this bit is required to
be one, and others it's required to be zero. Finally, on
ARMv6 and above, setting it turns on "no execute" and prevents
speculative prefetches.
With all these combinations, no one value fits all CPUs, so we
have to pick a value depending on the CPU type, and the area
we're mapping.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| H A D | proc-xsc3.S | diff 8799ee9f49f6171fd58f4d64f8c067ca49006a5d Thu Jun 29 12:24:21 CDT 2006 Russell King <rmk@dyn-67.arm.linux.org.uk> [ARM] Set bit 4 on section mappings correctly depending on CPU
On some CPUs, bit 4 of section mappings means "update the
cache when written to". On others, this bit is required to
be one, and others it's required to be zero. Finally, on
ARMv6 and above, setting it turns on "no execute" and prevents
speculative prefetches.
With all these combinations, no one value fits all CPUs, so we
have to pick a value depending on the CPU type, and the area
we're mapping.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| H A D | proc-xscale.S | diff 8799ee9f49f6171fd58f4d64f8c067ca49006a5d Thu Jun 29 12:24:21 CDT 2006 Russell King <rmk@dyn-67.arm.linux.org.uk> [ARM] Set bit 4 on section mappings correctly depending on CPU
On some CPUs, bit 4 of section mappings means "update the
cache when written to". On others, this bit is required to
be one, and others it's required to be zero. Finally, on
ARMv6 and above, setting it turns on "no execute" and prevents
speculative prefetches.
With all these combinations, no one value fits all CPUs, so we
have to pick a value depending on the CPU type, and the area
we're mapping.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| H A D | proc-v6.S | diff 8799ee9f49f6171fd58f4d64f8c067ca49006a5d Thu Jun 29 12:24:21 CDT 2006 Russell King <rmk@dyn-67.arm.linux.org.uk> [ARM] Set bit 4 on section mappings correctly depending on CPU
On some CPUs, bit 4 of section mappings means "update the
cache when written to". On others, this bit is required to
be one, and others it's required to be zero. Finally, on
ARMv6 and above, setting it turns on "no execute" and prevents
speculative prefetches.
With all these combinations, no one value fits all CPUs, so we
have to pick a value depending on the CPU type, and the area
we're mapping.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| /openbmc/linux/arch/arm/kernel/ |
| H A D | asm-offsets.c | diff 8799ee9f49f6171fd58f4d64f8c067ca49006a5d Thu Jun 29 12:24:21 CDT 2006 Russell King <rmk@dyn-67.arm.linux.org.uk> [ARM] Set bit 4 on section mappings correctly depending on CPU
On some CPUs, bit 4 of section mappings means "update the
cache when written to". On others, this bit is required to
be one, and others it's required to be zero. Finally, on
ARMv6 and above, setting it turns on "no execute" and prevents
speculative prefetches.
With all these combinations, no one value fits all CPUs, so we
have to pick a value depending on the CPU type, and the area
we're mapping.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| H A D | head.S | diff 8799ee9f49f6171fd58f4d64f8c067ca49006a5d Thu Jun 29 12:24:21 CDT 2006 Russell King <rmk@dyn-67.arm.linux.org.uk> [ARM] Set bit 4 on section mappings correctly depending on CPU
On some CPUs, bit 4 of section mappings means "update the
cache when written to". On others, this bit is required to
be one, and others it's required to be zero. Finally, on
ARMv6 and above, setting it turns on "no execute" and prevents
speculative prefetches.
With all these combinations, no one value fits all CPUs, so we
have to pick a value depending on the CPU type, and the area
we're mapping.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|