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/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dti,phy-am654-serdes.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/ti,phy-am654-serdes.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI AM654 SERDES
10 This binding describes the TI AM654 SERDES. AM654 SERDES can be configured
14 - Kishon Vijay Abraham I <kishon@ti.com>
19 - ti,phy-am654-serdes
24 reg-names:
26 - const: serdes
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/openbmc/u-boot/Documentation/devicetree/bindings/misc/
H A Dfsl,mpc83xx-serdes.txt1 MPC83xx SerDes controller devices
3 MPC83xx SoCs contain a built-in SerDes controller that determines which
4 protocols (SATA, PCI Express, SGMII, ...) are used on the system's serdes lines
8 - compatible: must be "fsl,mpc83xx-serdes"
9 - reg: must point to the serdes controller's register map
10 - proto: selects for which protocol the serdes lines are configured. One of
11 "sata", "pex", "pex-x2", "sgmii"
12 - serdes-clk: determines the frequency the serdes lines are configured for. One
14 - vdd: determines whether 1.0V core VDD is used or not
18 SERDES: serdes@e3000 {
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/openbmc/u-boot/drivers/soc/keystone/
H A Dkeystone_serdes.c1 // SPDX-License-Identifier: GPL-2.0+
3 * TI serdes driver for keystone2.
11 #include <asm/ti-common/keystone_serdes.h>
42 enum ks2_serdes_clock clk; member
49 /* SERDES PHY lane enable configuration value, indexed by PHY interface */
55 /* SERDES PHY PLL enable configuration value, indexed by PHY interface */
62 * Array to hold all possible serdes configurations.
67 .clk = SERDES_CLOCK_156P25M,
130 ks2_serdes_cfg_setup(base, cfg->cmu, SERDES_CMU_CFG_NUM); in ks2_serdes_init_cfg()
131 ks2_serdes_cfg_setup(base, cfg->comlane, SERDES_COMLANE_CFG_NUM); in ks2_serdes_init_cfg()
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/openbmc/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-intel.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 /* SERDES Register */
16 /* SERDES defines */
17 #define SERDES_PLL_CLK BIT(0) /* PLL clk valid signal */
18 #define SERDES_PHY_RX_CLK BIT(1) /* PSE SGMII PHY rx clk */
19 #define SERDES_RST BIT(2) /* Serdes Reset */
20 #define SERDES_PWR_ST_MASK GENMASK(6, 4) /* Serdes Power state*/
40 /* Cross-timestamping defines */
H A Ddwmac-intel.c1 // SPDX-License-Identifier: GPL-2.0
5 #include <linux/clk-provider.h>
8 #include "dwmac-intel.h"
14 int mdio_adhoc_addr; /* mdio address for serdes & etc */
44 int func = PCI_FUNC(pdev->devfn); in stmmac_pci_find_phy_addr()
49 return -ENODEV; in stmmac_pci_find_phy_addr()
51 dmi_data = dmi_id->driver_data; in stmmac_pci_find_phy_addr()
52 func_data = dmi_data->func; in stmmac_pci_find_phy_addr()
54 for (n = 0; n < dmi_data->nfuncs; n++, func_data++) in stmmac_pci_find_phy_addr()
55 if (func_data->func == func) in stmmac_pci_find_phy_addr()
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/openbmc/u-boot/arch/arm/include/asm/ti-common/
H A Dkeystone_serdes.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Texas Instruments Keystone SerDes driver
12 /* SERDES Reference clock */
21 /* SERDES Lane Baud Rate */
31 /* SERDES Lane Rate Mode */
38 /* SERDES PHY TYPE */
41 SERDES_PHY_PCSR, /* XGE SERDES */
45 enum ks2_serdes_clock clk; member
52 int ks2_serdes_init(u32 base, struct ks2_serdes *serdes, u32 num_lanes);
/openbmc/linux/drivers/phy/xilinx/
H A Dphy-zynqmp.c1 // SPDX-License-Identifier: GPL-2.0
3 * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
5 * Copyright (C) 2018-2020 Xilinx Inc.
15 #include <linux/clk.h>
26 #include <dt-bindings/phy/phy.h>
32 /* TX De-emphasis parameters */
190 * struct xpsgtr_ssc - structure to hold SSC settings for a lane
192 * @pll_ref_clk: value to be written to register for corresponding ref clk rate
204 * struct xpsgtr_phy - representation of a lane
224 * struct xpsgtr_dev - representation of a ZynMP GT device
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/openbmc/linux/drivers/phy/ti/
H A Dphy-j721e-wiz.c1 // SPDX-License-Identifier: GPL-2.0
3 * Wrapper driver for SERDES used in J721E
5 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/phy/phy-ti.h>
12 #include <linux/clk.h>
13 #include <linux/clk-provider.h>
25 #include <linux/reset-controller.h>
35 /* SERDES offsets */
125 [TI_WIZ_PLL0_REFCLK] = "pll0-refclk",
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H A Dphy-am654-serdes.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe SERDES driver for AM654x SoC
5 * Copyright (C) 2018 - 2019 Texas Instruments Incorporated - http://www.ti.com/
9 #include <dt-bindings/phy/phy.h>
10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
142 /* Mid-speed initial calibration control */
145 /* High-speed initial calibration control */
148 /* Mid-speed recalibration control */
151 /* High-speed recalibration control */
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/openbmc/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qmp-pcie-msm8996.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk.h>
7 #include <linux/clk-provider.h>
22 #include "phy-qcom-qmp.h"
66 /* set of registers with offsets different per-PHY */
169 /* struct qmp_phy_cfg - per-PHY initialization config */
174 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
199 * struct qmp_phy - per-lane phy descriptor
203 * @serdes: iomapped memory space for phy's serdes (i.e. PLL)
215 void __iomem *serdes; member
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H A Dphy-qcom-qmp-pcie.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk.h>
7 #include <linux/clk-provider.h>
25 #include "phy-qcom-qmp.h"
26 #include "phy-qcom-qmp-pcs-misc-v3.h"
27 #include "phy-qcom-qmp-pcs-pcie-v4.h"
28 #include "phy-qcom-qmp-pcs-pcie-v4_20.h"
29 #include "phy-qcom-qmp-pcs-pcie-v5.h"
30 #include "phy-qcom-qmp-pcs-pcie-v5_20.h"
31 #include "phy-qcom-qmp-pcs-pcie-v6.h"
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H A Dphy-qcom-qmp-usb-legacy.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk.h>
7 #include <linux/clk-provider.h>
23 #include "phy-qcom-qmp.h"
24 #include "phy-qcom-qmp-pcs-misc-v3.h"
25 #include "phy-qcom-qmp-pcs-usb-v4.h"
26 #include "phy-qcom-qmp-pcs-usb-v5.h"
89 /* set of registers with offsets different per-PHY */
501 u16 serdes; member
508 /* struct qmp_phy_cfg - per-PHY initialization config */
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H A Dphy-qcom-qmp-ufs.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk.h>
7 #include <linux/clk-provider.h>
23 #include "phy-qcom-qmp.h"
24 #include "phy-qcom-qmp-pcs-ufs-v2.h"
25 #include "phy-qcom-qmp-pcs-ufs-v3.h"
26 #include "phy-qcom-qmp-pcs-ufs-v4.h"
27 #include "phy-qcom-qmp-pcs-ufs-v5.h"
28 #include "phy-qcom-qmp-pcs-ufs-v6.h"
30 #include "phy-qcom-qmp-qserdes-txrx-ufs-v6.h"
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/openbmc/u-boot/drivers/misc/
H A Dmpc83xx_serdes.c1 // SPDX-License-Identifier: GPL-2.0+
6 * base on the MPC83xx serdes initialization, which is
20 * struct mpc83xx_serdes_priv - Private structure for MPC83xx serdes
22 * @rfcks: Variable to keep the serdes reference clock selection set during
31 * setup_sata() - Configure the SerDes device to SATA mode
39 setbits_be32(&priv->regs->srdsrstctl, SRDSRSTCTL_SATA_RESET); in setup_sata()
41 clrbits_be32(&priv->regs->srdsrstctl, SRDSRSTCTL_SATA_RESET); in setup_sata()
44 clrsetbits_be32(&priv->regs->srdscr0, in setup_sata()
49 clrbits_be32(&priv->regs->srdscr1, SRDSCR1_PLLBW); in setup_sata()
52 clrsetbits_be32(&priv->regs->srdscr2, in setup_sata()
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/openbmc/u-boot/board/freescale/bsc9132qds/
H A DREADME2 --------
4 Microcell, Picocell, and Enterprise-Femto base station market subsegments.
7 core technologies with MAPLE-B2P baseband acceleration processing elements
15 - Power Architecture subsystem including two e500 processors with
16 512-Kbyte shared L2 cache
17 - Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2
19 - 32 Kbyte of shared M3 memory
20 - The Multi Accelerator Platform Engine for Pico BaseStation Baseband
21 Processing (MAPLE-B2P)
22 - Two DDR3/3L memory interfaces with 32-bit data width (40 bits including
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/openbmc/linux/drivers/phy/samsung/
H A Dphy-exynos5250-sata.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Samsung SATA SerDes(PHY) driver
10 #include <linux/clk.h>
50 struct clk *phyclk;
66 return -EFAULT; in wait_for_reg_status()
73 return regmap_update_bits(sata_phy->pmureg, SATAPHY_CONTROL_OFFSET, in exynos_sata_phy_power_on()
82 return regmap_update_bits(sata_phy->pmureg, SATAPHY_CONTROL_OFFSET, in exynos_sata_phy_power_off()
94 ret = regmap_update_bits(sata_phy->pmureg, SATAPHY_CONTROL_OFFSET, in exynos_sata_phy_init()
97 dev_err(&sata_phy->phy->dev, "phy init failed\n"); in exynos_sata_phy_init()
99 writel(val, sata_phy->regs + EXYNOS5_SATA_RESET); in exynos_sata_phy_init()
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/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1028a-kontron-sl28-var1.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Device Tree file for the Kontron SMARC-sAL28 board.
8 * None of the four SerDes lanes are used by the module, instead they are
15 /dts-v1/;
16 #include "fsl-ls1028a-kontron-sl28.dts"
17 #include <dt-bindings/net/qca-ar803x.h>
20 model = "Kontron SMARC-sAL28 (4 Lanes)";
21 compatible = "kontron,sl28-var1", "kontron,sl28", "fsl,ls1028a";
26 /delete-node/ ethernet-phy@5;
28 phy0: ethernet-phy@4 {
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/openbmc/linux/drivers/phy/microchip/
H A Dsparx5_serdes.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Microchip Sparx5 Switch SerDes driver
7 * https://github.com/microchip-ung/sparx-5_reginfo
9 …* https://ww1.microchip.com/downloads/en/DeviceDoc/SparX-5_Family_L2L3_Enterprise_10G_Ethernet_Swi…
18 #include <linux/clk.h>
104 u8 if_width; /* UDL if-width: 10/16/20/32/64 */
106 enum sparx5_10g28cmu_mode cmu_sel; /* Device/Mode serdes uses */
107 bool no_pwrcycle:1; /* Omit initial power-cycle */
236 enum sparx5_10g28cmu_mode cmu_sel; /* Device/Mode serdes uses */
246 bool no_pwrcycle:1; /* Omit initial power-cycle */
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/openbmc/u-boot/arch/arm/mach-mvebu/serdes/a38x/
H A Dhigh_speed_env_spec.c1 // SPDX-License-Identifier: GPL-2.0
24 * serdes_seq_db - holds all serdes sequences, their size and the
30 #define ENDED_OK "High speed PHY - Ended Successfully\n"
42 * serdes_lane_in_use_count contains the exact amount of serdes lanes
63 /* Selector mapping for A380-A0 and A390-Z1 */
111 "DEFAULT SERDES",
158 /* Rx clk and Tx clk select non-inverted mode */
177 /* Rx clk and Tx clk select non-inverted mode */
185 /* SATA and SGMII - power up seq */
202 /* SATA and SGMII - speed config seq */
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/openbmc/u-boot/arch/arm/mach-mvebu/serdes/axp/
H A Dhigh_speed_env_lib.c1 // SPDX-License-Identifier: GPL-2.0
17 #define ENDED_OK "High speed PHY - Ended Successfully\n"
131 /* SERDES module (only PEX model is supported now) */ in board_modules_scan()
192 return &serdes_info_tbl[board_id - BOARD_ID_BASE][serdes_cfg_val]; in board_serdes_cfg_get()
213 return (info->line0_7 >> (line_num << 2)) & 0xF; in get_line_cfg()
215 return (info->line8_15 >> ((line_num - 8) << 2)) & 0xF; in get_line_cfg()
235 * non-established PCIe links (link down). Especially under certain
237 * To enable a board-specific detection pulse width this weak
239 * overwritten if needed by a board-specific version. If the board
240 * code does not provide a non-weak version of this variable, the
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/openbmc/linux/drivers/phy/marvell/
H A Dphy-mvebu-a3700-comphy.c1 // SPDX-License-Identifier: GPL-2.0
11 * Structure inspired from phy-mvebu-cp110-comphy.c written by Antoine Tenart.
17 #include <linux/clk.h>
41 * since the registers are 16-bit.
184 #define COMPHY_PHY_REG(lane, reg) (((1 - (lane)) * 0x28) + ((reg) & 0x3f))
301 /*-----------------------------------------------------------*/
392 priv->lane2_phy_indirect + COMPHY_LANE2_INDIR_ADDR); in comphy_set_indirect()
393 comphy_reg_set(priv->lane2_phy_indirect + COMPHY_LANE2_INDIR_DATA, in comphy_set_indirect()
400 if (lane->id == 2) { in comphy_lane_reg_set()
402 comphy_set_indirect(lane->priv, in comphy_lane_reg_set()
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/openbmc/linux/arch/mips/boot/dts/mscc/
H A Docelot.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 #address-cells = <1>;
6 #size-cells = <1>;
10 #address-cells = <1>;
11 #size-cells = <0>;
25 cpuintc: interrupt-controller {
26 #address-cells = <0>;
27 #interrupt-cells = <1>;
28 interrupt-controller;
29 compatible = "mti,cpu-interrupt-controller";
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/openbmc/u-boot/board/freescale/t1040qds/
H A Dt1040qds.c1 // SPDX-License-Identifier: GPL-2.0+
32 struct cpu_type *cpu = gd->arch.cpu; in checkboard()
37 printf("Board: %sQDS, ", cpu->name); in checkboard()
62 * Display the actual SERDES reference clocks as configured by the in checkboard()
65 * values that the SERDES expects (or vice versa). For now, however, in checkboard()
69 puts("SERDES Reference: "); in checkboard()
99 * TDMRiser uses QE-TDM in qe_board_setup()
133 * Remap Boot flash + PROMJET region to caching-inhibited in board_early_init_r()
137 /* Flush d-cache and invalidate i-cache of any FLASH data */ in board_early_init_r()
141 if (flash_esel == -1) { in board_early_init_r()
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/openbmc/u-boot/board/freescale/t4qds/
H A Dt4240qds.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2009-2012 Freescale Semiconductor, Inc.
43 struct cpu_type *cpu = gd->arch.cpu; in checkboard()
46 printf("Board: %sQDS, ", cpu->name); in checkboard()
69 * Display the actual SERDES reference clocks as configured by the in checkboard()
72 * values that the SERDES expects (or vice versa). For now, however, in checkboard()
76 puts("SERDES Reference Clocks: "); in checkboard()
81 unsigned int clock = (sw >> (6 - 2 * i)) & 3; in checkboard()
83 printf("SERDES%u=%sMHz ", i+1, freq[clock]); in checkboard()
124 return -1; in read_voltage()
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/openbmc/linux/arch/arm64/boot/dts/microchip/
H A Dsparx5.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/clock/microchip,sparx5.h>
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <1>;
23 stdout-path = "serial0:115200n8";
27 #address-cells = <1>;
28 #size-cells = <0>;
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