1 // SPDX-License-Identifier: GPL-2.0+
3  * Copyright 2009-2012 Freescale Semiconductor, Inc.
43 	struct cpu_type *cpu = gd->arch.cpu;  in checkboard()
46 	printf("Board: %sQDS, ", cpu->name);  in checkboard()
69 	 * Display the actual SERDES reference clocks as configured by the  in checkboard()
72 	 * values that the SERDES expects (or vice versa).  For now, however,  in checkboard()
76 	puts("SERDES Reference Clocks: ");  in checkboard()
81 		unsigned int clock = (sw >> (6 - 2 * i)) & 3;  in checkboard()
83 		printf("SERDES%u=%sMHz ", i+1, freq[clock]);  in checkboard()
124 			return -1;  in read_voltage()
147 	for (timeout = 0; abs(vdd_last - vdd_current) <= 4 &&  in wait_for_voltage_change()
153 		return -1;  in wait_for_voltage_change()
170 	for (timeout = 0; abs(vdd_last - vdd_current) >= 4 &&  in wait_for_voltage_stable()
178 		return -1;  in wait_for_voltage_stable()
192 		return -1;  in set_voltage()
198 		return -1;  in set_voltage()
252 		ret = -1;  in adjust_vdd()
257 	fusesr = in_be32(&gur->dcfg_fusesr);  in adjust_vdd()
295 	vdd_current = 121250 - (vid_current - 0x40) * 625;  in adjust_vdd()
306 		ret = -1;  in adjust_vdd()
326 		vid_current--;  in adjust_vdd()
332 		ret = -1;  in adjust_vdd()
340 /* Configure Crossbar switches for Front-Side SerDes Ports */
351 	srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &  in config_frontside_crossbar_vsc3316()
383 	srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &  in config_frontside_crossbar_vsc3316()
430 	srds_prtcl_s3 = in_be32(&gur->rcwsr[4]) &  in config_backside_crossbar_mux()
472 		return -1;  in config_backside_crossbar_mux()
475 	srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) &  in config_backside_crossbar_mux()
520 		return -1;  in config_backside_crossbar_mux()
532 	 * Remap Boot flash + PROMJET region to caching-inhibited  in board_early_init_r()
536 	/* Flush d-cache and invalidate i-cache of any FLASH data */  in board_early_init_r()
540 	if (flash_esel == -1) {  in board_early_init_r()
563 	/* Configure board SERDES ports crossbar */  in board_early_init_r()
648 		unsigned int clock = (sw >> (6 - 2 * i)) & 3;  in misc_init_r()
667 		pllcr0 = srds_regs->bank[0].pllcr0;  in misc_init_r()
670 			printf("Warning: SERDES%u expects reference clock %sMHz, but actual is %sMHz\n",  in misc_init_r()
723 	static const char * const clk[] = {"66.67", "100", "125", "133.33"};  in board_detail()  local
738 	printf("XVDD        = 1.%d V\n", ((brdcfg[8] & 0xf) - 4) * 5 + 25);  in board_detail()
742 	       clk[(brdcfg[11] >> 2) & 0x3], clk[brdcfg[11] & 3]);  in board_detail()
750 		puts("8-bit NOR\n");  in board_detail()
754 		puts("16-bit NOR\n");  in board_detail()
760 		puts("SPI 16-bit addressing\n");  in board_detail()
763 		puts("SPI 24-bit addressing\n");  in board_detail()
775 		puts("8-bit NAND, 2KB\n");  in board_detail()
779 			puts("Hard-coded RCW\n");  in board_detail()
781 			puts("8-bit NAND, 4KB\n");  in board_detail()
860 	puts("DIP switch (reverse-engineering)\n");  in qixis_dump_switch()
886 	"- override with the voltage specified in mV, eg. 1050"