1 // SPDX-License-Identifier: GPL-2.0+
6  * base on the MPC83xx serdes initialization, which is
20  * struct mpc83xx_serdes_priv - Private structure for MPC83xx serdes
22  * @rfcks: Variable to keep the serdes reference clock selection set during
31  * setup_sata() - Configure the SerDes device to SATA mode
39 	setbits_be32(&priv->regs->srdsrstctl, SRDSRSTCTL_SATA_RESET);  in setup_sata()
41 	clrbits_be32(&priv->regs->srdsrstctl, SRDSRSTCTL_SATA_RESET);  in setup_sata()
44 	clrsetbits_be32(&priv->regs->srdscr0,  in setup_sata()
49 	clrbits_be32(&priv->regs->srdscr1, SRDSCR1_PLLBW);  in setup_sata()
52 	clrsetbits_be32(&priv->regs->srdscr2,  in setup_sata()
57 	out_be32(&priv->regs->srdscr3,  in setup_sata()
62 	out_be32(&priv->regs->srdscr4, priv->rfcks | SRDSCR4_PROT_SATA);  in setup_sata()
66  * setup_pex() - Configure the SerDes device to PCI Express mode
75 	setbits_be32(&priv->regs->srdscr1, SRDSCR1_PLLBW);  in setup_pex()
78 	clrsetbits_be32(&priv->regs->srdscr2,  in setup_pex()
83 	out_be32(&priv->regs->srdscr3, SRDSCR3_SDFM_SATA_PEX);  in setup_pex()
87 		out_be32(&priv->regs->srdscr4,  in setup_pex()
88 			 priv->rfcks | SRDSCR4_PROT_PEX | SRDSCR4_PLANE_X2);  in setup_pex()
90 		out_be32(&priv->regs->srdscr4,  in setup_pex()
91 			 priv->rfcks | SRDSCR4_PROT_PEX);  in setup_pex()
95  * setup_sgmii() - Configure the SerDes device to SGMII mode
103 	clrbits_be32(&priv->regs->srdscr1, SRDSCR1_PLLBW);  in setup_sgmii()
106 	clrsetbits_be32(&priv->regs->srdscr2,  in setup_sgmii()
111 	out_be32(&priv->regs->srdscr3, 0);  in setup_sgmii()
114 	out_be32(&priv->regs->srdscr4, priv->rfcks | SRDSCR4_PROT_SGMII);  in setup_sgmii()
123 	priv->regs = map_sysmem(dev_read_addr(dev),  in mpc83xx_serdes_probe()
126 	switch (dev_read_u32_default(dev, "serdes-clk", -1)) {  in mpc83xx_serdes_probe()
128 		priv->rfcks = SRDSCR4_RFCKS_100;  in mpc83xx_serdes_probe()
131 		priv->rfcks = SRDSCR4_RFCKS_125;  in mpc83xx_serdes_probe()
134 		priv->rfcks = SRDSCR4_RFCKS_150;  in mpc83xx_serdes_probe()
137 		debug("%s: Could not read serdes clock value\n", dev->name);  in mpc83xx_serdes_probe()
138 		return -EINVAL;  in mpc83xx_serdes_probe()
146 		clrbits_be32(&priv->regs->srdscr0, SRDSCR0_DPP_1V2);  in mpc83xx_serdes_probe()
149 		clrbits_be32(&priv->regs->srdscr0, SRDSCR2_VDD_1V2);  in mpc83xx_serdes_probe()
159 	} else if (!strcmp(proto, "pex-x2")) {  in mpc83xx_serdes_probe()
164 		debug("%s: Invalid protocol value %s\n", dev->name, proto);  in mpc83xx_serdes_probe()
165 		return -EINVAL;  in mpc83xx_serdes_probe()
169 	setbits_be32(&priv->regs->srdsrstctl, SRDSRSTCTL_RST);  in mpc83xx_serdes_probe()
175 	{ .compatible = "fsl,mpc83xx-serdes" },