Lines Matching +full:serdes +full:- +full:clk
2 --------
4 Microcell, Picocell, and Enterprise-Femto base station market subsegments.
7 core technologies with MAPLE-B2P baseband acceleration processing elements
15 - Power Architecture subsystem including two e500 processors with
16 512-Kbyte shared L2 cache
17 - Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2
19 - 32 Kbyte of shared M3 memory
20 - The Multi Accelerator Platform Engine for Pico BaseStation Baseband
21 Processing (MAPLE-B2P)
22 - Two DDR3/3L memory interfaces with 32-bit data width (40 bits including
24 - Dedicated security engine featuring trusted boot
25 - Two DMA controllers
26 - OCNDMA with four bidirectional channels
27 - SysDMA with sixteen bidirectional channels
28 - Interfaces
29 - Four-lane SerDes PHY
30 - PCI Express controller complies with the PEX Specification-Rev 2.0
31 - Two Common Public Radio Interface (CPRI) controller lanes
32 - High-speed USB 2.0 host and device controller with ULPI interface
33 - Enhanced secure digital (SD/MMC) host controller (eSDHC)
34 - Antenna interface controller (AIC), supporting four industry
36 - ADI lanes support both full duplex FDD support & half duplex TDD
37 - Universal Subscriber Identity Module (USIM) interface that
38 facilitates communication to SIM cards or Eurochip pre-paid phone
40 - Two DUART, two eSPI, and two I2C controllers
41 - Integrated Flash memory controller (IFC)
42 - GPIO
43 - Sixteen 32-bit timers
46 - 32 KB, 8-way, level 1 instruction cache (L1 ICache)
47 - 32 KB, 8-way, level 1 data cache (L1 DCache)
48 - 512 KB, 8-way, level 2 unified instruction/data cache (L2 cache/M2 memory)
49 - Memory management unit (MMU)
50 - Global interrupt controller ( GIC)
51 - Debug and profiling unit (DPU)
52 - Two 32-bit quad timers
55 -------------------------
62 USB-ULPI
67 SerDes
72 --------------------------------
80 -----------------------
87 --------------------
90 Building U-Boot
91 --------------
92 To build the U-Boot for BSC9132QDS:
94 make BSC9132QDS_NOR_DDRCLK100 : For 100MHZ DDR CLK
95 make BSC9132QDS_NOR_DDRCLK133 : For 133MHZ DDR CLK
98 make BSC9132QDS_SPIFLASH_DDRCLK100 : For 100MHZ DDR CLK
99 make BSC9132QDS_SPIFLASH_DDRCLK133 : For 133MHZ DDR CLK
101 make BSC9132QDS_SDCARD_DDRCLK100 : For 100MHZ DDR CLK
102 make BSC9132QDS_SDCARD_DDRCLK133 : For 133MHZ DDR CLK
105 -----------
114 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M
124 ---------------
125 To place a new U-Boot image in the NAND flash and then boot
127 tftp 1000000 u-boot-nand.bin
133 ---------------------------------
137 dtc -b 0 -f -I dts -O dtb bsc9132qds.dts > bsc9132qds.dtb
141 linux-2.6/arch/powerpc/boot/dts/bsc9132qds.dts
144 -------------