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/openbmc/qemu/hw/misc/
H A Domap_clk.c4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
6 * Clocks data comes in part from arch/arm/mach-omap1/clock.h in Linux.
27 struct clk { struct
30 struct clk *parent; member
31 struct clk *child1; argument
32 struct clk *sibling; argument
42 int enabled; /* Is enabled, regardless of its input clk */ argument
50 static struct clk xtal_osc12m = { argument
56 static struct clk xtal_osc32k = {
62 static struct clk ck_ref = {
[all …]
/openbmc/linux/drivers/clk/
H A Dclk_test.c1 // SPDX-License-Identifier: GPL-2.0
3 * Kunit test for clk rate management
5 #include <linux/clk.h>
6 #include <linux/clk-provider.h>
9 #include "clk.h"
28 return ctx->rate; in clk_dummy_recalc_rate()
45 if (req->max_rate < ULONG_MAX) in clk_dummy_maximize_rate()
46 req->rate = req->max_rate; in clk_dummy_maximize_rate()
58 if (req->min_rate > 0) in clk_dummy_minimize_rate()
59 req->rate = req->min_rate; in clk_dummy_minimize_rate()
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H A Dclk-gate_test.c1 // SPDX-License-Identifier: GPL-2.0
3 * Kunit test for clk gate basic type
5 #include <linux/clk.h>
6 #include <linux/clk-provider.h>
16 pdev = platform_device_register_simple("test_gate_device", -1, NULL, 0); in clk_gate_register_test_dev()
19 ret = clk_hw_register_gate(&pdev->dev, "test_gate", NULL, 0, NULL, in clk_gate_register_test_dev()
31 struct clk_hw *parent; in clk_gate_register_test_parent_names() local
34 parent = clk_hw_register_fixed_rate(NULL, "test_parent", NULL, 0, in clk_gate_register_test_parent_names()
36 KUNIT_ASSERT_NOT_ERR_OR_NULL(test, parent); in clk_gate_register_test_parent_names()
41 KUNIT_EXPECT_PTR_EQ(test, parent, clk_hw_get_parent(ret)); in clk_gate_register_test_parent_names()
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H A Dclk.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
6 * Standard functionality for the common clock API. See Documentation/driver-api/clk.rst
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
11 #include <linux/clk/clk-conf.h>
25 #include "clk.h"
68 struct clk_core *parent; member
100 #include <trace/events/clk.h>
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/openbmc/u-boot/drivers/clk/renesas/
H A Dclk-rcar-gen3.c1 // SPDX-License-Identifier: GPL-2.0+
14 #include <clk-uclass.h>
20 #include <dt-bindings/clock/renesas-cpg-mssr.h>
22 #include "renesas-cpg-mssr.h"
23 #include "rcar-gen3-cpg.h"
62 *-------------------------------------------------------------------
88 static int gen3_clk_get_parent(struct gen3_clk_priv *priv, struct clk *clk, in gen3_clk_get_parent() argument
89 struct cpg_mssr_info *info, struct clk *parent) in gen3_clk_get_parent() argument
94 if (!renesas_clk_is_mod(clk)) { in gen3_clk_get_parent()
95 ret = renesas_clk_get_core(clk, info, &core); in gen3_clk_get_parent()
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H A Dclk-rcar-gen2.c1 // SPDX-License-Identifier: GPL-2.0+
14 #include <clk-uclass.h>
19 #include <dt-bindings/clock/renesas-cpg-mssr.h>
21 #include "renesas-cpg-mssr.h"
22 #include "rcar-gen2-cpg.h"
60 static int gen2_clk_enable(struct clk *clk) in gen2_clk_enable() argument
62 struct gen2_clk_priv *priv = dev_get_priv(clk->dev); in gen2_clk_enable()
64 return renesas_clk_endisable(clk, priv->base, true); in gen2_clk_enable()
67 static int gen2_clk_disable(struct clk *clk) in gen2_clk_disable() argument
69 struct gen2_clk_priv *priv = dev_get_priv(clk->dev); in gen2_clk_disable()
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/openbmc/linux/drivers/sh/clk/
H A Dcore.c4 * Copyright (C) 2005 - 2010 Paul Mundt
8 * Copyright (C) 2004 - 2008 Nokia Corporation
29 #include <linux/clk.h>
39 void clk_rate_table_build(struct clk *clk, in clk_rate_table_build() argument
49 clk->nr_freqs = nr_freqs; in clk_rate_table_build()
55 if (src_table->divisors && i < src_table->nr_divisors) in clk_rate_table_build()
56 div = src_table->divisors[i]; in clk_rate_table_build()
58 if (src_table->multipliers && i < src_table->nr_multipliers) in clk_rate_table_build()
59 mult = src_table->multipliers[i]; in clk_rate_table_build()
64 freq = clk->parent->rate * mult / div; in clk_rate_table_build()
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H A Dcpg.c5 * Copyright (C) 2010 - 2012 Paul Mundt
11 #include <linux/clk.h>
19 static unsigned int sh_clk_read(struct clk *clk) in sh_clk_read() argument
21 if (clk->flags & CLK_ENABLE_REG_8BIT) in sh_clk_read()
22 return ioread8(clk->mapped_reg); in sh_clk_read()
23 else if (clk->flags & CLK_ENABLE_REG_16BIT) in sh_clk_read()
24 return ioread16(clk->mapped_reg); in sh_clk_read()
26 return ioread32(clk->mapped_reg); in sh_clk_read()
29 static void sh_clk_write(int value, struct clk *clk) in sh_clk_write() argument
31 if (clk->flags & CLK_ENABLE_REG_8BIT) in sh_clk_write()
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/openbmc/linux/drivers/clk/tegra/
H A Dclk-tegra210-emc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved.
7 #include <linux/clk.h>
8 #include <linux/clk-provider.h>
9 #include <linux/clk/tegra.h>
15 #include "clk.h"
37 struct clk *parents[8];
57 value = readl_relaxed(emc->regs + CLK_SOURCE_EMC); in tegra210_clk_emc_get_parent()
70 * CCF assumes that neither the parent nor its rate will change during in tegra210_clk_emc_recalc_rate()
71 * ->set_rate(), so the parent rate passed in here was cached from the in tegra210_clk_emc_recalc_rate()
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H A Dclk-tegra124-emc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/clk/tegra/clk-emc.c
11 #include <linux/clk-provider.h>
12 #include <linux/clk.h>
14 #include <linux/clk/tegra.h>
27 #include "clk.h"
48 * When we change the timing to a timing with a parent that has the same
49 * clock source as the current parent, we must first change to a backup
68 struct clk *parent; member
75 struct clk *prev_parent;
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/openbmc/u-boot/drivers/clk/
H A Dclk_meson.c1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2018 - Beniamino Galvani <b.galvani@gmail.com>
4 * (C) Copyright 2018 - BayLibre, SAS
9 #include <asm/arch/clock-gx.h>
11 #include <clk-uclass.h>
16 #include <dt-bindings/clock/gxbb-clkc.h>
20 * - Can calculate clock frequency on a limited tree
21 * - Can Read muxes and basic dividers (0-based only)
22 * - Can enable/disable gates with limited propagation
23 * - Can reparent without propagation, only on muxes
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H A Dclk-ti-sci.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
8 * Loosely based on Linux kernel sci-clk.c...
14 #include <clk-uclass.h>
18 * struct ti_sci_clk_data - clock controller information structure
32 return -ENOMEM; in ti_sci_clk_probe()
35 data->sci = ti_sci_get_handle(dev); in ti_sci_clk_probe()
36 if (IS_ERR(data->sci)) in ti_sci_clk_probe()
37 return PTR_ERR(data->sci); in ti_sci_clk_probe()
42 static int ti_sci_clk_of_xlate(struct clk *clk, in ti_sci_clk_of_xlate() argument
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/openbmc/linux/drivers/clk/imx/
H A Dclk-scu.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2021 NXP
7 #include <dt-bindings/firmware/imx/rsrc.h>
8 #include <linux/arm-smccc.h>
10 #include <linux/clk-provider.h>
18 #include "clk-scu.h"
42 * struct clk_scu - Description of one SCU clock
53 struct clk_hw *parent; member
60 * struct clk_gpr_scu - Description of one SCU GPR clock
76 * struct imx_sc_msg_req_set_clock_rate - clock set rate protocol
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/openbmc/u-boot/drivers/clk/mediatek/
H A Dclk-mtk.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <clk-uclass.h>
15 #include "clk-mtk.h"
38 * In case the rate change propagation to parent clocks is undesirable,
39 * this function is recursively called to find the parent to calculate
42 static int mtk_clk_find_parent_rate(struct clk *clk, int id, in mtk_clk_find_parent_rate() argument
45 struct clk parent = { .id = id, }; in mtk_clk_find_parent_rate() local
51 return -ENODEV; in mtk_clk_find_parent_rate()
53 parent.dev = dev; in mtk_clk_find_parent_rate()
55 parent.dev = clk->dev; in mtk_clk_find_parent_rate()
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/openbmc/u-boot/drivers/clk/tegra/
H A Dtegra-car-clk.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <clk-uclass.h>
10 #include <asm/arch-tegra/clk_rst.h>
12 static int tegra_car_clk_request(struct clk *clk) in tegra_car_clk_request() argument
14 debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev, in tegra_car_clk_request()
15 clk->id); in tegra_car_clk_request()
25 if (clk->id >= PERIPH_ID_COUNT) in tegra_car_clk_request()
26 return -EINVAL; in tegra_car_clk_request()
31 static int tegra_car_clk_free(struct clk *clk) in tegra_car_clk_free() argument
33 debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev, in tegra_car_clk_free()
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/openbmc/u-boot/arch/arm/cpu/armv7/bcm281xx/
H A Dclk-bcm281xx.c1 // SPDX-License-Identifier: GPL-2.0+
8 * bcm281xx-specific clock tables
16 #include <asm/kona-common/clk.h>
17 #include "clk-core.h"
25 .clk = { \
27 .parent = clk_parent, \
43 DECLARE_REF_CLK(ref_104m, &ref_312m.clk, 104 * CLOCK_1M, 3);
44 DECLARE_REF_CLK(ref_52m, &ref_104m.clk, 52 * CLOCK_1M, 2);
45 DECLARE_REF_CLK(ref_13m, &ref_52m.clk, 13 * CLOCK_1M, 4);
47 DECLARE_REF_CLK(var_104m, &var_312m.clk, 104 * CLOCK_1M, 3);
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/openbmc/u-boot/arch/arm/cpu/armv7/bcm235xx/
H A Dclk-bcm235xx.c1 // SPDX-License-Identifier: GPL-2.0+
8 * bcm235xx-specific clock tables
16 #include <asm/kona-common/clk.h>
17 #include "clk-core.h"
25 .clk = { \
27 .parent = clk_parent, \
43 DECLARE_REF_CLK(ref_104m, &ref_312m.clk, 104 * CLOCK_1M, 3);
44 DECLARE_REF_CLK(ref_52m, &ref_104m.clk, 52 * CLOCK_1M, 2);
45 DECLARE_REF_CLK(ref_13m, &ref_52m.clk, 13 * CLOCK_1M, 4);
47 DECLARE_REF_CLK(var_104m, &var_312m.clk, 104 * CLOCK_1M, 3);
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/openbmc/linux/drivers/clk/ti/
H A Ddpll3xxx.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * OMAP3/4 - specific DPLL control functions
5 * Copyright (C) 2009-2010 Texas Instruments, Inc.
6 * Copyright (C) 2009-2010 Nokia Corporation
23 #include <linux/clk.h>
27 #include <linux/clk/ti.h>
40 static u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk);
41 static void omap3_dpll_deny_idle(struct clk_hw_omap *clk);
42 static void omap3_dpll_allow_idle(struct clk_hw_omap *clk);
46 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
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/openbmc/linux/arch/sh/kernel/cpu/sh4/
H A Dclock-sh4-202.c1 // SPDX-License-Identifier: GPL-2.0
3 * arch/sh/kernel/cpu/sh4/clock-sh4-202.c
5 * Additional SH4-202 support for the clock framework
22 static unsigned long emi_clk_recalc(struct clk *clk) in emi_clk_recalc() argument
25 return clk->parent->rate / frqcr3_divisors[idx]; in emi_clk_recalc()
28 static inline int frqcr3_lookup(struct clk *clk, unsigned long rate) in frqcr3_lookup() argument
30 int divisor = clk->parent->rate / rate; in frqcr3_lookup()
45 static struct clk sh4202_emi_clk = {
50 static unsigned long femi_clk_recalc(struct clk *clk) in femi_clk_recalc() argument
53 return clk->parent->rate / frqcr3_divisors[idx]; in femi_clk_recalc()
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/openbmc/u-boot/drivers/clk/at91/
H A Dclk-generated.c1 // SPDX-License-Identifier: GPL-2.0+
8 #include <clk-uclass.h>
20 * generated_clk_bind() - for the generated clock driver
21 * Recursively bind its children as clk devices.
27 return at91_clk_sub_device_bind(dev, "generic-clk"); in generated_clk_bind()
31 { .compatible = "atmel,sama5d2-clk-generated" },
36 .name = "generated-clk",
42 /*-------------------------------------------------------------*/
48 static ulong generic_clk_get_rate(struct clk *clk) in generic_clk_get_rate() argument
50 struct pmc_platdata *plat = dev_get_platdata(clk->dev); in generic_clk_get_rate()
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/openbmc/linux/drivers/clk/sunxi/
H A Dclk-sun9i-cpus.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2015 Chen-Yu Tsai
5 * Chen-Yu Tsai <wens@csie.org>
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
22 * sun9i_a80_cpus_clk_setup() - Setup function for a80 cpus composite clk
60 reg = readl(cpus->reg); in sun9i_a80_cpus_clk_recalc_rate()
62 /* apply pre-divider first if parent is pll4 */ in sun9i_a80_cpus_clk_recalc_rate()
66 /* clk divider */ in sun9i_a80_cpus_clk_recalc_rate()
73 u8 parent, unsigned long parent_rate) in sun9i_a80_cpus_clk_round() argument
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/openbmc/linux/drivers/clk/renesas/
H A Drcar-gen3-cpg.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Gen3 Clock Pulse Generator
5 * Copyright (C) 2015-2018 Glider bvba
8 * Based on clk-rcar-gen3.c
15 #include <linux/clk.h>
16 #include <linux/clk-provider.h>
25 #include "renesas-cpg-mssr.h"
26 #include "rcar-cpg-lib.h"
27 #include "rcar-gen3-cpg.h"
59 val = readl(pll_clk->pllcr_reg) & CPG_PLLnCR_STC_MASK; in cpg_pll_clk_recalc_rate()
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H A Drzg2l-cpg.c1 // SPDX-License-Identifier: GPL-2.0
7 * Based on renesas-cpg-mssr.c
15 #include <linux/clk.h>
16 #include <linux/clk-provider.h>
17 #include <linux/clk/renesas.h>
28 #include <linux/reset-controller.h>
32 #include <dt-bindings/clock/renesas-cpg-mssr.h>
34 #include "rzg2l-cpg.h"
85 * struct rzg2l_cpg_priv - Clock Pulse Generator Private Data
94 * @num_resets: Number of Module Resets in info->resets[]
[all …]
/openbmc/linux/include/linux/
H A Dsh_clk.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 #include <linux/clk.h>
13 struct clk;
24 void (*init)(struct clk *clk);
26 int (*enable)(struct clk *clk);
27 void (*disable)(struct clk *clk);
28 unsigned long (*recalc)(struct clk *clk);
29 int (*set_rate)(struct clk *clk, unsigned long rate);
30 int (*set_parent)(struct clk *clk, struct clk *parent);
31 long (*round_rate)(struct clk *clk, unsigned long rate);
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/openbmc/linux/drivers/clk/starfive/
H A Dclk-starfive-jh71x0.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2021-2022 Emil Renner Berthing <kernel@esmil.dk>
8 #include <linux/clk-provider.h>
13 #include "clk-starfive-jh71x0.h"
20 static struct jh71x0_clk_priv *jh71x0_priv_from(struct jh71x0_clk *clk) in jh71x0_priv_from() argument
22 return container_of(clk, struct jh71x0_clk_priv, reg[clk->idx]); in jh71x0_priv_from()
25 static u32 jh71x0_clk_reg_get(struct jh71x0_clk *clk) in jh71x0_clk_reg_get() argument
27 struct jh71x0_clk_priv *priv = jh71x0_priv_from(clk); in jh71x0_clk_reg_get()
28 void __iomem *reg = priv->base + 4 * clk->idx; in jh71x0_clk_reg_get()
33 static void jh71x0_clk_reg_rmw(struct jh71x0_clk *clk, u32 mask, u32 value) in jh71x0_clk_reg_rmw() argument
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