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Revision tags: v00.04.15, v00.04.14, v00.04.13, v00.04.12, v00.04.11, v00.04.10, v00.04.09, v00.04.08, v00.04.07, v00.04.06, v00.04.05, v00.04.04, v00.04.03, v00.04.02, v00.04.01, v00.04.00, v2021.04, v00.03.03, v2021.01, v2020.10, v2020.07, v00.02.13, v2020.04, v2020.01, v2019.10, v00.02.05, v00.02.04, v00.02.03, v00.02.02, v00.02.01, v2019.07, v00.02.00, v2019.04 |
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| #
8f5bfb76 |
| 03-Dec-2018 |
Tom Rini <trini@konsulko.com> |
Merge tag 'u-boot-amlogic-20181203' of git://git.denx.de/u-boot-amlogic
ARM: meson: Add regmap support for clock driver and sync DT with 4.19
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| #
8973d816 |
| 27-Nov-2018 |
Loic Devulder <ldevulder@suse.de> |
ARM: meson: Add regmap support for clock driver
This patch modifies the meson clock driver to use syscon/regmap like
the Linux kernel does, as it is needed if we want to share the same
DTS files.
D
ARM: meson: Add regmap support for clock driver
This patch modifies the meson clock driver to use syscon/regmap like
the Linux kernel does, as it is needed if we want to share the same
DTS files.
DTS files are synchronized from Linux 4.19.
Signed-off-by: Loic Devulder <ldevulder@suse.de>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
show more ...
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| #
93e72ac4 |
| 29-Nov-2018 |
Tom Rini <trini@konsulko.com> |
Merge tag 'u-boot-amlogic-20181126' of git://git.denx.de/u-boot-amlogic
Cleanup and update towards support for Amlogic Meson AXG SoCs :
- mmc: meson-gx: Add AXG compatible
- net: designware: add mes
Merge tag 'u-boot-amlogic-20181126' of git://git.denx.de/u-boot-amlogic
Cleanup and update towards support for Amlogic Meson AXG SoCs :
- mmc: meson-gx: Add AXG compatible
- net: designware: add meson meson compatibles
- Amlogic Meson cleanup for AXG SoC support
show more ...
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| #
33e33780 |
| 05-Oct-2018 |
Jerome Brunet <jbrunet@baylibre.com> |
ARM: meson: rework soc arch file to prepare for new SoC
We are about to add support for the Amlogic AXG SoC. While very close to
the Gx SoC family, we will need to handle a few thing which are diffe
ARM: meson: rework soc arch file to prepare for new SoC
We are about to add support for the Amlogic AXG SoC. While very close to
the Gx SoC family, we will need to handle a few thing which are different
in this SoC. Rework the meson arch directory to prepare for this.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
show more ...
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| #
572aeb53 |
| 26-Oct-2018 |
Jerome Brunet <jbrunet@baylibre.com> |
clk: meson: silence debug print
This debug print was not designed to be active in non-debug mode.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@bayli
clk: meson: silence debug print
This debug print was not designed to be active in non-debug mode.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
show more ...
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| #
19987c39 |
| 08-Nov-2018 |
Neil Armstrong <narmstrong@baylibre.com> |
clk: meson: add static to meson_gates table
The meson_gates table should be set static in the clk_meson driver.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
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| #
e070dc42 |
| 20-Nov-2018 |
Tom Rini <trini@konsulko.com> |
Merge branch '2018-11-19-master-imports'
- adc enhancements
- FAT fix
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| #
2fa77bd1 |
| 13-Nov-2018 |
Jerome Brunet <jbrunet@baylibre.com> |
clk: meson: fix clk81 divider calculation
clk81 divider is 0 based (meaning that 0 value in the register means
divide by 1). Fix clk81 rate calculation for this.
Signed-off-by: Jerome Brunet <jbrun
clk: meson: fix clk81 divider calculation
clk81 divider is 0 based (meaning that 0 value in the register means
divide by 1). Fix clk81 rate calculation for this.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
show more ...
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| #
c8e57016 |
| 06-Aug-2018 |
Neil Armstrong <narmstrong@baylibre.com> |
clk: clk_meson: Add mux and div support for reparent and rate setting
This patch adds support for :
- Rate calculation through muxes and generic dividers
- Basic gate setting propagation
- Reparenti
clk: clk_meson: Add mux and div support for reparent and rate setting
This patch adds support for :
- Rate calculation through muxes and generic dividers
- Basic gate setting propagation
- Reparenting for muxes
- Clock rate setting through generic dividers without reparenting
Support is only added to the Composite VPU and VAPB clocks in order
to support the Video Processing Unit Power Domain clock setup.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
show more ...
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Revision tags: v2018.07 |
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| #
c0fc1e21 |
| 14-Jun-2018 |
Beniamino Galvani <b.galvani@gmail.com> |
clk: add Amlogic meson clock driver
Introduce a basic clock driver for Amlogic Meson SoCs which supports
enabling/disabling clock gates and getting their frequency.
Signed-off-by: Beniamino Galvani
clk: add Amlogic meson clock driver
Introduce a basic clock driver for Amlogic Meson SoCs which supports
enabling/disabling clock gates and getting their frequency.
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
show more ...
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