1 // SPDX-License-Identifier: GPL-2.0+
3  * Copyright 2018-2021 NXP
7 #include <dt-bindings/firmware/imx/rsrc.h>
8 #include <linux/arm-smccc.h>
10 #include <linux/clk-provider.h>
18 #include "clk-scu.h"
42  * struct clk_scu - Description of one SCU clock
53 	struct clk_hw *parent;  member
60  * struct clk_gpr_scu - Description of one SCU GPR clock
76  * struct imx_sc_msg_req_set_clock_rate - clock set rate protocol
80  * @clk: clk type of this resource
88 	u8 clk;  member
93 	u8 clk;  member
101  * struct imx_sc_msg_get_clock_rate - clock get rate protocol
117  * struct imx_sc_msg_get_clock_parent - clock get parent protocol
119  * @req: get parent request protocol
120  * @resp: get parent response protocol
122  * This structure describes the SCU protocol of clock get parent
129 			u8 clk;  member
132 			u8 parent;  member
138  * struct imx_sc_msg_set_clock_parent - clock set parent protocol
140  * @req: set parent request protocol
142  * This structure describes the SCU protocol of clock set parent
147 	u8 clk;  member
148 	u8 parent;  member
152  * struct imx_sc_msg_req_clock_enable - clock gate protocol
155  * @clk: clk type of this resource
164 	u8 clk;  member
176 	return *(u32 *)rsrc - *(u32 *)rsrc_p;  in imx_scu_clk_search_cmp()
186 	p = bsearch(&rsrc_id, rsrc_table->rsrc, rsrc_table->num,  in imx_scu_clk_is_valid()
187 		    sizeof(rsrc_table->rsrc[0]), imx_scu_clk_search_cmp);  in imx_scu_clk_is_valid()
202 	of_property_read_u32(np, "#clock-cells", &clk_cells);  in imx_clk_scu_init()
209 		pd_np = of_find_compatible_node(NULL, NULL, "fsl,scu-pd");  in imx_clk_scu_init()
211 			return -EINVAL;  in imx_clk_scu_init()
220  * clk_scu_recalc_rate - Get clock rate for a SCU clock
222  * @parent_rate: parent rate provided by common clock framework, not used
230 	struct clk_scu *clk = to_clk_scu(hw);  in clk_scu_recalc_rate()  local
235 	hdr->ver = IMX_SC_RPC_VERSION;  in clk_scu_recalc_rate()
236 	hdr->svc = IMX_SC_RPC_SVC_PM;  in clk_scu_recalc_rate()
237 	hdr->func = IMX_SC_PM_FUNC_GET_CLOCK_RATE;  in clk_scu_recalc_rate()
238 	hdr->size = 2;  in clk_scu_recalc_rate()
240 	msg.data.req.resource = cpu_to_le16(clk->rsrc_id);  in clk_scu_recalc_rate()
241 	msg.data.req.clk = clk->clk_type;  in clk_scu_recalc_rate()
254  * clk_scu_determine_rate - Returns the closest rate for a SCU clock
271  * clk_scu_round_rate - Round clock rate for a SCU clock
274  * @parent_rate: parent rate provided by common clock framework, not used
291 	struct clk_scu *clk = to_clk_scu(hw);  in clk_scu_atf_set_cpu_rate()  local
295 	if (clk->rsrc_id == IMX_SC_R_A35 || clk->rsrc_id == IMX_SC_R_A53)  in clk_scu_atf_set_cpu_rate()
297 	else if (clk->rsrc_id == IMX_SC_R_A72)  in clk_scu_atf_set_cpu_rate()
300 		return -EINVAL;  in clk_scu_atf_set_cpu_rate()
302 	/* CPU frequency scaling can ONLY be done by ARM-Trusted-Firmware */  in clk_scu_atf_set_cpu_rate()
310  * clk_scu_set_rate - Set rate for a SCU clock
313  * @parent_rate: rate of the clock parent, not used for SCU clocks
321 	struct clk_scu *clk = to_clk_scu(hw);  in clk_scu_set_rate()  local
325 	hdr->ver = IMX_SC_RPC_VERSION;  in clk_scu_set_rate()
326 	hdr->svc = IMX_SC_RPC_SVC_PM;  in clk_scu_set_rate()
327 	hdr->func = IMX_SC_PM_FUNC_SET_CLOCK_RATE;  in clk_scu_set_rate()
328 	hdr->size = 3;  in clk_scu_set_rate()
331 	msg.resource = cpu_to_le16(clk->rsrc_id);  in clk_scu_set_rate()
332 	msg.clk = clk->clk_type;  in clk_scu_set_rate()
339 	struct clk_scu *clk = to_clk_scu(hw);  in clk_scu_get_parent()  local
344 	hdr->ver = IMX_SC_RPC_VERSION;  in clk_scu_get_parent()
345 	hdr->svc = IMX_SC_RPC_SVC_PM;  in clk_scu_get_parent()
346 	hdr->func = IMX_SC_PM_FUNC_GET_CLOCK_PARENT;  in clk_scu_get_parent()
347 	hdr->size = 2;  in clk_scu_get_parent()
349 	msg.data.req.resource = cpu_to_le16(clk->rsrc_id);  in clk_scu_get_parent()
350 	msg.data.req.clk = clk->clk_type;  in clk_scu_get_parent()
354 		pr_err("%s: failed to get clock parent %d\n",  in clk_scu_get_parent()
359 	clk->parent_index = msg.data.resp.parent;  in clk_scu_get_parent()
361 	return msg.data.resp.parent;  in clk_scu_get_parent()
366 	struct clk_scu *clk = to_clk_scu(hw);  in clk_scu_set_parent()  local
371 	hdr->ver = IMX_SC_RPC_VERSION;  in clk_scu_set_parent()
372 	hdr->svc = IMX_SC_RPC_SVC_PM;  in clk_scu_set_parent()
373 	hdr->func = IMX_SC_PM_FUNC_SET_CLOCK_PARENT;  in clk_scu_set_parent()
374 	hdr->size = 2;  in clk_scu_set_parent()
376 	msg.resource = cpu_to_le16(clk->rsrc_id);  in clk_scu_set_parent()
377 	msg.clk = clk->clk_type;  in clk_scu_set_parent()
378 	msg.parent = index;  in clk_scu_set_parent()
382 		pr_err("%s: failed to set clock parent %d\n",  in clk_scu_set_parent()
387 	clk->parent_index = index;  in clk_scu_set_parent()
393 			      u8 clk, bool enable, bool autog)  in sc_pm_clock_enable()  argument
398 	hdr->ver = IMX_SC_RPC_VERSION;  in sc_pm_clock_enable()
399 	hdr->svc = IMX_SC_RPC_SVC_PM;  in sc_pm_clock_enable()
400 	hdr->func = IMX_SC_PM_FUNC_CLOCK_ENABLE;  in sc_pm_clock_enable()
401 	hdr->size = 3;  in sc_pm_clock_enable()
404 	msg.clk = clk;  in sc_pm_clock_enable()
412  * clk_scu_prepare - Enable a SCU clock
419 	struct clk_scu *clk = to_clk_scu(hw);  in clk_scu_prepare()  local
421 	return sc_pm_clock_enable(ccm_ipc_handle, clk->rsrc_id,  in clk_scu_prepare()
422 				  clk->clk_type, true, false);  in clk_scu_prepare()
426  * clk_scu_unprepare - Disable a SCU clock
433 	struct clk_scu *clk = to_clk_scu(hw);  in clk_scu_unprepare()  local
436 	ret = sc_pm_clock_enable(ccm_ipc_handle, clk->rsrc_id,  in clk_scu_unprepare()
437 				 clk->clk_type, false, false);  in clk_scu_unprepare()
439 		pr_warn("%s: clk unprepare failed %d\n", clk_hw_get_name(hw),  in clk_scu_unprepare()
472 	struct clk_scu *clk;  in __imx_clk_scu()  local
476 	clk = kzalloc(sizeof(*clk), GFP_KERNEL);  in __imx_clk_scu()
477 	if (!clk)  in __imx_clk_scu()
478 		return ERR_PTR(-ENOMEM);  in __imx_clk_scu()
480 	clk->rsrc_id = rsrc_id;  in __imx_clk_scu()
481 	clk->clk_type = clk_type;  in __imx_clk_scu()
502 	clk->hw.init = &init;  in __imx_clk_scu()
504 	hw = &clk->hw;  in __imx_clk_scu()
507 		kfree(clk);  in __imx_clk_scu()
513 		dev_set_drvdata(dev, clk);  in __imx_clk_scu()
521 	unsigned int rsrc = clkspec->args[0];  in imx_scu_of_clk_src_get()
522 	unsigned int idx = clkspec->args[1];  in imx_scu_of_clk_src_get()
524 	struct imx_scu_clk_node *clk;  in imx_scu_of_clk_src_get()  local
526 	list_for_each_entry(clk, &scu_clks[rsrc], node) {  in imx_scu_of_clk_src_get()
527 		if (clk->clk_type == idx)  in imx_scu_of_clk_src_get()
528 			return clk->hw;  in imx_scu_of_clk_src_get()
531 	return ERR_PTR(-ENODEV);  in imx_scu_of_clk_src_get()
536 	struct device *dev = &pdev->dev;  in imx_clk_scu_probe()
537 	struct imx_scu_clk_node *clk = dev_get_platdata(dev);  in imx_clk_scu_probe()  local
541 	if (!((clk->rsrc == IMX_SC_R_A35) || (clk->rsrc == IMX_SC_R_A53) ||  in imx_clk_scu_probe()
542 	    (clk->rsrc == IMX_SC_R_A72))) {  in imx_clk_scu_probe()
545 		pm_runtime_use_autosuspend(&pdev->dev);  in imx_clk_scu_probe()
556 	hw = __imx_clk_scu(dev, clk->name, clk->parents, clk->num_parents,  in imx_clk_scu_probe()
557 			   clk->rsrc, clk->clk_type);  in imx_clk_scu_probe()
563 	clk->hw = hw;  in imx_clk_scu_probe()
564 	list_add_tail(&clk->node, &imx_scu_clks[clk->rsrc]);  in imx_clk_scu_probe()
566 	if (!((clk->rsrc == IMX_SC_R_A35) || (clk->rsrc == IMX_SC_R_A53) ||  in imx_clk_scu_probe()
567 	    (clk->rsrc == IMX_SC_R_A72))) {  in imx_clk_scu_probe()
568 		pm_runtime_mark_last_busy(&pdev->dev);  in imx_clk_scu_probe()
569 		pm_runtime_put_autosuspend(&pdev->dev);  in imx_clk_scu_probe()
572 	dev_dbg(dev, "register SCU clock rsrc:%d type:%d\n", clk->rsrc,  in imx_clk_scu_probe()
573 		clk->clk_type);  in imx_clk_scu_probe()
580 	struct clk_scu *clk = dev_get_drvdata(dev);  in imx_clk_scu_suspend()  local
581 	u32 rsrc_id = clk->rsrc_id;  in imx_clk_scu_suspend()
587 	clk->parent = clk_hw_get_parent(&clk->hw);  in imx_clk_scu_suspend()
589 	/* DC SS needs to handle bypass clock using non-cached clock rate */  in imx_clk_scu_suspend()
590 	if (clk->rsrc_id == IMX_SC_R_DC_0_VIDEO0 ||  in imx_clk_scu_suspend()
591 		clk->rsrc_id == IMX_SC_R_DC_0_VIDEO1 ||  in imx_clk_scu_suspend()
592 		clk->rsrc_id == IMX_SC_R_DC_1_VIDEO0 ||  in imx_clk_scu_suspend()
593 		clk->rsrc_id == IMX_SC_R_DC_1_VIDEO1)  in imx_clk_scu_suspend()
594 		clk->rate = clk_scu_recalc_rate(&clk->hw, 0);  in imx_clk_scu_suspend()
596 		clk->rate = clk_hw_get_rate(&clk->hw);  in imx_clk_scu_suspend()
597 	clk->is_enabled = clk_hw_is_prepared(&clk->hw);  in imx_clk_scu_suspend()
599 	if (clk->parent)  in imx_clk_scu_suspend()
600 		dev_dbg(dev, "save parent %s idx %u\n", clk_hw_get_name(clk->parent),  in imx_clk_scu_suspend()
601 			clk->parent_index);  in imx_clk_scu_suspend()
603 	if (clk->rate)  in imx_clk_scu_suspend()
604 		dev_dbg(dev, "save rate %d\n", clk->rate);  in imx_clk_scu_suspend()
606 	if (clk->is_enabled)  in imx_clk_scu_suspend()
614 	struct clk_scu *clk = dev_get_drvdata(dev);  in imx_clk_scu_resume()  local
615 	u32 rsrc_id = clk->rsrc_id;  in imx_clk_scu_resume()
622 	if (clk->parent) {  in imx_clk_scu_resume()
623 		ret = clk_scu_set_parent(&clk->hw, clk->parent_index);  in imx_clk_scu_resume()
624 		dev_dbg(dev, "restore parent %s idx %u %s\n",  in imx_clk_scu_resume()
625 			clk_hw_get_name(clk->parent),  in imx_clk_scu_resume()
626 			clk->parent_index, !ret ? "success" : "failed");  in imx_clk_scu_resume()
629 	if (clk->rate) {  in imx_clk_scu_resume()
630 		ret = clk_scu_set_rate(&clk->hw, clk->rate, 0);  in imx_clk_scu_resume()
631 		dev_dbg(dev, "restore rate %d %s\n", clk->rate,  in imx_clk_scu_resume()
635 	if (clk->is_enabled && rsrc_id != IMX_SC_R_PI_0_PLL) {  in imx_clk_scu_resume()
636 		ret = clk_scu_prepare(&clk->hw);  in imx_clk_scu_resume()
651 		.name = "imx-scu-clk",
677 	struct imx_scu_clk_node clk = {  in imx_clk_scu_alloc_dev()  local
688 		return ERR_PTR(-EINVAL);  in imx_clk_scu_alloc_dev()
692 		pr_err("%s: failed to allocate scu clk dev rsrc %d type %d\n",  in imx_clk_scu_alloc_dev()
694 		return ERR_PTR(-ENOMEM);  in imx_clk_scu_alloc_dev()
697 	ret = platform_device_add_data(pdev, &clk, sizeof(clk));  in imx_clk_scu_alloc_dev()
703 	ret = driver_set_override(&pdev->dev, &pdev->driver_override,  in imx_clk_scu_alloc_dev()
704 				  "imx-scu-clk", strlen("imx-scu-clk"));  in imx_clk_scu_alloc_dev()
710 	ret = imx_clk_scu_attach_pd(&pdev->dev, rsrc_id);  in imx_clk_scu_alloc_dev()
727 	struct imx_scu_clk_node *clk, *n;  in imx_clk_scu_unregister()  local
731 		list_for_each_entry_safe(clk, n, &imx_scu_clks[i], node) {  in imx_clk_scu_unregister()
732 			clk_hw_unregister(clk->hw);  in imx_clk_scu_unregister()
733 			kfree(clk);  in imx_clk_scu_unregister()
741 	struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);  in clk_gpr_div_scu_recalc_rate()  local
746 	err = imx_sc_misc_get_control(ccm_ipc_handle, clk->rsrc_id,  in clk_gpr_div_scu_recalc_rate()
747 				      clk->gpr_id, &val);  in clk_gpr_div_scu_recalc_rate()
768 	struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);  in clk_gpr_div_scu_set_rate()  local
773 	err = imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id,  in clk_gpr_div_scu_set_rate()
774 				      clk->gpr_id, val);  in clk_gpr_div_scu_set_rate()
776 	return err ? -EINVAL : 0;  in clk_gpr_div_scu_set_rate()
787 	struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);  in clk_gpr_mux_scu_get_parent()  local
790 	imx_sc_misc_get_control(ccm_ipc_handle, clk->rsrc_id,  in clk_gpr_mux_scu_get_parent()
791 				clk->gpr_id, &val);  in clk_gpr_mux_scu_get_parent()
798 	struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);  in clk_gpr_mux_scu_set_parent()  local
800 	return imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id,  in clk_gpr_mux_scu_set_parent()
801 				       clk->gpr_id, index);  in clk_gpr_mux_scu_set_parent()
812 	struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);  in clk_gpr_gate_scu_prepare()  local
814 	return imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id,  in clk_gpr_gate_scu_prepare()
815 				       clk->gpr_id, !clk->gate_invert);  in clk_gpr_gate_scu_prepare()
820 	struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);  in clk_gpr_gate_scu_unprepare()  local
823 	ret = imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id,  in clk_gpr_gate_scu_unprepare()
824 				      clk->gpr_id, clk->gate_invert);  in clk_gpr_gate_scu_unprepare()
826 		pr_err("%s: clk unprepare failed %d\n", clk_hw_get_name(hw),  in clk_gpr_gate_scu_unprepare()
832 	struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);  in clk_gpr_gate_scu_is_prepared()  local
836 	ret = imx_sc_misc_get_control(ccm_ipc_handle, clk->rsrc_id,  in clk_gpr_gate_scu_is_prepared()
837 				      clk->gpr_id, &val);  in clk_gpr_gate_scu_is_prepared()
841 	return clk->gate_invert ? !val : val;  in clk_gpr_gate_scu_is_prepared()
855 	struct clk_gpr_scu *clk;  in __imx_clk_gpr_scu()  local
861 		return ERR_PTR(-EINVAL);  in __imx_clk_gpr_scu()
865 		return ERR_PTR(-ENOMEM);  in __imx_clk_gpr_scu()
869 		return ERR_PTR(-EINVAL);  in __imx_clk_gpr_scu()
872 	clk = kzalloc(sizeof(*clk), GFP_KERNEL);  in __imx_clk_gpr_scu()
873 	if (!clk) {  in __imx_clk_gpr_scu()
875 		return ERR_PTR(-ENOMEM);  in __imx_clk_gpr_scu()
878 	clk->rsrc_id = rsrc_id;  in __imx_clk_gpr_scu()
879 	clk->gpr_id = gpr_id;  in __imx_clk_gpr_scu()
880 	clk->flags = flags;  in __imx_clk_gpr_scu()
881 	clk->gate_invert = invert;  in __imx_clk_gpr_scu()
897 	clk->hw.init = &init;  in __imx_clk_gpr_scu()
899 	hw = &clk->hw;  in __imx_clk_gpr_scu()
902 		kfree(clk);  in __imx_clk_gpr_scu()
906 		clk_node->hw = hw;  in __imx_clk_gpr_scu()
907 		clk_node->clk_type = gpr_id;  in __imx_clk_gpr_scu()
908 		list_add_tail(&clk_node->node, &imx_scu_clks[rsrc_id]);  in __imx_clk_gpr_scu()