Home
last modified time | relevance | path

Searched +full:cs +full:- +full:3 (Results 1 – 25 of 1112) sorted by relevance

12345678910>>...45

/openbmc/u-boot/board/freescale/corenet_ds/
H A Dp4080ds_ddr.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2009-2011 Freescale Semiconductor, Inc.
78 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
79 .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
80 .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
81 .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
82 .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
83 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
84 .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
85 .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
[all …]
/openbmc/qemu/hw/intc/
H A Darm_gicv3_cpuif.c18 #include "qemu/main-loop.h"
24 #include "target/arm/cpu-features.h"
37 return env->gicv3state; in icc_cs_from_env()
51 static inline int icv_min_vbpr(GICv3CPUState *cs) in icv_min_vbpr() argument
53 return 7 - cs->vprebits; in icv_min_vbpr()
56 static inline int ich_num_aprs(GICv3CPUState *cs) in ich_num_aprs() argument
59 int aprmax = 1 << (cs->vprebits - 5); in ich_num_aprs()
60 assert(aprmax <= ARRAY_SIZE(cs->ich_apr[0])); in ich_num_aprs()
108 static int read_vbpr(GICv3CPUState *cs, int grp) in read_vbpr() argument
114 return extract64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VBPR0_SHIFT, in read_vbpr()
[all …]
H A Darm_gicv3_common.c2 * ARM GICv3 support - common bits of emulated and KVM kernel model
27 #include "qemu/error-report.h"
30 #include "hw/qdev-properties.h"
33 #include "hw/arm/linux-boot-if.h"
37 static void gicv3_gicd_no_migration_shift_bug_post_load(GICv3State *cs) in gicv3_gicd_no_migration_shift_bug_post_load() argument
39 if (cs->gicd_no_migration_shift_bug) { in gicv3_gicd_no_migration_shift_bug_post_load()
50 memmove(cs->group, (uint8_t *)cs->group + GIC_INTERNAL / 8, in gicv3_gicd_no_migration_shift_bug_post_load()
51 sizeof(cs->group) - GIC_INTERNAL / 8); in gicv3_gicd_no_migration_shift_bug_post_load()
52 memmove(cs->grpmod, (uint8_t *)cs->grpmod + GIC_INTERNAL / 8, in gicv3_gicd_no_migration_shift_bug_post_load()
53 sizeof(cs->grpmod) - GIC_INTERNAL / 8); in gicv3_gicd_no_migration_shift_bug_post_load()
[all …]
/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_write_leveling.c1 // SPDX-License-Identifier: GPL-2.0
46 static int ddr3_write_leveling_single_cs(u32 cs, u32 freq, int ratio_2to1,
59 * Args: freq - current sequence frequency
60 * dram_info - main struct
66 u32 reg, phase, delay, cs, pup; in ddr3_write_leveling_hw() local
70 /* Debug message - Start Read leveling procedure */ in ddr3_write_leveling_hw()
71 DEBUG_WL_S("DDR3 - Write Leveling - Starting HW WL procedure\n"); in ddr3_write_leveling_hw()
86 reg |= (dram_info->cs_ena << (REG_DRAM_TRAINING_CS_OFFS)); in ddr3_write_leveling_hw()
87 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_write_leveling_hw()
103 * Read results to arrays - Results are required for WL in ddr3_write_leveling_hw()
[all …]
H A Dddr3_read_leveling.c1 // SPDX-License-Identifier: GPL-2.0
44 static int ddr3_read_leveling_single_cs_rl_mode(u32 cs, u32 freq,
48 static int ddr3_read_leveling_single_cs_window_mode(u32 cs, u32 freq,
56 * Args: dram_info - main struct
57 * freq - current sequence frequency
65 /* Debug message - Start Read leveling procedure */ in ddr3_read_leveling_hw()
66 DEBUG_RL_S("DDR3 - Read Leveling - Starting HW RL procedure\n"); in ddr3_read_leveling_hw()
73 /* Enable CS in the automatic process */ in ddr3_read_leveling_hw()
74 reg |= (dram_info->cs_ena << REG_DRAM_TRAINING_CS_OFFS); in ddr3_read_leveling_hw()
76 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_read_leveling_hw()
[all …]
H A Dddr3_spd.c1 // SPDX-License-Identifier: GPL-2.0
30 #define SPD_MODULE_TYPE_BYTE 3
40 #define SPD_ROW_NUM_OFF 3
52 #define SPD_MODULE_BANK_NUM_OFF 3
58 #define SPD_BUS_ECC_OFF 3
59 #define SPD_BUS_ECC_MASK (3 << SPD_BUS_ECC_OFF)
196 * Name: ddr3_get_dimm_num - Find number of dimms and their addresses
198 * Args: dimm_addr - array of dimm addresses
205 u8 data[3]; in ddr3_get_dimm_num()
211 dimm_cur_addr--) { in ddr3_get_dimm_num()
[all …]
/openbmc/linux/arch/m68k/include/asm/
H A Dm5307sim.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m5307sim.h -- ColdFire 5307 System Integration Module support.
19 #define CPU_INSTR_PER_JIFFY 3
41 #define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */
51 #define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
52 #define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
53 #define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
54 #define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
55 #define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
56 #define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
[all …]
H A Dm5407sim.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m5407sim.h -- ColdFire 5407 System Integration Module support.
19 #define CPU_INSTR_PER_JIFFY 3
41 #define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */
51 #define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
52 #define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
53 #define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
54 #define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
55 #define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
56 #define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
[all …]
H A Dm5206sim.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m5206sim.h -- ColdFire 5206 System Integration Module support.
17 #define CPU_INSTR_PER_JIFFY 3
28 #define MCFSIM_ICR3 (MCF_MBAR + 0x16) /* Intr Ctrl reg 3 */
62 #define MCFSIM_CSAR0 (MCF_MBAR + 0x64) /* CS 0 Address reg */
63 #define MCFSIM_CSMR0 (MCF_MBAR + 0x68) /* CS 0 Mask reg */
64 #define MCFSIM_CSCR0 (MCF_MBAR + 0x6e) /* CS 0 Control reg */
65 #define MCFSIM_CSAR1 (MCF_MBAR + 0x70) /* CS 1 Address reg */
66 #define MCFSIM_CSMR1 (MCF_MBAR + 0x74) /* CS 1 Mask reg */
67 #define MCFSIM_CSCR1 (MCF_MBAR + 0x7a) /* CS 1 Control reg */
[all …]
/openbmc/qemu/target/i386/tcg/system/
H A Dsmm_helper.c2 * x86 SMM helpers (system-only)
22 #include "exec/helper-proto.h"
24 #include "tcg/helper-tcg.h"
37 CPUX86State *env = &cpu->env; in do_smm_enter()
38 CPUState *cs = CPU(cpu); in do_smm_enter() local
46 env->msr_smi_count++; in do_smm_enter()
47 env->hflags |= HF_SMM_MASK; in do_smm_enter()
48 if (env->hflags2 & HF2_NMI_MASK) { in do_smm_enter()
49 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK; in do_smm_enter()
51 env->hflags2 |= HF2_NMI_MASK; in do_smm_enter()
[all …]
/openbmc/linux/sound/core/
H A Dpcm_iec958.c1 // SPDX-License-Identifier: GPL-2.0-only
13 * snd_pcm_create_iec958_consumer_default - create default consumer format IEC958 channel status
14 * @cs: channel status buffer, at least four bytes
17 * Create the consumer format channel status data in @cs of maximum size
18 * @len. When relevant, the configuration-dependant bits will be set as
29 int snd_pcm_create_iec958_consumer_default(u8 *cs, size_t len) in snd_pcm_create_iec958_consumer_default() argument
32 return -EINVAL; in snd_pcm_create_iec958_consumer_default()
34 memset(cs, 0, len); in snd_pcm_create_iec958_consumer_default()
36 cs[0] = IEC958_AES0_CON_NOT_COPYRIGHT | IEC958_AES0_CON_EMPHASIS_NONE; in snd_pcm_create_iec958_consumer_default()
37 cs[1] = IEC958_AES1_CON_GENERAL; in snd_pcm_create_iec958_consumer_default()
[all …]
/openbmc/qemu/target/loongarch/kvm/
H A Dkvm.c1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 #include "asm-loongarch/kvm_para.h"
14 #include "qemu/error-report.h"
15 #include "qemu/main-loop.h"
21 #include "exec/address-spaces.h"
28 #include "cpu-csr.h"
38 static int kvm_get_stealtime(CPUState *cs) in kvm_get_stealtime() argument
40 CPULoongArchState *env = cpu_env(cs); in kvm_get_stealtime()
45 .addr = (uint64_t)&env->stealtime.guest_addr, in kvm_get_stealtime()
48 err = kvm_vcpu_ioctl(cs, KVM_HAS_DEVICE_ATTR, attr); in kvm_get_stealtime()
[all …]
/openbmc/qemu/target/i386/
H A Dhelper.c21 #include "qapi/qapi-events-run-state.h"
24 #include "exec/translation-block.h"
33 #include "tcg/insn-start-words.h"
38 if ((env->cr[4] & CR4_OSXSAVE_MASK) in cpu_sync_avx_hflag()
39 && (env->xcr0 & (XSTATE_SSE_MASK | XSTATE_YMM_MASK)) in cpu_sync_avx_hflag()
41 env->hflags |= HF_AVX_EN_MASK; in cpu_sync_avx_hflag()
43 env->hflags &= ~HF_AVX_EN_MASK; in cpu_sync_avx_hflag()
49 uint32_t hflags = env->hflags; in cpu_sync_bndcs_hflags()
50 uint32_t hflags2 = env->hflags2; in cpu_sync_bndcs_hflags()
53 if ((hflags & HF_CPL_MASK) == 3) { in cpu_sync_bndcs_hflags()
[all …]
/openbmc/linux/drivers/gpu/drm/i915/gt/
H A Dselftest_engine_pm.c1 // SPDX-License-Identifier: GPL-2.0
25 return *a - *b; in cmp_u64()
31 return (a[1] + 2 * a[2] + a[3]) >> 2; in trifilter()
34 static u32 *emit_wait(u32 *cs, u32 offset, int op, u32 value) in emit_wait() argument
36 *cs++ = MI_SEMAPHORE_WAIT | in emit_wait()
40 *cs++ = value; in emit_wait()
41 *cs++ = offset; in emit_wait()
42 *cs++ = 0; in emit_wait()
44 return cs; in emit_wait()
47 static u32 *emit_store(u32 *cs, u32 offset, u32 value) in emit_store() argument
[all …]
/openbmc/qemu/target/i386/hvf/
H A Dx86hvf.c2 * Copyright (c) 2003-2008 Fabrice Bellard
35 void hvf_set_segment(CPUState *cs, struct vmx_segment *vmx_seg, in hvf_set_segment() argument
38 vmx_seg->sel = qseg->selector; in hvf_set_segment()
39 vmx_seg->base = qseg->base; in hvf_set_segment()
40 vmx_seg->limit = qseg->limit; in hvf_set_segment()
42 if (!qseg->selector && !x86_is_real(cs) && !is_tr) { in hvf_set_segment()
45 vmx_seg->ar = 1 << 16; in hvf_set_segment()
48 vmx_seg->ar = (qseg->flags >> DESC_TYPE_SHIFT) & 0xf; in hvf_set_segment()
49 vmx_seg->ar |= ((qseg->flags >> DESC_G_SHIFT) & 1) << 15; in hvf_set_segment()
50 vmx_seg->ar |= ((qseg->flags >> DESC_B_SHIFT) & 1) << 14; in hvf_set_segment()
[all …]
/openbmc/qemu/target/sparc/
H A Dmmu_helper.c4 * Copyright (c) 2003-2005 Fabrice Bellard
24 #include "exec/page-protection.h"
25 #include "qemu/qemu-print.h"
77 CPUState *cs = env_cpu(env); in get_physical_address() local
83 full->lg_page_size = TARGET_PAGE_BITS; in get_physical_address()
85 if (rw == 2 && (env->mmuregs[0] & env->def.mmu_bm)) { in get_physical_address()
86 full->phys_addr = env->prom_addr | (address & 0x7ffffULL); in get_physical_address()
87 full->prot = PAGE_READ | PAGE_EXEC; in get_physical_address()
90 full->phys_addr = address; in get_physical_address()
91 full->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; in get_physical_address()
[all …]
/openbmc/u-boot/board/atmel/at91sam9261ek/
H A Dat91sam9261ek.c1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2007-2008
24 #include <asm/mach-types.h>
28 /* ------------------------------------------------------------------------- */
41 csa = readl(&matrix->ebicsa); in at91sam9261ek_nand_hw_init()
44 writel(csa, &matrix->ebicsa); in at91sam9261ek_nand_hw_init()
50 &smc->cs[3].setup); in at91sam9261ek_nand_hw_init()
51 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(7) | in at91sam9261ek_nand_hw_init()
52 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(7), in at91sam9261ek_nand_hw_init()
53 &smc->cs[3].pulse); in at91sam9261ek_nand_hw_init()
[all …]
/openbmc/u-boot/cmd/
H A Dmmc_spi.c5 * Licensed under the GPL-2 or later.
23 * rising edge ... meaning SPI modes 0 or 3. So either SPI mode
26 * specify mode 3 (if hardware is not compatible to mode 0).
35 uint cs = CONFIG_MMC_SPI_CS; in do_mmc_spi() local
44 cs = simple_strtoul(argv[1], &endp, 0); in do_mmc_spi()
50 bus = cs; in do_mmc_spi()
51 cs = simple_strtoul(endp + 1, &endp, 0); in do_mmc_spi()
55 if (argc >= 3) { in do_mmc_spi()
61 mode = simple_strtoul(argv[3], &endp, 16); in do_mmc_spi()
62 if (*argv[3] == 0 || *endp != 0) in do_mmc_spi()
[all …]
/openbmc/u-boot/drivers/spi/
H A Domap3_spi.c1 // SPDX-License-Identifier: GPL-2.0+
9 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
43 /* per-register bitmasks */
44 #define OMAP3_MCSPI_SYSCONFIG_SMARTIDLE (2 << 3)
53 #define OMAP3_MCSPI_MODULCTRL_STEST BIT(3)
104 /* channel0: 0x2C - 0x3C, bus 0 & 1 & 2 & 3 */
105 /* channel1: 0x40 - 0x50, bus 0 & 1 */
106 /* channel2: 0x54 - 0x64, bus 0 & 1 */
107 /* channel3: 0x68 - 0x78, bus 0 */
115 unsigned int cs; member
[all …]
/openbmc/qemu/target/arm/tcg/
H A Dtlb-insns.c6 * SPDX-License-Identifier: GPL-2.0-or-later
13 #include "cpu-features.h"
54 CPUState *cs = env_cpu(env); in tlbiall_is_write() local
56 tlb_flush_all_cpus_synced(cs); in tlbiall_is_write()
62 CPUState *cs = env_cpu(env); in tlbiasid_is_write() local
64 tlb_flush_all_cpus_synced(cs); in tlbiasid_is_write()
70 CPUState *cs = env_cpu(env); in tlbimva_is_write() local
72 tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK); in tlbimva_is_write()
78 CPUState *cs = env_cpu(env); in tlbimvaa_is_write() local
80 tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK); in tlbimvaa_is_write()
[all …]
/openbmc/u-boot/drivers/ddr/fsl/
H A Dmpc85xx_ddr_gen3.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2008-2012 Freescale Semiconductor, Inc.
16 * regs has the to-be-set values for DDR controller registers
36 int csn = -1; in fsl_ddr_set_memctl_regs()
56 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3) in fsl_ddr_set_memctl_regs()
57 case 3: in fsl_ddr_set_memctl_regs()
69 if (regs->ddr_eor) in fsl_ddr_set_memctl_regs()
70 out_be32(&ddr->eor, regs->ddr_eor); in fsl_ddr_set_memctl_regs()
74 cs_sa = (regs->cs[i].bnds >> 16) & 0xfff; in fsl_ddr_set_memctl_regs()
75 cs_ea = regs->cs[i].bnds & 0xfff; in fsl_ddr_set_memctl_regs()
[all …]
/openbmc/u-boot/drivers/ddr/marvell/a38x/
H A Dmv_ddr_regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
118 #define CS_STRUCT_OFFS(cs) (CS_STRUCT_BASE + (cs) * 4) argument
121 #define CS_SIZE_OFFS(cs) (CS_SIZE_BASE + (cs) * 4) argument
124 #define CS_SIZE_HIGH_OFFS(cs) (CS_SIZE_HIGH_BASE + (cs)) argument
135 #define SDRAM_OP_CMD_CS_OFFS(cs) (SDRAM_OP_CMD_CS_BASE + (cs)) argument
162 #define CPU_INTERJECTION_ENA_OFFS 3
205 #define CAL_UPDATE_CTRL_OFFS 3
231 #define RD_SMPL_DLY_CS_OFFS(cs) (RD_SMPL_DLY_CS_BASE + (cs) * 8) argument
236 #define RD_RDY_DLY_CS_OFFS(cs) (RD_RDY_DLY_CS_BASE + (cs) * 8) argument
263 #define TRN_DBG_RDY_INC_PH_2TO1_OFFS(phase) (TRN_DBG_RDY_INC_PH_2TO1_BASE + (phase) * 3)
[all …]
/openbmc/linux/drivers/memory/
H A Domap-gpmc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2005-2006 Nokia Corporation
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
32 #include <linux/omap-gpmc.h>
36 #include <linux/platform_data/mtd-nand-omap2.h>
38 #define DEVICE_NAME "omap-gpmc"
145 #define GPMC_CONFIG1_CLKACTIVATIONTIME(val) (((val) & 3) << 25)
148 #define GPMC_CONFIG1_PAGE_LEN(val) (((val) & 3) << 23)
153 #define GPMC_CONFIG1_WAIT_MON_TIME(val) (((val) & 3) << 18)
156 #define GPMC_CONFIG1_WAIT_PIN_SEL(val) (((val) & 3) << 16)
[all …]
/openbmc/qemu/target/arm/
H A Dkvm.c4 * Copyright Christoffer Dall 2009-2010
5 * Copyright Mian-M. Hamayun 2013, Virtual Open Systems
9 * See the COPYING file in the top-level directory.
19 #include "qemu/error-report.h"
20 #include "qemu/main-loop.h"
33 #include "exec/address-spaces.h"
80 init.target = cpu->kvm_target; in kvm_arm_vcpu_init()
81 memcpy(init.features, cpu->kvm_init_features, sizeof(init.features)); in kvm_arm_vcpu_init()
107 int ret = 0, kvmfd = -1, vmfd = -1, cpufd = -1; in kvm_arm_create_scratch_host_vcpu()
120 } while (vmfd == -1 && errno == EINTR); in kvm_arm_create_scratch_host_vcpu()
[all …]
/openbmc/qemu/target/m68k/
H A Dm68k-semi.c4 * Copyright (c) 2005-2007 CodeSourcery.
21 * https://sourceware.org/git/?p=newlib-cygwin.git;a=blob;f=libgloss/m68k/m68k-semi.txt;hb=HEAD
37 #define HOSTED_CLOSE 3
78 static void m68k_semi_u32_cb(CPUState *cs, uint64_t ret, int err) in m68k_semi_u32_cb() argument
80 CPUM68KState *env = cpu_env(cs); in m68k_semi_u32_cb()
82 target_ulong args = env->dregs[1]; in m68k_semi_u32_cb()
90 qemu_log_mask(LOG_GUEST_ERROR, "m68k-semihosting: return value " in m68k_semi_u32_cb()
95 static void m68k_semi_u64_cb(CPUState *cs, uint64_t ret, int err) in m68k_semi_u64_cb() argument
97 CPUM68KState *env = cpu_env(cs); in m68k_semi_u64_cb()
99 target_ulong args = env->dregs[1]; in m68k_semi_u64_cb()
[all …]

12345678910>>...45