Lines Matching +full:cs +full:- +full:3
4 * Copyright (c) 2003-2005 Fabrice Bellard
24 #include "exec/page-protection.h"
25 #include "qemu/qemu-print.h"
77 CPUState *cs = env_cpu(env); in get_physical_address() local
83 full->lg_page_size = TARGET_PAGE_BITS; in get_physical_address()
85 if (rw == 2 && (env->mmuregs[0] & env->def.mmu_bm)) { in get_physical_address()
86 full->phys_addr = env->prom_addr | (address & 0x7ffffULL); in get_physical_address()
87 full->prot = PAGE_READ | PAGE_EXEC; in get_physical_address()
90 full->phys_addr = address; in get_physical_address()
91 full->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; in get_physical_address()
96 full->phys_addr = 0xffffffffffff0000ULL; in get_physical_address()
98 /* SPARC reference MMU table walk: Context table->L1->L2->PTE */ in get_physical_address()
100 pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2); in get_physical_address()
101 pde = address_space_ldl(cs->as, pde_ptr, MEMTXATTRS_UNSPECIFIED, &result); in get_physical_address()
112 case 3: /* Reserved */ in get_physical_address()
115 pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4); in get_physical_address()
116 pde = address_space_ldl(cs->as, pde_ptr, in get_physical_address()
126 case 3: /* Reserved */ in get_physical_address()
129 pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4); in get_physical_address()
130 pde = address_space_ldl(cs->as, pde_ptr, in get_physical_address()
140 case 3: /* Reserved */ in get_physical_address()
143 pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4); in get_physical_address()
144 pde = address_space_ldl(cs->as, pde_ptr, in get_physical_address()
147 return (3 << 8) | (4 << 2); /* Translation fault, L = 3 */ in get_physical_address()
153 return (3 << 8) | (1 << 2); in get_physical_address()
155 case 3: /* Reserved */ in get_physical_address()
156 return (3 << 8) | (4 << 2); in get_physical_address()
160 full->lg_page_size = TARGET_PAGE_BITS; in get_physical_address()
164 full->lg_page_size = 18; in get_physical_address()
169 full->lg_page_size = 24; in get_physical_address()
177 if (error_code && !((env->mmuregs[0] & MMU_NF) && is_user)) { in get_physical_address()
188 stl_phys_notdirty(cs->as, pde_ptr, pde); in get_physical_address()
192 full->prot = perm_table[is_user][access_perms]; in get_physical_address()
196 full->prot &= ~PAGE_WRITE; in get_physical_address()
201 full->phys_addr = ((hwaddr)(pde & PTE_ADDR_MASK) << 4) + page_offset; in get_physical_address()
206 bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, in sparc_cpu_tlb_fill() argument
210 CPUSPARCState *env = cpu_env(cs); in sparc_cpu_tlb_fill()
229 "Translate at %" VADDR_PRIx " -> " in sparc_cpu_tlb_fill()
232 tlb_set_page_full(cs, mmu_idx, vaddr, &full); in sparc_cpu_tlb_fill()
236 if (env->mmuregs[3]) { /* Fault status register */ in sparc_cpu_tlb_fill()
237 env->mmuregs[3] = 1; /* overflow (not read before another fault) */ in sparc_cpu_tlb_fill()
239 env->mmuregs[3] |= (access_index << 5) | error_code | 2; in sparc_cpu_tlb_fill()
240 env->mmuregs[4] = address; /* Fault address register */ in sparc_cpu_tlb_fill()
242 if ((env->mmuregs[0] & MMU_NF) || env->psret == 0) { in sparc_cpu_tlb_fill()
248 tlb_set_page_full(cs, mmu_idx, vaddr, &full); in sparc_cpu_tlb_fill()
252 cs->exception_index = TT_TFAULT; in sparc_cpu_tlb_fill()
254 cs->exception_index = TT_DFAULT; in sparc_cpu_tlb_fill()
256 cpu_loop_exit_restore(cs, retaddr); in sparc_cpu_tlb_fill()
262 CPUState *cs = env_cpu(env); in mmu_probe() local
273 pde_ptr = (hwaddr)(env->mmuregs[1] << 4) + in mmu_probe()
274 (env->mmuregs[2] << 2); in mmu_probe()
275 pde = address_space_ldl(cs->as, pde_ptr, MEMTXATTRS_UNSPECIFIED, &result); in mmu_probe()
284 case 3: /* Reserved */ in mmu_probe()
287 if (mmulev == 3) { in mmu_probe()
290 pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4); in mmu_probe()
291 pde = address_space_ldl(cs->as, pde_ptr, in mmu_probe()
300 case 3: /* Reserved */ in mmu_probe()
308 pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4); in mmu_probe()
309 pde = address_space_ldl(cs->as, pde_ptr, in mmu_probe()
318 case 3: /* Reserved */ in mmu_probe()
326 pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4); in mmu_probe()
327 pde = address_space_ldl(cs->as, pde_ptr, in mmu_probe()
337 case 3: /* Reserved */ in mmu_probe()
350 CPUState *cs = env_cpu(env); in dump_mmu() local
357 (hwaddr)env->mmuregs[1] << 4, env->mmuregs[2]); in dump_mmu()
361 pa = cpu_get_phys_page_debug(cs, va); in dump_mmu()
367 pa = cpu_get_phys_page_debug(cs, va1); in dump_mmu()
374 pa = cpu_get_phys_page_debug(cs, va2); in dump_mmu()
391 int sparc_cpu_memory_rw_debug(CPUState *cs, vaddr address, in sparc_cpu_memory_rw_debug() argument
394 CPUSPARCState *env = cpu_env(cs); in sparc_cpu_memory_rw_debug()
398 int cwp = env->cwp; in sparc_cpu_memory_rw_debug()
401 for (i = 0; i < env->nwindows; i++) { in sparc_cpu_memory_rw_debug()
403 target_ulong fp = env->regbase[cwp * 16 + 22]; in sparc_cpu_memory_rw_debug()
413 if (env->wim & (1 << cwp)) { in sparc_cpu_memory_rw_debug()
429 len1 = fp - addr; in sparc_cpu_memory_rw_debug()
430 if (cpu_memory_rw_debug(cs, addr, buf, len1, is_write) != 0) { in sparc_cpu_memory_rw_debug()
431 return -1; in sparc_cpu_memory_rw_debug()
434 len -= len1; in sparc_cpu_memory_rw_debug()
441 off = addr - fp; in sparc_cpu_memory_rw_debug()
442 len1 = 64 - off; in sparc_cpu_memory_rw_debug()
448 for (; len1; len1--) { in sparc_cpu_memory_rw_debug()
454 u.v = cpu_to_be32(env->regbase[reg]); in sparc_cpu_memory_rw_debug()
455 *buf++ = u.c[off & 3]; in sparc_cpu_memory_rw_debug()
457 len--; in sparc_cpu_memory_rw_debug()
466 return cpu_memory_rw_debug(cs, addr, buf, len, is_write); in sparc_cpu_memory_rw_debug()
488 uint64_t mask = -(8192ULL << 3 * TTE_PGSIZE(tlb->tte)); in ultrasparc_tag_match()
491 if (TTE_IS_VALID(tlb->tte) && in ultrasparc_tag_match()
492 (TTE_IS_GLOBAL(tlb->tte) || tlb_compare_context(tlb, context)) in ultrasparc_tag_match()
493 && compare_masked(address, tlb->tag, mask)) { in ultrasparc_tag_match()
495 *physical = ((tlb->tte & mask) | (address & ~mask)) & 0x1ffffffe000ULL; in ultrasparc_tag_match()
531 if (env->pstate & PS_PRIV) { in build_sfsr()
535 if (env->dmmu.sfsr & SFSR_VALID_BIT) { /* Fault status register */ in build_sfsr()
547 CPUState *cs = env_cpu(env); in get_physical_address_data() local
562 context = env->dmmu.mmu_primary_context & 0x1fff; in get_physical_address_data()
568 context = env->dmmu.mmu_secondary_context & 0x1fff; in get_physical_address_data()
577 if (ultrasparc_tag_match(&env->dtlb[i], address, context, in get_physical_address_data()
578 &full->phys_addr)) { in get_physical_address_data()
581 if (TTE_IS_IE(env->dtlb[i].tte)) { in get_physical_address_data()
582 full->tlb_fill_flags |= TLB_BSWAP; in get_physical_address_data()
587 if (TTE_IS_PRIV(env->dtlb[i].tte) && is_user) { in get_physical_address_data()
590 trace_mmu_helper_dfault(address, context, mmu_idx, env->tl); in get_physical_address_data()
593 if (TTE_IS_SIDEEFFECT(env->dtlb[i].tte)) { in get_physical_address_data()
598 if (TTE_IS_NFO(env->dtlb[i].tte)) { in get_physical_address_data()
606 cs->exception_index = TT_DFAULT; in get_physical_address_data()
607 } else if (!TTE_IS_W_OK(env->dtlb[i].tte) && (rw == 1)) { in get_physical_address_data()
609 cs->exception_index = TT_DPROT; in get_physical_address_data()
611 trace_mmu_helper_dprot(address, context, mmu_idx, env->tl); in get_physical_address_data()
615 full->prot = PAGE_READ; in get_physical_address_data()
616 if (TTE_IS_W_OK(env->dtlb[i].tte)) { in get_physical_address_data()
617 full->prot |= PAGE_WRITE; in get_physical_address_data()
620 TTE_SET_USED(env->dtlb[i].tte); in get_physical_address_data()
625 env->dmmu.sfsr = sfsr; in get_physical_address_data()
626 env->dmmu.sfar = address; /* Fault address register */ in get_physical_address_data()
627 env->dmmu.tag_access = (address & ~0x1fffULL) | context; in get_physical_address_data()
636 * - UltraSPARC IIi: SFSR and SFAR unmodified in get_physical_address_data()
637 * - JPS1: SFAR updated and some fields of SFSR updated in get_physical_address_data()
639 env->dmmu.tag_access = (address & ~0x1fffULL) | context; in get_physical_address_data()
640 cs->exception_index = TT_DMISS; in get_physical_address_data()
647 CPUState *cs = env_cpu(env); in get_physical_address_code() local
661 context = env->dmmu.mmu_primary_context & 0x1fff; in get_physical_address_code()
668 if (env->tl == 0) { in get_physical_address_code()
670 context = env->dmmu.mmu_primary_context & 0x1fff; in get_physical_address_code()
678 if (ultrasparc_tag_match(&env->itlb[i], in get_physical_address_code()
679 address, context, &full->phys_addr)) { in get_physical_address_code()
681 if (TTE_IS_PRIV(env->itlb[i].tte) && is_user) { in get_physical_address_code()
683 if (env->immu.sfsr & SFSR_VALID_BIT) { in get_physical_address_code()
684 env->immu.sfsr = SFSR_OW_BIT; /* overflow (not read before in get_physical_address_code()
687 env->immu.sfsr = 0; in get_physical_address_code()
689 if (env->pstate & PS_PRIV) { in get_physical_address_code()
690 env->immu.sfsr |= SFSR_PR_BIT; in get_physical_address_code()
692 if (env->tl > 0) { in get_physical_address_code()
693 env->immu.sfsr |= SFSR_CT_NUCLEUS; in get_physical_address_code()
697 env->immu.sfsr |= SFSR_FT_PRIV_BIT | SFSR_VALID_BIT; in get_physical_address_code()
698 cs->exception_index = TT_TFAULT; in get_physical_address_code()
700 env->immu.tag_access = (address & ~0x1fffULL) | context; in get_physical_address_code()
706 full->prot = PAGE_EXEC; in get_physical_address_code()
707 TTE_SET_USED(env->itlb[i].tte); in get_physical_address_code()
715 env->immu.tag_access = (address & ~0x1fffULL) | context; in get_physical_address_code()
716 cs->exception_index = TT_TMISS; in get_physical_address_code()
726 full->lg_page_size = TARGET_PAGE_BITS; in get_physical_address()
729 if (env->tl > 0 && mmu_idx != MMU_NUCLEUS_IDX) { in get_physical_address()
731 trace_mmu_helper_get_phys_addr_code(env->tl, mmu_idx, in get_physical_address()
732 env->dmmu.mmu_primary_context, in get_physical_address()
733 env->dmmu.mmu_secondary_context, in get_physical_address()
736 trace_mmu_helper_get_phys_addr_data(env->tl, mmu_idx, in get_physical_address()
737 env->dmmu.mmu_primary_context, in get_physical_address()
738 env->dmmu.mmu_secondary_context, in get_physical_address()
744 full->phys_addr = ultrasparc_truncate_physical(address); in get_physical_address()
745 full->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; in get_physical_address()
757 bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, in sparc_cpu_tlb_fill() argument
761 CPUSPARCState *env = cpu_env(cs); in sparc_cpu_tlb_fill()
769 trace_mmu_helper_mmu_fault(address, full.phys_addr, mmu_idx, env->tl, in sparc_cpu_tlb_fill()
770 env->dmmu.mmu_primary_context, in sparc_cpu_tlb_fill()
771 env->dmmu.mmu_secondary_context); in sparc_cpu_tlb_fill()
772 tlb_set_page_full(cs, mmu_idx, address, &full); in sparc_cpu_tlb_fill()
778 cpu_loop_exit_restore(cs, retaddr); in sparc_cpu_tlb_fill()
788 env->dmmu.mmu_primary_context, in dump_mmu()
789 env->dmmu.mmu_secondary_context); in dump_mmu()
791 "\n", env->dmmu.tag_access, env->dmmu.tsb_tag_target); in dump_mmu()
792 if ((env->lsu & DMMU_E) == 0) { in dump_mmu()
797 switch (TTE_PGSIZE(env->dtlb[i].tte)) { in dump_mmu()
812 if (TTE_IS_VALID(env->dtlb[i].tte)) { in dump_mmu()
816 env->dtlb[i].tag & (uint64_t)~0x1fffULL, in dump_mmu()
817 TTE_PA(env->dtlb[i].tte), in dump_mmu()
819 TTE_IS_PRIV(env->dtlb[i].tte) ? "priv" : "user", in dump_mmu()
820 TTE_IS_W_OK(env->dtlb[i].tte) ? "RW" : "RO", in dump_mmu()
821 TTE_IS_LOCKED(env->dtlb[i].tte) ? in dump_mmu()
823 TTE_IS_IE(env->dtlb[i].tte) ? in dump_mmu()
825 env->dtlb[i].tag & (uint64_t)0x1fffULL, in dump_mmu()
826 TTE_IS_GLOBAL(env->dtlb[i].tte) ? in dump_mmu()
831 if ((env->lsu & IMMU_E) == 0) { in dump_mmu()
836 switch (TTE_PGSIZE(env->itlb[i].tte)) { in dump_mmu()
851 if (TTE_IS_VALID(env->itlb[i].tte)) { in dump_mmu()
855 env->itlb[i].tag & (uint64_t)~0x1fffULL, in dump_mmu()
856 TTE_PA(env->itlb[i].tte), in dump_mmu()
858 TTE_IS_PRIV(env->itlb[i].tte) ? "priv" : "user", in dump_mmu()
859 TTE_IS_LOCKED(env->itlb[i].tte) ? in dump_mmu()
861 env->itlb[i].tag & (uint64_t)0x1fffULL, in dump_mmu()
862 TTE_IS_GLOBAL(env->itlb[i].tte) ? in dump_mmu()
891 return -1; in cpu_get_phys_page_nofault()
897 hwaddr sparc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) in sparc_cpu_get_phys_page_debug() argument
899 CPUSPARCState *env = cpu_env(cs); in sparc_cpu_get_phys_page_debug()
901 int mmu_idx = cpu_mmu_index(cs, false); in sparc_cpu_get_phys_page_debug()
905 return -1; in sparc_cpu_get_phys_page_debug()
911 G_NORETURN void sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr, in sparc_cpu_do_unaligned_access() argument
916 CPUSPARCState *env = cpu_env(cs); in sparc_cpu_do_unaligned_access()
919 env->dmmu.sfsr = build_sfsr(env, mmu_idx, access_type); in sparc_cpu_do_unaligned_access()
920 env->dmmu.sfar = addr; in sparc_cpu_do_unaligned_access()
922 env->mmuregs[4] = addr; in sparc_cpu_do_unaligned_access()