6  * SPDX-License-Identifier: GPL-2.0-or-later
13 #include "cpu-features.h"
54     CPUState *cs = env_cpu(env);  in tlbiall_is_write()  local
56     tlb_flush_all_cpus_synced(cs);  in tlbiall_is_write()
62     CPUState *cs = env_cpu(env);  in tlbiasid_is_write()  local
64     tlb_flush_all_cpus_synced(cs);  in tlbiasid_is_write()
70     CPUState *cs = env_cpu(env);  in tlbimva_is_write()  local
72     tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK);  in tlbimva_is_write()
78     CPUState *cs = env_cpu(env);  in tlbimvaa_is_write()  local
80     tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK);  in tlbimvaa_is_write()
84  * Non-IS variants of TLB operations are upgraded to
97     CPUState *cs = env_cpu(env);  in tlbiall_write()  local
100         tlb_flush_all_cpus_synced(cs);  in tlbiall_write()
102         tlb_flush(cs);  in tlbiall_write()
110     CPUState *cs = env_cpu(env);  in tlbimva_write()  local
114         tlb_flush_page_all_cpus_synced(cs, value);  in tlbimva_write()
116         tlb_flush_page(cs, value);  in tlbimva_write()
124     CPUState *cs = env_cpu(env);  in tlbiasid_write()  local
127         tlb_flush_all_cpus_synced(cs);  in tlbiasid_write()
129         tlb_flush(cs);  in tlbiasid_write()
137     CPUState *cs = env_cpu(env);  in tlbimvaa_write()  local
141         tlb_flush_page_all_cpus_synced(cs, value);  in tlbimvaa_write()
143         tlb_flush_page(cs, value);  in tlbimvaa_write()
150     CPUState *cs = env_cpu(env);  in tlbimva_hyp_write()  local
153     tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E2);  in tlbimva_hyp_write()
159     CPUState *cs = env_cpu(env);  in tlbimva_hyp_is_write()  local
162     tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,  in tlbimva_hyp_is_write()
169     CPUState *cs = env_cpu(env);  in tlbiipas2_hyp_write()  local
172     tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_Stage2);  in tlbiipas2_hyp_write()
178     CPUState *cs = env_cpu(env);  in tlbiipas2is_hyp_write()  local
181     tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, ARMMMUIdxBit_Stage2);  in tlbiipas2is_hyp_write()
187     CPUState *cs = env_cpu(env);  in tlbiall_nsnh_write()  local
189     tlb_flush_by_mmuidx(cs, alle1_tlbmask(env));  in tlbiall_nsnh_write()
195     CPUState *cs = env_cpu(env);  in tlbiall_nsnh_is_write()  local
197     tlb_flush_by_mmuidx_all_cpus_synced(cs, alle1_tlbmask(env));  in tlbiall_nsnh_is_write()
204     CPUState *cs = env_cpu(env);  in tlbiall_hyp_write()  local
206     tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E2);  in tlbiall_hyp_write()
212     CPUState *cs = env_cpu(env);  in tlbiall_hyp_is_write()  local
214     tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E2);  in tlbiall_hyp_is_write()
219  * Page D4-1736 (DDI0487A.b)
307     CPUState *cs = env_cpu(env);  in tlbi_aa64_vmalle1is_write()  local
310     tlb_flush_by_mmuidx_all_cpus_synced(cs, mask);  in tlbi_aa64_vmalle1is_write()
316     CPUState *cs = env_cpu(env);  in tlbi_aa64_vmalle1_write()  local
320         tlb_flush_by_mmuidx_all_cpus_synced(cs, mask);  in tlbi_aa64_vmalle1_write()
322         tlb_flush_by_mmuidx(cs, mask);  in tlbi_aa64_vmalle1_write()
337     CPUState *cs = env_cpu(env);  in tlbi_aa64_alle1_write()  local
340     tlb_flush_by_mmuidx(cs, mask);  in tlbi_aa64_alle1_write()
346     CPUState *cs = env_cpu(env);  in tlbi_aa64_alle2_write()  local
349     tlb_flush_by_mmuidx(cs, mask);  in tlbi_aa64_alle2_write()
356     CPUState *cs = CPU(cpu);  in tlbi_aa64_alle3_write()  local
358     tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E3);  in tlbi_aa64_alle3_write()
364     CPUState *cs = env_cpu(env);  in tlbi_aa64_alle1is_write()  local
367     tlb_flush_by_mmuidx_all_cpus_synced(cs, mask);  in tlbi_aa64_alle1is_write()
373     CPUState *cs = env_cpu(env);  in tlbi_aa64_alle2is_write()  local
376     tlb_flush_by_mmuidx_all_cpus_synced(cs, mask);  in tlbi_aa64_alle2is_write()
382     CPUState *cs = env_cpu(env);  in tlbi_aa64_alle3is_write()  local
384     tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E3);  in tlbi_aa64_alle3is_write()
393      * flush-last-level-only.  in tlbi_aa64_vae2_write()
395     CPUState *cs = env_cpu(env);  in tlbi_aa64_vae2_write()  local
400     tlb_flush_page_bits_by_mmuidx(cs, pageaddr, mask, bits);  in tlbi_aa64_vae2_write()
409      * flush-last-level-only.  in tlbi_aa64_vae3_write()
412     CPUState *cs = CPU(cpu);  in tlbi_aa64_vae3_write()  local
415     tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E3);  in tlbi_aa64_vae3_write()
421     CPUState *cs = env_cpu(env);  in tlbi_aa64_vae1is_write()  local
426     tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits);  in tlbi_aa64_vae1is_write()
435      * since we don't support flush-for-specific-ASID-only or  in tlbi_aa64_vae1_write()
436      * flush-last-level-only.  in tlbi_aa64_vae1_write()
438     CPUState *cs = env_cpu(env);  in tlbi_aa64_vae1_write()  local
444         tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits);  in tlbi_aa64_vae1_write()
446         tlb_flush_page_bits_by_mmuidx(cs, pageaddr, mask, bits);  in tlbi_aa64_vae1_write()
453     CPUState *cs = env_cpu(env);  in tlbi_aa64_vae2is_write()  local
458     tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits);  in tlbi_aa64_vae2is_write()
464     CPUState *cs = env_cpu(env);  in tlbi_aa64_vae3is_write()  local
468     tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr,  in tlbi_aa64_vae3is_write()
488     CPUState *cs = env_cpu(env);  in tlbi_aa64_ipas2e1_write()  local
493         tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, mask);  in tlbi_aa64_ipas2e1_write()
495         tlb_flush_page_by_mmuidx(cs, pageaddr, mask);  in tlbi_aa64_ipas2e1_write()
502     CPUState *cs = env_cpu(env);  in tlbi_aa64_ipas2e1is_write()  local
506     tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, mask);  in tlbi_aa64_ipas2e1is_write()
512      * the unified TLB ops but also the dside/iside/inner-shareable variants.
524       .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write,
559     { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
566     { .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
569     { .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
572     { .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
575     { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
582     { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
585     { .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
598       .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5,
619       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
625       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
631       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
637       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
643       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
649       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
673       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
699       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4,
703       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 6,
730       .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4,
736     { .name = "TLBIALLHIS", .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0,
742     { .name = "TLBIMVAHIS", .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1,
761       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0,
766       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1,
771       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5,
779       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 0,
783       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 1,
787       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 5,
821     case 3:  in tlbi_range_tg_to_gran_size()
902      * since we don't support flush-for-specific-ASID-only or  in tlbi_aa64_rvae1_write()
903      * flush-last-level-only.  in tlbi_aa64_rvae1_write()
918      * flush-for-specific-ASID-only, flush-last-level-only or inner/outer  in tlbi_aa64_rvae1is_write()
932      * since we don't support flush-for-specific-ASID-only or  in tlbi_aa64_rvae2_write()
933      * flush-last-level-only.  in tlbi_aa64_rvae2_write()
949      * since we don't support flush-for-specific-ASID-only,  in tlbi_aa64_rvae2is_write()
950      * flush-last-level-only or inner/outer shareable specific flushes.  in tlbi_aa64_rvae2is_write()
964      * since we don't support flush-for-specific-ASID-only or  in tlbi_aa64_rvae3_write()
965      * flush-last-level-only.  in tlbi_aa64_rvae3_write()
978      * since we don't support flush-for-specific-ASID-only,  in tlbi_aa64_rvae3is_write()
979      * flush-last-level-only or inner/outer specific flushes.  in tlbi_aa64_rvae3is_write()
1007       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 3,
1031       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 3,
1055       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 3,
1164       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 3,
1209       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 3,
1234     CPUState *cs = env_cpu(env);  in tlbi_aa64_paall_write()  local
1236     tlb_flush(cs);  in tlbi_aa64_paall_write()
1242     CPUState *cs = env_cpu(env);  in tlbi_aa64_paallos_write()  local
1244     tlb_flush_all_cpus_synced(cs);  in tlbi_aa64_paallos_write()
1267       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 4, .opc2 = 3,
1276     CPUARMState *env = &cpu->env;  in define_tlb_insn_regs()