Lines Matching +full:cs +full:- +full:3
21 #include "qapi/qapi-events-run-state.h"
24 #include "exec/translation-block.h"
33 #include "tcg/insn-start-words.h"
38 if ((env->cr[4] & CR4_OSXSAVE_MASK) in cpu_sync_avx_hflag()
39 && (env->xcr0 & (XSTATE_SSE_MASK | XSTATE_YMM_MASK)) in cpu_sync_avx_hflag()
41 env->hflags |= HF_AVX_EN_MASK; in cpu_sync_avx_hflag()
43 env->hflags &= ~HF_AVX_EN_MASK; in cpu_sync_avx_hflag()
49 uint32_t hflags = env->hflags; in cpu_sync_bndcs_hflags()
50 uint32_t hflags2 = env->hflags2; in cpu_sync_bndcs_hflags()
53 if ((hflags & HF_CPL_MASK) == 3) { in cpu_sync_bndcs_hflags()
54 bndcsr = env->bndcs_regs.cfgu; in cpu_sync_bndcs_hflags()
56 bndcsr = env->msr_bndcfgs; in cpu_sync_bndcs_hflags()
59 if ((env->cr[4] & CR4_OSXSAVE_MASK) in cpu_sync_bndcs_hflags()
60 && (env->xcr0 & XSTATE_BNDCSR_MASK) in cpu_sync_bndcs_hflags()
73 env->hflags = hflags; in cpu_sync_bndcs_hflags()
74 env->hflags2 = hflags2; in cpu_sync_bndcs_hflags()
79 int cpuver = env->cpuid_version; in cpu_x86_version()
113 CPUX86State *env = &cpu->env; in x86_cpu_set_a20()
116 if (a20_state != ((env->a20_mask >> 20) & 1)) { in x86_cpu_set_a20()
117 CPUState *cs = CPU(cpu); in x86_cpu_set_a20() local
122 cpu_interrupt(cs, CPU_INTERRUPT_EXITTB); in x86_cpu_set_a20()
126 tlb_flush(cs); in x86_cpu_set_a20()
127 env->a20_mask = ~(1 << 20) | (a20_state << 20); in x86_cpu_set_a20()
138 (env->cr[0] & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK))) { in cpu_x86_update_cr0()
143 if (!(env->cr[0] & CR0_PG_MASK) && (new_cr0 & CR0_PG_MASK) && in cpu_x86_update_cr0()
144 (env->efer & MSR_EFER_LME)) { in cpu_x86_update_cr0()
147 if (!(env->cr[4] & CR4_PAE_MASK)) in cpu_x86_update_cr0()
149 env->efer |= MSR_EFER_LMA; in cpu_x86_update_cr0()
150 env->hflags |= HF_LMA_MASK; in cpu_x86_update_cr0()
151 } else if ((env->cr[0] & CR0_PG_MASK) && !(new_cr0 & CR0_PG_MASK) && in cpu_x86_update_cr0()
152 (env->efer & MSR_EFER_LMA)) { in cpu_x86_update_cr0()
154 env->efer &= ~MSR_EFER_LMA; in cpu_x86_update_cr0()
155 env->hflags &= ~(HF_LMA_MASK | HF_CS64_MASK); in cpu_x86_update_cr0()
156 env->eip &= 0xffffffff; in cpu_x86_update_cr0()
159 env->cr[0] = new_cr0 | CR0_ET_MASK; in cpu_x86_update_cr0()
162 pe_state = (env->cr[0] & CR0_PE_MASK); in cpu_x86_update_cr0()
163 env->hflags = (env->hflags & ~HF_PE_MASK) | (pe_state << HF_PE_SHIFT); in cpu_x86_update_cr0()
165 env->hflags |= ((pe_state ^ 1) << HF_ADDSEG_SHIFT); in cpu_x86_update_cr0()
167 env->hflags = (env->hflags & ~(HF_MP_MASK | HF_EM_MASK | HF_TS_MASK)) | in cpu_x86_update_cr0()
168 ((new_cr0 << (HF_MP_SHIFT - 1)) & (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK)); in cpu_x86_update_cr0()
175 env->cr[3] = new_cr3; in cpu_x86_update_cr3()
176 if (env->cr[0] & CR0_PG_MASK) { in cpu_x86_update_cr3()
188 printf("CR4 update: %08x -> %08x\n", (uint32_t)env->cr[4], new_cr4); in cpu_x86_update_cr4()
190 if ((new_cr4 ^ env->cr[4]) & in cpu_x86_update_cr4()
197 hflags = env->hflags & ~(HF_OSFXSR_MASK | HF_SMAP_MASK | HF_UMIP_MASK); in cpu_x86_update_cr4()
200 if (!(env->features[FEAT_1_EDX] & CPUID_SSE)) { in cpu_x86_update_cr4()
207 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SMAP)) { in cpu_x86_update_cr4()
213 if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_UMIP)) { in cpu_x86_update_cr4()
220 if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_PKU)) { in cpu_x86_update_cr4()
223 if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_PKS)) { in cpu_x86_update_cr4()
227 if (!(env->features[FEAT_7_1_EAX] & CPUID_7_1_EAX_LAM)) { in cpu_x86_update_cr4()
231 env->cr[4] = new_cr4; in cpu_x86_update_cr4()
232 env->hflags = hflags; in cpu_x86_update_cr4()
239 hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, in x86_cpu_get_phys_page_attrs_debug() argument
242 X86CPU *cpu = X86_CPU(cs); in x86_cpu_get_phys_page_attrs_debug()
243 CPUX86State *env = &cpu->env; in x86_cpu_get_phys_page_attrs_debug()
253 if (!(env->cr[0] & CR0_PG_MASK)) { in x86_cpu_get_phys_page_attrs_debug()
256 } else if (env->cr[4] & CR4_PAE_MASK) { in x86_cpu_get_phys_page_attrs_debug()
261 if (env->hflags & HF_LMA_MASK) { in x86_cpu_get_phys_page_attrs_debug()
262 bool la57 = env->cr[4] & CR4_LA57_MASK; in x86_cpu_get_phys_page_attrs_debug()
269 if (sext != 0 && sext != -1) { in x86_cpu_get_phys_page_attrs_debug()
270 return -1; in x86_cpu_get_phys_page_attrs_debug()
274 pml5e_addr = ((env->cr[3] & ~0xfff) + in x86_cpu_get_phys_page_attrs_debug()
275 (((addr >> 48) & 0x1ff) << 3)) & a20_mask; in x86_cpu_get_phys_page_attrs_debug()
276 pml5e = x86_ldq_phys(cs, pml5e_addr); in x86_cpu_get_phys_page_attrs_debug()
278 return -1; in x86_cpu_get_phys_page_attrs_debug()
281 pml5e = env->cr[3]; in x86_cpu_get_phys_page_attrs_debug()
285 (((addr >> 39) & 0x1ff) << 3)) & a20_mask; in x86_cpu_get_phys_page_attrs_debug()
286 pml4e = x86_ldq_phys(cs, pml4e_addr); in x86_cpu_get_phys_page_attrs_debug()
288 return -1; in x86_cpu_get_phys_page_attrs_debug()
291 (((addr >> 30) & 0x1ff) << 3)) & a20_mask; in x86_cpu_get_phys_page_attrs_debug()
292 pdpe = x86_ldq_phys(cs, pdpe_addr); in x86_cpu_get_phys_page_attrs_debug()
294 return -1; in x86_cpu_get_phys_page_attrs_debug()
305 pdpe_addr = ((env->cr[3] & ~0x1f) + ((addr >> 27) & 0x18)) & in x86_cpu_get_phys_page_attrs_debug()
307 pdpe = x86_ldq_phys(cs, pdpe_addr); in x86_cpu_get_phys_page_attrs_debug()
309 return -1; in x86_cpu_get_phys_page_attrs_debug()
313 (((addr >> 21) & 0x1ff) << 3)) & a20_mask; in x86_cpu_get_phys_page_attrs_debug()
314 pde = x86_ldq_phys(cs, pde_addr); in x86_cpu_get_phys_page_attrs_debug()
316 return -1; in x86_cpu_get_phys_page_attrs_debug()
325 (((addr >> 12) & 0x1ff) << 3)) & a20_mask; in x86_cpu_get_phys_page_attrs_debug()
327 pte = x86_ldq_phys(cs, pte_addr); in x86_cpu_get_phys_page_attrs_debug()
330 return -1; in x86_cpu_get_phys_page_attrs_debug()
336 pde_addr = ((env->cr[3] & ~0xfff) + ((addr >> 20) & 0xffc)) & a20_mask; in x86_cpu_get_phys_page_attrs_debug()
337 pde = x86_ldl_phys(cs, pde_addr); in x86_cpu_get_phys_page_attrs_debug()
339 return -1; in x86_cpu_get_phys_page_attrs_debug()
340 if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) { in x86_cpu_get_phys_page_attrs_debug()
341 pte = pde | ((pde & 0x1fe000LL) << (32 - 13)); in x86_cpu_get_phys_page_attrs_debug()
346 pte = x86_ldl_phys(cs, pte_addr); in x86_cpu_get_phys_page_attrs_debug()
348 return -1; in x86_cpu_get_phys_page_attrs_debug()
358 pte &= PG_ADDRESS_MASK & ~(page_size - 1); in x86_cpu_get_phys_page_attrs_debug()
359 page_offset = (addr & TARGET_PAGE_MASK) & (page_size - 1); in x86_cpu_get_phys_page_attrs_debug()
382 static void do_inject_x86_mce(CPUState *cs, run_on_cpu_data data) in do_inject_x86_mce() argument
385 X86CPU *cpu = X86_CPU(cs); in do_inject_x86_mce()
386 CPUX86State *cenv = &cpu->env; in do_inject_x86_mce()
387 uint64_t *banks = cenv->mce_banks + 4 * params->bank; in do_inject_x86_mce()
391 bool ar = !!(params->status & MCI_STATUS_AR); in do_inject_x86_mce()
393 cpu_synchronize_state(cs); in do_inject_x86_mce()
394 recursive = !!(cenv->mcg_status & MCG_STATUS_MCIP); in do_inject_x86_mce()
400 if (!(params->flags & MCE_INJECT_UNCOND_AO) && !ar && recursive) { in do_inject_x86_mce()
405 if (params->status & MCI_STATUS_UC) { in do_inject_x86_mce()
410 if ((cenv->mcg_cap & MCG_CTL_P) && cenv->mcg_ctl != ~(uint64_t)0) { in do_inject_x86_mce()
411 monitor_printf(params->mon, in do_inject_x86_mce()
413 cs->cpu_index); in do_inject_x86_mce()
422 monitor_printf(params->mon, in do_inject_x86_mce()
425 cs->cpu_index, params->bank); in do_inject_x86_mce()
429 if (!(cenv->cr[4] & CR4_MCE_MASK)) { in do_inject_x86_mce()
432 "raising triple fault", cs->cpu_index); in do_inject_x86_mce()
436 "raising triple fault", cs->cpu_index); in do_inject_x86_mce()
442 monitor_printf(params->mon, "%s", msg); in do_inject_x86_mce()
449 params->status |= MCI_STATUS_OVER; in do_inject_x86_mce()
451 banks[2] = params->addr; in do_inject_x86_mce()
452 banks[3] = params->misc; in do_inject_x86_mce()
453 cenv->mcg_status = params->mcg_status; in do_inject_x86_mce()
454 banks[1] = params->status; in do_inject_x86_mce()
455 cpu_interrupt(cs, CPU_INTERRUPT_MCE); in do_inject_x86_mce()
459 params->status |= MCI_STATUS_OVER; in do_inject_x86_mce()
461 banks[2] = params->addr; in do_inject_x86_mce()
462 banks[3] = params->misc; in do_inject_x86_mce()
463 banks[1] = params->status; in do_inject_x86_mce()
475 CPUState *cs = CPU(cpu); in cpu_x86_inject_mce() local
476 CPUX86State *cenv = &cpu->env; in cpu_x86_inject_mce()
486 unsigned bank_num = cenv->mcg_cap & 0xff; in cpu_x86_inject_mce()
488 if (!cenv->mcg_cap) { in cpu_x86_inject_mce()
506 run_on_cpu(cs, do_inject_x86_mce, RUN_ON_CPU_HOST_PTR(¶ms)); in cpu_x86_inject_mce()
516 if (other_cs == cs) { in cpu_x86_inject_mce()
528 CPUState *cs = env_cpu(env); in get_memio_eip() local
530 if (!cpu_unwind_state_data(cs, cs->mem_io_pc, data)) { in get_memio_eip()
531 return env->eip; in get_memio_eip()
535 if (tcg_cflags_has(cs, CF_PCREL)) { in get_memio_eip()
536 return (env->eip & TARGET_PAGE_MASK) | data[0]; in get_memio_eip()
538 return data[0] - env->segs[R_CS].base; in get_memio_eip()
548 CPUState *cs = env_cpu(env); in cpu_report_tpr_access() local
551 env->tpr_access_type = access; in cpu_report_tpr_access()
553 cpu_interrupt(cs, CPU_INTERRUPT_TPR); in cpu_report_tpr_access()
557 apic_handle_tpr_access_report(cpu->apic_state, eip, access); in cpu_report_tpr_access()
566 CPUState *cs = env_cpu(env); in cpu_x86_get_descr_debug() local
573 dt = &env->ldt; in cpu_x86_get_descr_debug()
575 dt = &env->gdt; in cpu_x86_get_descr_debug()
577 ptr = dt->base + index; in cpu_x86_get_descr_debug()
578 if ((index + 7) > dt->limit in cpu_x86_get_descr_debug()
579 || cpu_memory_rw_debug(cs, ptr, (uint8_t *)&e1, sizeof(e1), 0) != 0 in cpu_x86_get_descr_debug()
580 || cpu_memory_rw_debug(cs, ptr+4, (uint8_t *)&e2, sizeof(e2), 0) != 0) in cpu_x86_get_descr_debug()
595 CPUState *cs = CPU(cpu); in do_cpu_init() local
596 CPUX86State *env = &cpu->env; in do_cpu_init()
598 int sipi = cs->interrupt_request & CPU_INTERRUPT_SIPI; in do_cpu_init()
602 cpu_reset(cs); in do_cpu_init()
603 cs->interrupt_request = sipi; in do_cpu_init()
604 memcpy(&env->start_init_save, &save->start_init_save, in do_cpu_init()
605 offsetof(CPUX86State, end_init_save) - in do_cpu_init()
612 apic_init_reset(cpu->apic_state); in do_cpu_init()
620 apic_sipi(cpu->apic_state); in do_cpu_sipi()
625 env->efer = val; in cpu_load_efer()
626 env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK); in cpu_load_efer()
627 if (env->efer & MSR_EFER_LMA) { in cpu_load_efer()
628 env->hflags |= HF_LMA_MASK; in cpu_load_efer()
630 if (env->efer & MSR_EFER_SVME) { in cpu_load_efer()
631 env->hflags |= HF_SVME_MASK; in cpu_load_efer()
635 uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr) in x86_ldub_phys() argument
637 X86CPU *cpu = X86_CPU(cs); in x86_ldub_phys()
638 CPUX86State *env = &cpu->env; in x86_ldub_phys()
640 AddressSpace *as = cpu_addressspace(cs, attrs); in x86_ldub_phys()
645 uint32_t x86_lduw_phys(CPUState *cs, hwaddr addr) in x86_lduw_phys() argument
647 X86CPU *cpu = X86_CPU(cs); in x86_lduw_phys()
648 CPUX86State *env = &cpu->env; in x86_lduw_phys()
650 AddressSpace *as = cpu_addressspace(cs, attrs); in x86_lduw_phys()
655 uint32_t x86_ldl_phys(CPUState *cs, hwaddr addr) in x86_ldl_phys() argument
657 X86CPU *cpu = X86_CPU(cs); in x86_ldl_phys()
658 CPUX86State *env = &cpu->env; in x86_ldl_phys()
660 AddressSpace *as = cpu_addressspace(cs, attrs); in x86_ldl_phys()
665 uint64_t x86_ldq_phys(CPUState *cs, hwaddr addr) in x86_ldq_phys() argument
667 X86CPU *cpu = X86_CPU(cs); in x86_ldq_phys()
668 CPUX86State *env = &cpu->env; in x86_ldq_phys()
670 AddressSpace *as = cpu_addressspace(cs, attrs); in x86_ldq_phys()
675 void x86_stb_phys(CPUState *cs, hwaddr addr, uint8_t val) in x86_stb_phys() argument
677 X86CPU *cpu = X86_CPU(cs); in x86_stb_phys()
678 CPUX86State *env = &cpu->env; in x86_stb_phys()
680 AddressSpace *as = cpu_addressspace(cs, attrs); in x86_stb_phys()
685 void x86_stl_phys_notdirty(CPUState *cs, hwaddr addr, uint32_t val) in x86_stl_phys_notdirty() argument
687 X86CPU *cpu = X86_CPU(cs); in x86_stl_phys_notdirty()
688 CPUX86State *env = &cpu->env; in x86_stl_phys_notdirty()
690 AddressSpace *as = cpu_addressspace(cs, attrs); in x86_stl_phys_notdirty()
695 void x86_stw_phys(CPUState *cs, hwaddr addr, uint32_t val) in x86_stw_phys() argument
697 X86CPU *cpu = X86_CPU(cs); in x86_stw_phys()
698 CPUX86State *env = &cpu->env; in x86_stw_phys()
700 AddressSpace *as = cpu_addressspace(cs, attrs); in x86_stw_phys()
705 void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val) in x86_stl_phys() argument
707 X86CPU *cpu = X86_CPU(cs); in x86_stl_phys()
708 CPUX86State *env = &cpu->env; in x86_stl_phys()
710 AddressSpace *as = cpu_addressspace(cs, attrs); in x86_stl_phys()
715 void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val) in x86_stq_phys() argument
717 X86CPU *cpu = X86_CPU(cs); in x86_stq_phys()
718 CPUX86State *env = &cpu->env; in x86_stq_phys()
720 AddressSpace *as = cpu_addressspace(cs, attrs); in x86_stq_phys()