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Searched refs:port_clock (Results 1 – 25 of 32) sorted by relevance

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/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_ddi_buf_trans.c1306 if (crtc_state->port_clock > 540000) { in icl_get_combo_buf_trans_edp()
1335 if (crtc_state->port_clock > 270000) { in icl_get_mg_buf_trans_dp()
1360 if (crtc_state->port_clock > 270000) in ehl_get_combo_buf_trans_edp()
1385 if (crtc_state->port_clock > 270000) in jsl_get_combo_buf_trans_edp()
1412 if (crtc_state->port_clock > 270000) { in tgl_get_combo_buf_trans_dp()
1463 if (crtc_state->port_clock > 270000) in dg1_get_combo_buf_trans_dp()
1476 if (crtc_state->port_clock > 540000) in dg1_get_combo_buf_trans_edp()
1507 if (crtc_state->port_clock > 270000) in rkl_get_combo_buf_trans_dp()
1550 if (crtc_state->port_clock > 270000) in adls_get_combo_buf_trans_dp()
1561 if (crtc_state->port_clock > 540000) in adls_get_combo_buf_trans_edp()
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H A Dintel_dpll.c772 crtc_state->port_clock, refclk, in bxt_find_best_dpll()
1178 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in ilk_crtc_compute_clock()
1189 crtc_state->port_clock = crtc_state->dpll.dot; in ilk_crtc_compute_clock()
1252 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in chv_crtc_compute_clock()
1262 crtc_state->port_clock = crtc_state->dpll.dot; in chv_crtc_compute_clock()
1288 crtc_state->port_clock = crtc_state->dpll.dot; in vlv_crtc_compute_clock()
1333 crtc_state->port_clock = crtc_state->dpll.dot; in g4x_crtc_compute_clock()
1371 crtc_state->port_clock = crtc_state->dpll.dot; in pnv_crtc_compute_clock()
1407 crtc_state->port_clock = crtc_state->dpll.dot; in i9xx_crtc_compute_clock()
1447 crtc_state->port_clock = crtc_state->dpll.dot; in i8xx_crtc_compute_clock()
[all …]
H A Dintel_pmdemand.c135 enum pipe pipe, int port_clock) in intel_pmdemand_update_port_clock() argument
140 pmdemand_state->ddi_clocks[pipe] = port_clock; in intel_pmdemand_update_port_clock()
156 new_crtc_state->port_clock); in intel_pmdemand_update_max_ddiclk()
300 if (new_crtc_state->port_clock != old_crtc_state->port_clock) in intel_pmdemand_needs_update()
H A Dintel_pmdemand.h56 enum pipe pipe, int port_clock);
H A Dg4x_dp.c79 if (pipe_config->port_clock == divisor[i].dot) { in g4x_dp_set_clock()
98 pipe_config->port_clock, in intel_dp_prepare()
201 pipe_config->port_clock); in ilk_edp_pll_on()
205 if (pipe_config->port_clock == 162000) in ilk_edp_pll_on()
393 pipe_config->port_clock = 162000; in intel_dp_get_config()
395 pipe_config->port_clock = 270000; in intel_dp_get_config()
399 intel_dotclock_calculate(pipe_config->port_clock, in intel_dp_get_config()
H A Dintel_dp_link_training.c733 intel_dp_compute_rate(intel_dp, crtc_state->port_clock, in intel_dp_prepare_link_train()
930 } else if (crtc_state->port_clock == 810000) { in intel_dp_training_pattern()
948 } else if (crtc_state->port_clock >= 540000) { in intel_dp_training_pattern()
1110 crtc_state->port_clock, crtc_state->lane_count); in intel_dp_link_train_phy()
1131 crtc_state->port_clock, in intel_dp_schedule_fallback_link_training()
1377 crtc_state->port_clock, crtc_state->lane_count); in intel_dp_128b132b_link_train()
H A Dintel_ddi.c264 int clock = crtc_state->port_clock; in icl_pll_to_ddi_clk_sel()
301 switch (port_clock) { in ddi_buf_phy_link_rate()
319 MISSING_CASE(port_clock); in ddi_buf_phy_link_rate()
1098 if (crtc_state->port_clock > 600000) in icl_combo_phy_loadgen_select()
1302 crtc_state->port_clock > 500000 ? in icl_mg_phy_set_signal_levels()
1309 crtc_state->port_clock > 500000 ? in icl_mg_phy_set_signal_levels()
2416 crtc_state->port_clock, in mtl_ddi_pre_enable_dp()
2522 crtc_state->port_clock, in tgl_ddi_pre_enable_dp()
2667 crtc_state->port_clock, in hsw_ddi_pre_enable_dp()
3587 crtc_state->port_clock > 594000) in intel_ddi_compute_min_voltage_level()
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H A Dintel_cx0_phy.c332 (crtc_state->port_clock == 540000 || in intel_c10_get_tx_vboost_lvl()
333 crtc_state->port_clock == 810000)) in intel_c10_get_tx_vboost_lvl()
346 (crtc_state->port_clock == 540000 || in intel_c10_get_tx_term_ctl()
347 crtc_state->port_clock == 810000)) in intel_c10_get_tx_term_ctl()
1797 if (crtc_state->port_clock == tables[i]->clock) { in intel_c10pll_calc_state()
2022 if (intel_c20_compute_hdmi_tmds_pll(crtc_state->port_clock, in intel_c20pll_calc_state()
2032 if (crtc_state->port_clock == tables[i]->link_bit_rate) { in intel_c20pll_calc_state()
2424 is_hdmi_frl(crtc_state->port_clock)) in intel_program_port_clock_ctl()
2431 if (crtc_state->port_clock == 1000000 || crtc_state->port_clock == 2000000) in intel_program_port_clock_ctl()
2746 crtc_state->port_clock); in intel_cx0pll_enable()
[all …]
H A Dintel_dpll_mgr.c1000 int clock = crtc_state->port_clock; in hsw_ddi_lcpll_compute_dpll()
1020 int clock = crtc_state->port_clock; in hsw_ddi_lcpll_get_dpll()
1716 ret = skl_ddi_calculate_wrpll(crtc_state->port_clock, in skl_ddi_hdmi_pll_dividers()
1751 switch (crtc_state->port_clock / 2) { in skl_ddi_dp_set_dpll_hw_state()
2156 if (crtc_state->port_clock == bxt_dp_clk_val[i].dot) { in bxt_ddi_dp_pll_dividers()
2165 clk_div->dot != crtc_state->port_clock); in bxt_ddi_dp_pll_dividers()
2173 int clock = crtc_state->port_clock; in bxt_ddi_set_dpll_hw_state()
2276 crtc_state->port_clock = bxt_ddi_pll_get_freq(i915, NULL, in bxt_ddi_hdmi_set_dpll_hw_state()
2565 int clock = crtc_state->port_clock; in icl_calc_dp_combo_pll()
2648 u32 afe_clock = crtc_state->port_clock * 5; in icl_calc_wrpll()
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H A Dintel_dp_mst.c56 int symbol_clock = crtc_state->port_clock / 32; in intel_dp_mst_check_constraints()
95 crtc_state->port_clock = limits->max_rate; in intel_dp_mst_find_vcpi_slots_for_bpp()
100 crtc_state->port_clock, in intel_dp_mst_find_vcpi_slots_for_bpp()
168 crtc_state->port_clock, in intel_dp_mst_compute_link_config()
262 crtc_state->port_clock, in intel_dp_dsc_mst_compute_link_config()
H A Dintel_dp.h84 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
H A Dintel_dpio_phy.c942 if (crtc_state->port_clock > 270000) in chv_phy_pre_encoder_enable()
944 else if (crtc_state->port_clock > 135000) in chv_phy_pre_encoder_enable()
946 else if (crtc_state->port_clock > 67500) in chv_phy_pre_encoder_enable()
948 else if (crtc_state->port_clock > 33750) in chv_phy_pre_encoder_enable()
H A Dvlv_dsi_pll.c203 config->port_clock = pclk; in vlv_dsi_pll_compute()
526 config->port_clock = pclk; in bxt_dsi_pll_compute()
H A Dintel_audio.c235 crtc_state->port_clock == hdmi_ncts_table[i].clock) { in audio_config_hdmi_get_n()
438 link_clk = crtc_state->port_clock; in calc_hblank_early_prog()
476 link_clk = crtc_state->port_clock; in calc_samples_room()
755 crtc_state->port_clock, in intel_audio_codec_enable()
H A Dintel_dp.c127 return crtc_state->port_clock >= 1000000; in intel_dp_is_uhbr()
1300 intel_dp_rate_select(intel_dp, port_clock); in intel_dp_compute_rate()
1302 *link_bw = drm_dp_link_rate_to_bw_code(port_clock); in intel_dp_compute_rate()
1513 pipe_config->port_clock = link_rate; in intel_dp_compute_link_config_wide()
1709 pipe_config->port_clock = limits->max_rate; in intel_dp_dsc_compute_config()
1731 pipe_config->port_clock, in intel_dp_dsc_compute_config()
1882 pipe_config->lane_count, pipe_config->port_clock, in intel_dp_compute_link_config()
1890 intel_dp_max_data_rate(pipe_config->port_clock, in intel_dp_compute_link_config()
1901 intel_dp_max_data_rate(pipe_config->port_clock, in intel_dp_compute_link_config()
2358 pipe_config->port_clock, in intel_dp_compute_config()
[all …]
H A Dg4x_hdmi.c190 dotclock = DIV_ROUND_CLOSEST(pipe_config->port_clock * 2, 3); in intel_hdmi_get_config()
192 dotclock = pipe_config->port_clock; in intel_hdmi_get_config()
H A Dintel_tv.c1128 tv_mode.clock = pipe_config->port_clock; in intel_tv_get_config()
1155 intel_tv_mode_to_mode(&mode, &tv_mode, pipe_config->port_clock); in intel_tv_get_config()
1221 pipe_config->port_clock = tv_mode->clock; in intel_tv_compute_config()
1229 intel_tv_mode_to_mode(adjusted_mode, tv_mode, pipe_config->port_clock); in intel_tv_compute_config()
H A Dintel_display.c3009 pipe_config->port_clock / pipe_config->pixel_multiplier; in i9xx_get_pipe_config()
3843 int port_clock; in i9xx_crtc_clock_get() local
3885 port_clock = pnv_calc_dpll_params(refclk, &clock); in i9xx_crtc_clock_get()
3887 port_clock = i9xx_calc_dpll_params(refclk, &clock); in i9xx_crtc_clock_get()
3916 port_clock = i9xx_calc_dpll_params(refclk, &clock); in i9xx_crtc_clock_get()
3924 pipe_config->port_clock = port_clock; in i9xx_crtc_clock_get()
3955 dotclock = DIV_ROUND_CLOSEST(pipe_config->port_clock * 24, in intel_crtc_dotclock()
3958 dotclock = pipe_config->port_clock; in intel_crtc_dotclock()
4719 crtc_state->port_clock = 0; in intel_modeset_pipe_config()
4750 if (!crtc_state->port_clock) in intel_modeset_pipe_config()
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H A Dintel_modeset_setup.c556 crtc_state->port_clock == 0; in has_bogus_dpll_config()
872 crtc_state->port_clock); in intel_modeset_readout_hw_state()
H A Dintel_crt.c147 pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock; in intel_crt_get_config()
457 pipe_config->port_clock = 135000 * 2; in hsw_crt_compute_config()
H A Dintel_crtc_state_dump.c319 pipe_config->port_clock, DRM_RECT_ARG(&pipe_config->pipe_src), in intel_crtc_state_dump()
H A Dintel_dvo.c178 pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock; in intel_dvo_get_config()
H A Dintel_snps_phy.c1793 if (intel_snps_phy_check_hdmi_link_rate(crtc_state->port_clock) in intel_mpllb_calc_state()
1801 crtc_state->port_clock); in intel_mpllb_calc_state()
1811 if (crtc_state->port_clock == tables[i]->clock) { in intel_mpllb_calc_state()
H A Dintel_lvds.c156 crtc_state->hw.adjusted_mode.crtc_clock = crtc_state->port_clock; in intel_lvds_get_config()
H A Dintel_cdclk.c2575 crtc_state->port_clock >= 540000 && in intel_crtc_compute_min_cdclk()
2602 min_cdclk = max(crtc_state->port_clock, min_cdclk); in intel_crtc_compute_min_cdclk()
2858 switch (crtc_state->port_clock / 2) { in skl_dpll0_vco()

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