drm/i915/tgl: s/TGL/TIGERLAKE for platform/subplatform defines

Follow consistent naming convention. Replace TGL with
TIGERLAKE.Replace IS_TGL_DISPLAY_STEP with
IS_TIGERLAKE() && IS_DISPLAY_STEP().

drm/i915/tgl: s/TGL/TIGERLAKE for platform/subplatform defines

Follow consistent naming convention. Replace TGL with
TIGERLAKE.Replace IS_TGL_DISPLAY_STEP with
IS_TIGERLAKE() && IS_DISPLAY_STEP().

v2:
- s/TGL/tgl in the subject prefix(Anusha)

v3:
- Unrolled wrapper IS_TGL_DISPLAY_STEP and Replace
- Replace IS_PLATFORM && DISPLAY_STEP (Jani/Tvrtko).

v4:
- Removed unused macros

Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230801135344.3797924-10-dnyaneshwar.bhadane@intel.com

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drm/i915/cml: s/CML/COMETLAKE for platform/subplatform defines

Follow consistent naming convention. Replace CML with
COMETLAKE.

Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
Re

drm/i915/cml: s/CML/COMETLAKE for platform/subplatform defines

Follow consistent naming convention. Replace CML with
COMETLAKE.

Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230801135344.3797924-7-dnyaneshwar.bhadane@intel.com

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drm/i915/cfl: s/CFL/COFFEELAKE for platform/subplatform defines

Follow consistent naming convention. Replace CFL with
COFFEELAKE.

Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>

drm/i915/cfl: s/CFL/COFFEELAKE for platform/subplatform defines

Follow consistent naming convention. Replace CFL with
COFFEELAKE.

Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230801135344.3797924-6-dnyaneshwar.bhadane@intel.com

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drm/i915/kbl: s/KBL/KABYLAKE for platform/subplatform defines

Follow consistent naming convention. Replace KBL with
KABYLAKE.Replace IS_KBL_GRAPHICS_STEP with
IS_KABYLAKE () && IS_GRAPHICS_STEP().

drm/i915/kbl: s/KBL/KABYLAKE for platform/subplatform defines

Follow consistent naming convention. Replace KBL with
KABYLAKE.Replace IS_KBL_GRAPHICS_STEP with
IS_KABYLAKE () && IS_GRAPHICS_STEP().

v2:
- s/KBL/kbl in the subject prefix(Anusha)

v3:
- Unrolled wrapper IS_KBL_GRAPHICS_STEP.
- Replace with IS_PLATFORM && DISPLAY_STEP(tvrtko/jani)

v4:
- Removed unused macro.

Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Anusha Srivatsa <Anusha.Srivatsa@intel.com>
Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230801135344.3797924-5-dnyaneshwar.bhadane@intel.com

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drm/i915/skl: s/SKL/SKYLAKE for platform/subplatform defines

Follow consistent naming convention. Replace SKL with
SKYLAKE and Replace IS_SKL_GRAPHICS_STEP with
IS_SKYLAKE() && IS_GRAPHICS_STEP().

drm/i915/skl: s/SKL/SKYLAKE for platform/subplatform defines

Follow consistent naming convention. Replace SKL with
SKYLAKE and Replace IS_SKL_GRAPHICS_STEP with
IS_SKYLAKE() && IS_GRAPHICS_STEP().

v2:
- Change subject skl instead of SKL(Anusha)

v3:
- Unrolled wrapper IS_SKL_GRAPHICS_STEP.
- Replace with IS_PLATFORM && DISPLAY_STEP(tvrtko/jani)

v4:
- Removed the unused macro.

Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230801135344.3797924-4-dnyaneshwar.bhadane@intel.com

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drm/i915/mtl: Add new vswing table for C20 phy to support DP 1.4

Add vswing table to support DP 1.4 for C20 phy.

v2: rename mtl_c10_trans
v3: add default_entry for mtl_c20_trans_dp14
v4: rename mtl

drm/i915/mtl: Add new vswing table for C20 phy to support DP 1.4

Add vswing table to support DP 1.4 for C20 phy.

v2: rename mtl_c10_trans
v3: add default_entry for mtl_c20_trans_dp14
v4: rename mtl_cx0_trans_dp14

Bspec: 74104
Signed-off-by: Lee Shawn C <shawn.c.lee@intel.com>
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Clint Taylor <Clinton.A.Taylor@intel.com>
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Cc: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230609002038.11516-1-shawn.c.lee@intel.com

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drm/i915/mtl: update DP 2.0 vswing table for C20 phy

Update preset 15 setting to align the latest bspec value.

Bspec: 74104
Signed-off-by: Lee Shawn C <shawn.c.lee@intel.com>
Cc: Mika Kahola <mika.

drm/i915/mtl: update DP 2.0 vswing table for C20 phy

Update preset 15 setting to align the latest bspec value.

Bspec: 74104
Signed-off-by: Lee Shawn C <shawn.c.lee@intel.com>
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Clint Taylor <Clinton.A.Taylor@intel.com>
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Cc: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230606104238.31953-1-shawn.c.lee@intel.com

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drm/i915/mtl: Add voltage swing sequence for C20

DP1.4 and DP20 voltage swing sequence for C20 phy.

Bspec: 65449, 67636, 67610

Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Signed-off-by: M

drm/i915/mtl: Add voltage swing sequence for C20

DP1.4 and DP20 voltage swing sequence for C20 phy.

Bspec: 65449, 67636, 67610

Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Clint Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230428095433.4109054-6-mika.kahola@intel.com

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drm/i915/mtl: Add vswing programming for C10 phys

C10 phys uses direct mapping internally for voltage and pre-emphasis levels.
Program the levels directly to the fields in the VDR Registers.

Bspec:

drm/i915/mtl: Add vswing programming for C10 phys

C10 phys uses direct mapping internally for voltage and pre-emphasis levels.
Program the levels directly to the fields in the VDR Registers.

Bspec: 65449

v2: From table "C10: Tx EQ settings for DP 1.4x" it shows level 1
and preemphasis 1 instead of two times of level 1 preemphasis 0.
Fix this in the driver code as well.
v3: VSwing update (Clint)
v4: Add vboost termination ctl programming(Imre)
Fix tx llogic and other nits
Restrict C10 vdr ctl register access for C10 phy(RK)
v5: Program vboots, termination ctl for both lanes(Imre)

Cc: Imre Deak <imre.deak@intel.com>
Cc: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Clint Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>(v3)
Link: https://patchwork.freedesktop.org/patch/msgid/20230413212443.1504245-5-radhakrishna.sripada@intel.com

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drm/i915/display/adlp: More updates to voltage swing table

Voltage swing table updated for eDP HBR3

Bspec: 49291
Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Rev

drm/i915/display/adlp: More updates to voltage swing table

Voltage swing table updated for eDP HBR3

Bspec: 49291
Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220602135719.1093081-1-balasubramani.vivekanandan@intel.com

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drm/i915/bios: Split VBT data into per-panel vs. global parts

Move the panel specific VBT parsing to happen during the
output probing stage. Needs to be done because the VBT
parsing will need to loo

drm/i915/bios: Split VBT data into per-panel vs. global parts

Move the panel specific VBT parsing to happen during the
output probing stage. Needs to be done because the VBT
parsing will need to look at the EDID to determine
the correct panel_type on some machines.

We split the parsed VBT data (i915->vbt) along the same
boundary. For the moment we just hoist all the panel
specific stuff into connector->panel.vbt since that seems
like the most convenient place for eg. the backlight code.

Note that we simply drop the drrs type check from
intel_drrs_frontbuffer_update() since that operates on the whole
device rather than a specific connector/encoder. But the check
was just a micro optimization so removing it doesn't actually
mattter for correctness.

TODO: Lot's of cleanup to be done in the future. Eg. most of
the DSI stuff could probably be eliminated entirely and just
parsed on demand during DSI init.

v2: Note the intel_drrs_frontbuffer_update() change

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220510104242.6099-13-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>

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drm/i915/display/adl_p: Updates to HDMI combo PHY voltage swing table

New updates to HDMI combo PHY voltage swing tables. Actually with this
update (bspec updated on 08/17/2021), the values are reve

drm/i915/display/adl_p: Updates to HDMI combo PHY voltage swing table

New updates to HDMI combo PHY voltage swing tables. Actually with this
update (bspec updated on 08/17/2021), the values are reverted back to be
same as icelake for HDMI combo PHY.

Bspec: 49291
Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220526064935.969225-1-balasubramani.vivekanandan@intel.com

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drm/i915: warn about missing ->get_buf_trans initialization

Make sure each DDI platform has sane ->get_buf_trans initialized.

Suggested-by: Matt Roper <matthew.d.roper@intel.com>
Cc: Matt Roper <ma

drm/i915: warn about missing ->get_buf_trans initialization

Make sure each DDI platform has sane ->get_buf_trans initialized.

Suggested-by: Matt Roper <matthew.d.roper@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220503082134.4128355-1-jani.nikula@intel.com

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drm/i915/display/adlp: More voltage swing table updates

A few more updates in the alderlake-P voltage swing tables.

eDP HBR3 table was the same as icelake one but now it has changes for
voltage 0 a

drm/i915/display/adlp: More voltage swing table updates

A few more updates in the alderlake-P voltage swing tables.

eDP HBR3 table was the same as icelake one but now it has changes for
voltage 0 and pre-emphasis 2 line.
And DP tables also had one line change in each.

Bspec: 49291
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220315205122.202701-1-jose.souza@intel.com

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drm/i915/display/adlp: Update eDP voltage swing table

Up to now alderlake-p was using the same eDP voltage swing table for
frequencies up to HBR2 as icelake but now it has its own table.

BSpec: 492

drm/i915/display/adlp: Update eDP voltage swing table

Up to now alderlake-p was using the same eDP voltage swing table for
frequencies up to HBR2 as icelake but now it has its own table.

BSpec: 49291
Cc: Clinton A Taylor <clinton.a.taylor@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220314152753.85081-1-jose.souza@intel.com

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drm/i915/tgl: Simply subplatform detection

In the past we had a need to differentiate TGL U and TGL Y, there
was a different voltage swing table for each subplatform and some PCI
ids of this subplat

drm/i915/tgl: Simply subplatform detection

In the past we had a need to differentiate TGL U and TGL Y, there
was a different voltage swing table for each subplatform and some PCI
ids of this subplatforms are shared but it turned out that it was a
specification mistake and the voltage swing table was indeed the same
but we went ahead with that patch because we needed to differentiate
TGL U and Y from TGL H and by that time TGL H was embargoed so that
was the perfect way to land it upstream.

Now the embargo for TGL H is long past and now we even have
INTEL_TGL_12_GT1_IDS with all TGL H ids, so we can drop this PCI root
check and only rely in the PCI ids to differentiate TGL U and Y from
TGL H that actually has code differences.

Besides the simplification this will fix issues in virtualization
environments where the PCI root is virtualized and don't have the same
id as actual hardware.

v2:
- add and set INTEL_SUBPLATFORM_UY

Cc: Fred Gao <fred.gao@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Tested-by: Yu He <yu.he@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220222141424.35165-1-jose.souza@intel.com

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drm/i915/display/ehl: Update voltage swing table

EHL table was recently updated with some minor fixes.

BSpec: 21257
Cc: stable@vger.kernel.org
Cc: Clint Taylor <clinton.a.taylor@intel.com>
Signed-o

drm/i915/display/ehl: Update voltage swing table

EHL table was recently updated with some minor fixes.

BSpec: 21257
Cc: stable@vger.kernel.org
Cc: Clint Taylor <clinton.a.taylor@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220113160437.49059-1-jose.souza@intel.com
(cherry picked from commit 5ec7baef52c367cdbda964aa662f7135c25bab1f)
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

show more ...

drm/i915/display/ehl: Update voltage swing table

EHL table was recently updated with some minor fixes.

BSpec: 21257
Cc: stable@vger.kernel.org
Cc: Clint Taylor <clinton.a.taylor@intel.com>
Signed-o

drm/i915/display/ehl: Update voltage swing table

EHL table was recently updated with some minor fixes.

BSpec: 21257
Cc: stable@vger.kernel.org
Cc: Clint Taylor <clinton.a.taylor@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220113160437.49059-1-jose.souza@intel.com

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drm/i915/snps: vswing value refined for SNPS phys

Updated new values from BSPEC.

Bspec: 53920
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Imre Deak

drm/i915/snps: vswing value refined for SNPS phys

Updated new values from BSPEC.

Bspec: 53920
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220110234520.6836-1-clinton.a.taylor@intel.com

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drm/i915/ddi: add use_edp_hobl() and use_edp_low_vswing() helpers

Localize HOBL and low vswing VBT lookups to a couple of small helpers,
and get rid of a bunch of local variables.

Signed-off-by: Ja

drm/i915/ddi: add use_edp_hobl() and use_edp_low_vswing() helpers

Localize HOBL and low vswing VBT lookups to a couple of small helpers,
and get rid of a bunch of local variables.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211203131318.2885969-1-jani.nikula@intel.com

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drm/i915/dg2: fix snps buf trans for uhbr

The UHBR check was using > instead of >=. Use the helper instead to
avoid mistakes. Also always use the non-UHBR values for HDMI.

v2: Use intel_crtc_has_dp

drm/i915/dg2: fix snps buf trans for uhbr

The UHBR check was using > instead of >=. Use the helper instead to
avoid mistakes. Also always use the non-UHBR values for HDMI.

v2: Use intel_crtc_has_dp_encoder() && intel_dp_is_uhbr() (Ville)

Fixes: 2817efaeb608 ("drm/i915/dg2: add SNPS PHY translations for UHBR link rates")
Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211007124201.18686-1-jani.nikula@intel.com

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drm/i915: Nuke intel_ddi_hdmi_num_entries()

Since intel_ddi_level() now looks at the buf_trans table there's
no point in having intel_ddi_hdmi_num_entries() around. Just
roll the necessary bits of l

drm/i915: Nuke intel_ddi_hdmi_num_entries()

Since intel_ddi_level() now looks at the buf_trans table there's
no point in having intel_ddi_hdmi_num_entries() around. Just
roll the necessary bits of locic into
intel_ddi_hdmi_level()/intel_ddi_level().

Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211001130107.1746-8-ville.syrjala@linux.intel.com

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drm/i915: s/ddi_translations/trans/

"ddi_translations" is a bit too long, let's shorten it to just "trans".

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.free

drm/i915: s/ddi_translations/trans/

"ddi_translations" is a bit too long, let's shorten it to just "trans".

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210927182455.27119-2-ville.syrjala@linux.intel.com
Reviewed-by: Imre Deak <imre.deak@intel.com>

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drm/i915/dg2: add SNPS PHY translations for UHBR link rates

UHBR link rates use different tx equalization settings. Using this will
require changes in the link training code too.

Bspec: 53920
Cc: M

drm/i915/dg2: add SNPS PHY translations for UHBR link rates

UHBR link rates use different tx equalization settings. Using this will
require changes in the link training code too.

Bspec: 53920
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210813115151.19290-3-jani.nikula@intel.com

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drm/i915/dg2: use existing mechanisms for SNPS PHY translations

We use encoder->get_buf_trans() in many places, for example
intel_ddi_dp_voltage_max(), and the hook was set to some old platform's
fu

drm/i915/dg2: use existing mechanisms for SNPS PHY translations

We use encoder->get_buf_trans() in many places, for example
intel_ddi_dp_voltage_max(), and the hook was set to some old platform's
function for DG2 SNPS PHY. Convert SNPS PHY to use the same translation
mechanisms as everything else.

Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210813115151.19290-2-jani.nikula@intel.com

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