Lines Matching refs:port_clock
970 hsw_ddi_calculate_wrpll(crtc_state->port_clock * 1000, &r2, &n2, &p); in hsw_ddi_wrpll_compute_dpll()
977 crtc_state->port_clock = hsw_ddi_wrpll_get_freq(i915, NULL, in hsw_ddi_wrpll_compute_dpll()
1000 int clock = crtc_state->port_clock; in hsw_ddi_lcpll_compute_dpll()
1020 int clock = crtc_state->port_clock; in hsw_ddi_lcpll_get_dpll()
1076 if (drm_WARN_ON(crtc->base.dev, crtc_state->port_clock / 2 != 135000)) in hsw_ddi_spll_compute_dpll()
1716 ret = skl_ddi_calculate_wrpll(crtc_state->port_clock * 1000, in skl_ddi_hdmi_pll_dividers()
1735 crtc_state->port_clock = skl_ddi_wrpll_get_freq(i915, NULL, in skl_ddi_hdmi_pll_dividers()
1751 switch (crtc_state->port_clock / 2) { in skl_ddi_dp_set_dpll_hw_state()
2156 if (crtc_state->port_clock == bxt_dp_clk_val[i].dot) { in bxt_ddi_dp_pll_dividers()
2165 clk_div->dot != crtc_state->port_clock); in bxt_ddi_dp_pll_dividers()
2173 int clock = crtc_state->port_clock; in bxt_ddi_set_dpll_hw_state()
2276 crtc_state->port_clock = bxt_ddi_pll_get_freq(i915, NULL, in bxt_ddi_hdmi_set_dpll_hw_state()
2565 int clock = crtc_state->port_clock; in icl_calc_dp_combo_pll()
2648 u32 afe_clock = crtc_state->port_clock * 5; in icl_calc_wrpll()
2858 int clock = crtc_state->port_clock; in icl_calc_mg_pll_state()
3192 crtc_state->port_clock = icl_ddi_combo_pll_get_freq(dev_priv, NULL, in icl_compute_combo_phy_dpll()
3284 crtc_state->port_clock = icl_ddi_mg_pll_get_freq(dev_priv, NULL, in icl_compute_tc_phy_dplls()