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/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dsnps,dw-apb-ssi.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/spi/snps,dw-apb-ssi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Brown <broonie@kernel.org>
13 - $ref: spi-controller.yaml#
14 - if:
19 - mscc,ocelot-spi
20 - mscc,jaguar2-spi
25 - if:
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/openbmc/linux/drivers/spi/
H A Dspi-dw-bt1.c1 // SPDX-License-Identifier: GPL-2.0-only
9 // Baikal-T1 DW APB SPI and System Boot SPI driver
24 #include <linux/spi/spi-mem.h>
27 #include "spi-dw.h"
52 struct dw_spi_bt1 *dwsbt1 = to_dw_spi_bt1(desc->mem->spi->controller); in dw_spi_bt1_dirmap_create()
54 if (!dwsbt1->map || in dw_spi_bt1_dirmap_create()
55 !dwsbt1->dws.mem_ops.supports_op(desc->mem, &desc->info.op_tmpl)) in dw_spi_bt1_dirmap_create()
56 return -EOPNOTSUPP; in dw_spi_bt1_dirmap_create()
60 * mapped flash memory bounds and the operation is read-only. in dw_spi_bt1_dirmap_create()
62 if (desc->info.offset + desc->info.length > dwsbt1->map_len || in dw_spi_bt1_dirmap_create()
[all …]
H A Dspi-dw.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 #include <linux/spi/spi-mem.h>
14 /* Synopsys DW SSI IP-core virtual IDs */
18 /* Synopsys DW SSI component versions (FourCC sequence) */
21 /* DW SSI IP-core ID and version check helpers */
23 ((_dws)->ip == DW_ ## _ip ## _ID)
26 (dw_spi_ip_is(_dws, _ip) && (_dws)->ver _op DW_ ## _ip ## _ ## _ver)
32 /* DW SPI controller capabilities */
36 /* Register offsets (Generic for both DWC APB SSI and DWC SSI IP-cores) */
65 /* Bit fields in CTRLR0 (DWC APB SSI) */
[all …]
H A Dspi-dw-mmio.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Memory-mapped interface driver for DW SPI Core
24 #include "spi-dw.h"
57 * Elba SoC does not use ssi, pin override is used for cs 0,1 and
61 * bit: |---3-------2-------1-------0
79 struct dw_spi *dws = spi_controller_get_devdata(spi->controller); in dw_spi_mscc_set_cs()
81 struct dw_spi_mscc *dwsmscc = dwsmmio->priv; in dw_spi_mscc_set_cs()
90 writel(sw_mode, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE); in dw_spi_mscc_set_cs()
102 dwsmscc = devm_kzalloc(&pdev->dev, sizeof(*dwsmscc), GFP_KERNEL); in dw_spi_mscc_init()
104 return -ENOMEM; in dw_spi_mscc_init()
[all …]
H A Dspi-dw-dma.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Special handling for DW DMA core
9 #include <linux/dma-mapping.h>
15 #include <linux/platform_data/dma-dw.h>
19 #include "spi-dw.h"
30 if (s->dma_dev != chan->device->dev) in dw_spi_dma_chan_filter()
33 chan->private = s; in dw_spi_dma_chan_filter()
43 def_burst = dws->fifo_len / 2; in dw_spi_dma_maxburst_init()
45 ret = dma_get_slave_caps(dws->rxchan, &caps); in dw_spi_dma_maxburst_init()
51 dws->rxburst = min(max_burst, def_burst); in dw_spi_dma_maxburst_init()
[all …]
H A Dspi-dw-core.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/dma-mapping.h>
17 #include <linux/spi/spi-mem.h>
21 #include "spi-dw.h"
64 snprintf(name, 32, "dw_spi%d", dws->host->bus_num); in dw_spi_debugfs_init()
65 dws->debugfs = debugfs_create_dir(name, NULL); in dw_spi_debugfs_init()
67 dws->regset.regs = dw_spi_dbgfs_regs; in dw_spi_debugfs_init()
68 dws->regset.nregs = ARRAY_SIZE(dw_spi_dbgfs_regs); in dw_spi_debugfs_init()
69 dws->regset.base = dws->regs; in dw_spi_debugfs_init()
70 debugfs_create_regset32("registers", 0400, dws->debugfs, &dws->regset); in dw_spi_debugfs_init()
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
13 dynamic device discovery; some are even write-only or read-only.
17 chips, analog to digital (and d-to-a) converters, and more.
23 (half duplex), SSP, SSI, and PSP. This driver framework should
44 If your system has an master-capable SPI controller (which
56 by providing a high-level interface to send memory-like commands.
145 supports spi-mem interface.
224 this code to manage the per-word or per-transfer accesses to the
254 Flash over 1/2/4-bit wide bus. Enable this option if you have a
266 Flash over up to 8-bit wide bus. Enable this option if you have a
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/openbmc/u-boot/arch/arm/dts/
H A Dsocfpga_stratix10.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
11 compatible = "altr,socfpga-stratix10";
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "arm,cortex-a53", "arm,armv8";
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H A Dsocfpga.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/reset/altr,rst-mgr.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
22 #address-cells = <1>;
23 #size-cells = <0>;
24 enable-method = "altr,socfpga-smp";
27 compatible = "arm,cortex-a9";
30 next-level-cache = <&L2>;
33 compatible = "arm,cortex-a9";
[all …]
H A Dsocfpga_arria10.dtsi17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
21 #address-cells = <1>;
22 #size-cells = <1>;
25 tick-timer = &timer2;
26 u-boot,dm-pre-reloc;
30 #address-cells = <1>;
31 #size-cells = <0>;
32 enable-method = "altr,socfpga-a10-smp";
35 compatible = "arm,cortex-a9";
[all …]
/openbmc/linux/arch/arm/boot/dts/synaptics/
H A Dberlin2cd.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Device Tree Include file for Marvell Armada 1500-mini (Berlin BG2CD) SoC
11 #include <dt-bindings/clock/berlin2.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 model = "Marvell Armada 1500-mini (BG2CD) SoC";
17 #address-cells = <1>;
18 #size-cells = <1>;
26 #address-cells = <1>;
27 #size-cells = <0>;
30 compatible = "arm,cortex-a9";
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/openbmc/linux/arch/arm64/boot/dts/intel/
H A Dsocfpga_agilex5.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/clock/intel,agilex5-clkmgr.h>
14 compatible = "intel,socfpga-agilex5";
15 #address-cells = <2>;
16 #size-cells = <2>;
[all …]
H A Dsocfpga_agilex.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/agilex-clock.h>
13 compatible = "intel,socfpga-agilex";
14 #address-cells = <2>;
15 #size-cells = <2>;
17 reserved-memory {
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/openbmc/linux/arch/arm64/boot/dts/altera/
H A Dsocfpga_stratix10.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/stratix10-clock.h>
12 compatible = "altr,socfpga-stratix10";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
[all …]
/openbmc/u-boot/arch/arc/dts/
H A Daxs10x_mb.dtsi1 // SPDX-License-Identifier: GPL-2.0+
12 compatible = "simple-bus";
13 #address-cells = <1>;
14 #size-cells = <1>;
16 u-boot,dm-pre-reloc;
19 compatible = "simple-bus";
20 u-boot,dm-pre-reloc;
23 compatible = "fixed-clock";
24 clock-frequency = <50000000>;
25 #clock-cells = <0>;
[all …]
H A Dhsdk.dts1 // SPDX-License-Identifier: GPL-2.0+
5 /dts-v1/;
8 #include "dt-bindings/clock/snps,hsdk-cgu.h"
13 #address-cells = <1>;
14 #size-cells = <1>;
23 #clock-cells = <0>;
24 compatible = "fixed-clock";
25 clock-frequency = <500000000>;
26 u-boot,dm-pre-reloc;
30 clk-fmeas {
[all …]
/openbmc/linux/arch/arm/boot/dts/intel/socfpga/
H A Dsocfpga_arria10.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 enable-method = "altr,socfpga-a10-smp";
19 compatible = "arm,cortex-a9";
22 next-level-cache = <&L2>;
[all …]
H A Dsocfpga.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/reset/altr,rst-mgr.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
22 #address-cells = <1>;
23 #size-cells = <0>;
24 enable-method = "altr,socfpga-smp";
27 compatible = "arm,cortex-a9";
30 next-level-cache = <&L2>;
33 compatible = "arm,cortex-a9";
[all …]
/openbmc/linux/arch/riscv/boot/dts/canaan/
H A Dk210.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
6 #include <dt-bindings/clock/k210-clk.h>
7 #include <dt-bindings/pinctrl/k210-fpioa.h>
8 #include <dt-bindings/reset/k210-rst.h>
12 * Although the K210 is a 64-bit CPU, the address bus is only 32-bits
15 #address-cells = <1>;
16 #size-cells = <1>;
17 compatible = "canaan,kendryte-k210";
28 * Since this is a non-ratified draft specification, the kernel does not
[all …]
/openbmc/linux/arch/arc/boot/dts/
H A Dhsdk.dts1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/reset/snps,hsdk-reset.h>
18 #address-cells = <2>;
19 #size-cells = <2>;
22 … "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
30 #address-cells = <1>;
31 #size-cells = <0>;
62 input_clk: input-clk {
[all …]
/openbmc/u-boot/arch/mips/dts/
H A Dmscc,jr2.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #address-cells = <1>;
8 #size-cells = <1>;
12 #address-cells = <1>;
13 #size-cells = <0>;
27 cpuintc: interrupt-controller@0 {
28 #address-cells = <0>;
29 #interrupt-cells = <1>;
30 interrupt-controller;
31 compatible = "mti,cpu-interrupt-controller";
[all …]
H A Dmscc,ocelot.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #address-cells = <1>;
8 #size-cells = <1>;
12 #address-cells = <1>;
13 #size-cells = <0>;
27 cpuintc: interrupt-controller@0 {
28 #address-cells = <0>;
29 #interrupt-cells = <1>;
30 interrupt-controller;
31 compatible = "mti,cpu-interrupt-controller";
[all …]
/openbmc/linux/arch/mips/boot/dts/mscc/
H A Docelot.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 #address-cells = <1>;
6 #size-cells = <1>;
10 #address-cells = <1>;
11 #size-cells = <0>;
25 cpuintc: interrupt-controller {
26 #address-cells = <0>;
27 #interrupt-cells = <1>;
28 interrupt-controller;
29 compatible = "mti,cpu-interrupt-controller";
[all …]
/openbmc/u-boot/drivers/spi/
H A Ddesignware_spi.c1 // SPDX-License-Identifier: GPL-2.0
8 * drivers/spi/spi-dw.c, which is:
13 #include <asm-generic/gpio.h>
91 s32 frequency; /* Default clock frequency, -1 for none */
102 struct gpio_desc cs_gpio; /* External chip-select gpio */
121 return __raw_readl(priv->regs + offset); in dw_read()
126 __raw_writel(val, priv->regs + offset); in dw_write()
136 ret = gpio_request_by_name(bus, "cs-gpio", 0, &priv->cs_gpio, 0); in request_gpio_cs()
137 if (ret == -ENOENT) in request_gpio_cs()
141 printf("Error: %d: Can't get %s gpio!\n", ret, bus->name); in request_gpio_cs()
[all …]
/openbmc/linux/
H A DMAINTAINERS5 ----------
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