1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2018 Microsemi Corporation 4 */ 5 6/ { 7 #address-cells = <1>; 8 #size-cells = <1>; 9 compatible = "mscc,jr2"; 10 11 cpus { 12 #address-cells = <1>; 13 #size-cells = <0>; 14 15 cpu@0 { 16 compatible = "mips,mips24KEc"; 17 device_type = "cpu"; 18 clocks = <&cpu_clk>; 19 reg = <0>; 20 }; 21 }; 22 23 aliases { 24 serial0 = &uart0; 25 }; 26 27 cpuintc: interrupt-controller@0 { 28 #address-cells = <0>; 29 #interrupt-cells = <1>; 30 interrupt-controller; 31 compatible = "mti,cpu-interrupt-controller"; 32 }; 33 34 cpu_clk: cpu-clock { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 clock-frequency = <500000000>; 38 }; 39 40 ahb_clk: ahb-clk { 41 compatible = "fixed-clock"; 42 #clock-cells = <0>; 43 clock-frequency = <250000000>; 44 }; 45 46 ahb { 47 compatible = "simple-bus"; 48 #address-cells = <1>; 49 #size-cells = <1>; 50 ranges = <0 0x70000000 0x2000000>; 51 52 interrupt-parent = <&intc>; 53 54 cpu_ctrl: syscon@0 { 55 compatible = "mscc,jr2-cpu-syscon", "syscon"; 56 reg = <0x0 0x2c>; 57 }; 58 59 intc: interrupt-controller@70 { 60 compatible = "mscc,jr2-icpu-intr"; 61 reg = <0x70 0x94>; 62 #interrupt-cells = <1>; 63 interrupt-controller; 64 interrupt-parent = <&cpuintc>; 65 interrupts = <2>; 66 }; 67 68 uart0: serial@100000 { 69 pinctrl-0 = <&uart_pins>; 70 pinctrl-names = "default"; 71 compatible = "ns16550a"; 72 reg = <0x100000 0x20>; 73 interrupts = <6>; 74 clocks = <&ahb_clk>; 75 reg-io-width = <4>; 76 reg-shift = <2>; 77 78 status = "disabled"; 79 }; 80 81 uart2: serial@100800 { 82 pinctrl-0 = <&uart2_pins>; 83 pinctrl-names = "default"; 84 compatible = "ns16550a"; 85 reg = <0x100800 0x20>; 86 interrupts = <7>; 87 clocks = <&ahb_clk>; 88 reg-io-width = <4>; 89 reg-shift = <2>; 90 91 status = "disabled"; 92 }; 93 94 spi0: spi-master@101000 { 95 #address-cells = <1>; 96 #size-cells = <0>; 97 compatible = "snps,dw-apb-ssi"; 98 reg = <0x101000 0x40>; 99 num-chipselect = <4>; 100 bus-num = <0>; 101 reg-io-width = <4>; 102 reg-shift = <2>; 103 spi-max-frequency = <18000000>; /* input clock */ 104 clocks = <&ahb_clk>; 105 106 status = "disabled"; 107 }; 108 109 reset@1010008 { 110 compatible = "mscc,jr2-chip-reset"; 111 reg = <0x1010008 0x4>; 112 }; 113 114 gpio: pinctrl@1070034 { 115 compatible = "mscc,jaguar2-pinctrl"; 116 reg = <0x1010038 0x90>; 117 gpio-controller; 118 #gpio-cells = <2>; 119 gpio-ranges = <&gpio 0 0 64>; 120 121 sgpio_pins: sgpio-pins { 122 pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3"; 123 function = "sg0"; 124 }; 125 126 sgpio1_pins: sgpio1-pins { 127 pins = "GPIO_4", "GPIO_5", "GPIO_12", "GPIO_13"; 128 function = "sg1"; 129 }; 130 131 sgpio2_pins: sgpio2-pins { 132 pins = "GPIO_30", "GPIO_31", 133 "GPIO_32", "GPIO_33"; 134 function = "sg2"; 135 }; 136 137 uart_pins: uart-pins { 138 pins = "GPIO_10", "GPIO_11"; 139 function = "uart"; 140 }; 141 142 uart2_pins: uart2-pins { 143 pins = "GPIO_24", "GPIO_25"; 144 function = "uart2"; 145 }; 146 }; 147 148 sgpio: gpio@1010150 { 149 compatible = "mscc,ocelot-sgpio"; 150 status = "disabled"; 151 pinctrl-0 = <&sgpio_pins>; 152 pinctrl-names = "default"; 153 reg = <0x1010150 0x100>; 154 gpio-controller; 155 #gpio-cells = <2>; 156 gpio-ranges = <&sgpio 0 0 64>; 157 gpio-bank-name = "sgpio0_"; 158 sgpio-clock = <0x14>; 159 }; 160 161 sgpio1: gpio@101025c { 162 compatible = "mscc,ocelot-sgpio"; 163 status = "disabled"; 164 pinctrl-0 = <&sgpio1_pins>; 165 pinctrl-names = "default"; 166 reg = <0x101025c 0x100>; 167 gpio-controller; 168 #gpio-cells = <2>; 169 gpio-ranges = <&sgpio1 0 0 64>; 170 gpio-bank-name = "sgpio1_"; 171 sgpio-clock = <0x14>; 172 }; 173 174 sgpio2: gpio@1010368 { 175 compatible = "mscc,ocelot-sgpio"; 176 status = "disabled"; 177 pinctrl-0 = <&sgpio2_pins>; 178 pinctrl-names = "default"; 179 reg = <0x1010368 0x100>; 180 gpio-controller; 181 #gpio-cells = <2>; 182 gpio-ranges = <&sgpio2 0 0 64>; 183 gpio-bank-name = "sgpio2_"; 184 sgpio-clock = <0x14>; 185 }; 186 }; 187}; 188