mips/dts/mscc%2Cocelot.dtsi

1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 	#address-cells = <1>;
8 	#size-cells = <1>;
12 		#address-cells = <1>;
13 		#size-cells = <0>;
27 	cpuintc: interrupt-controller@0 {
28 		#address-cells = <0>;
29 		#interrupt-cells = <1>;
30 		interrupt-controller;
31 		compatible = "mti,cpu-interrupt-controller";
34 	cpu_clk: cpu-clock {
35 		compatible = "fixed-clock";
36 		#clock-cells = <0>;
37 		clock-frequency = <500000000>;
40 	sys_clk: sys-clk {
41 		compatible = "fixed-clock";
42 		#clock-cells = <0>;
43 		clock-frequency = <250000000>;
46 	ahb_clk: ahb-clk {
47 		compatible = "fixed-clock";
48 		#clock-cells = <0>;
49 		clock-frequency = <250000000>;
53 		compatible = "simple-bus";
54 		#address-cells = <1>;
55 		#size-cells = <1>;
58 		interrupt-parent = <&intc>;
61 			compatible = "mscc,ocelot-cpu-syscon", "syscon";
65 		intc: interrupt-controller@70 {
66 			compatible = "mscc,ocelot-icpu-intr";
68 			#interrupt-cells = <1>;
69 			interrupt-controller;
70 			interrupt-parent = <&cpuintc>;
75 			pinctrl-0 = <&uart_pins>;
76 			pinctrl-names = "default";
81 			reg-io-width = <4>;
82 			reg-shift = <2>;
88 			pinctrl-0 = <&uart2_pins>;
89 			pinctrl-names = "default";
94 			reg-io-width = <4>;
95 			reg-shift = <2>;
100 		spi0: spi-master@101000 {
101 			#address-cells = <1>;
102 			#size-cells = <0>;
103 			compatible = "snps,dw-apb-ssi";
105 			num-chipselect = <4>;
106 			bus-num = <0>;
107 			reg-io-width = <4>;
108 			reg-shift = <2>;
109 			spi-max-frequency = <18000000>; /* input clock */
116 			pinctrl-0 = <&miim1_pins>;
117 			pinctrl-names = "default";
119 			compatible = "mscc,vsc7514-switch";
137 			reg-names = "sys", "rew", "qs", "hsio", "port0",
142 			interrupt-names = "xtr", "inj";
145 			ethernet-ports {
146 				#address-cells = <1>;
147 				#size-cells = <0>;
186 			#address-cells = <1>;
187 			#size-cells = <0>;
188 			compatible = "mscc,ocelot-miim";
193 			phy0: ethernet-phy@0 {
196 			phy1: ethernet-phy@1 {
199 			phy2: ethernet-phy@2 {
202 			phy3: ethernet-phy@3 {
208 			compatible = "mscc,ocelot-chip-reset";
213 			compatible = "mscc,ocelot-pinctrl";
215 			gpio-controller;
216 			#gpio-cells = <2>;
217 			gpio-ranges = <&gpio 0 0 22>;
219 			sgpio_pins: sgpio-pins {
224 			uart_pins: uart-pins {
229 			uart2_pins: uart2-pins {
234 			spi_cs1_pin: spi-cs1-pin {
239 			miim1_pins: miim1-pins {
244 			spi_cs2_pin: spi-cs2-pin {
249 			spi_cs3_pin: spi-cs3-pin {
254 			spi_cs4_pin: spi-cs4-pin {
261 			compatible = "mscc,ocelot-sgpio";
264 			pinctrl-0 = <&sgpio_pins>;
265 			pinctrl-names = "default";
267 			gpio-controller;
268 			#gpio-cells = <2>;
269 			gpio-ranges = <&sgpio 0 0 64>;