183d290c5STom Rini// SPDX-License-Identifier: GPL-2.0+ 20c77092eSVlad Zakharov/* 30c77092eSVlad Zakharov * Copyright (C) 2017 Synopsys, Inc. All rights reserved. 40c77092eSVlad Zakharov */ 50c77092eSVlad Zakharov 60c77092eSVlad Zakharov/ { 7*cdfe6913SEugeniy Paltsev aliases { 8*cdfe6913SEugeniy Paltsev spi0 = &spi0; 9*cdfe6913SEugeniy Paltsev }; 10*cdfe6913SEugeniy Paltsev 110c77092eSVlad Zakharov axs10x_mb@e0000000 { 120c77092eSVlad Zakharov compatible = "simple-bus"; 130c77092eSVlad Zakharov #address-cells = <1>; 140c77092eSVlad Zakharov #size-cells = <1>; 150c77092eSVlad Zakharov ranges = <0x00000000 0xe0000000 0x10000000>; 160c77092eSVlad Zakharov u-boot,dm-pre-reloc; 170c77092eSVlad Zakharov 180c77092eSVlad Zakharov clocks { 190c77092eSVlad Zakharov compatible = "simple-bus"; 200c77092eSVlad Zakharov u-boot,dm-pre-reloc; 210c77092eSVlad Zakharov 220c77092eSVlad Zakharov apbclk: apbclk { 230c77092eSVlad Zakharov compatible = "fixed-clock"; 240c77092eSVlad Zakharov clock-frequency = <50000000>; 250c77092eSVlad Zakharov #clock-cells = <0>; 260c77092eSVlad Zakharov }; 270c77092eSVlad Zakharov 280c77092eSVlad Zakharov uartclk: uartclk { 290c77092eSVlad Zakharov compatible = "fixed-clock"; 300c77092eSVlad Zakharov clock-frequency = <33333333>; 310c77092eSVlad Zakharov #clock-cells = <0>; 320c77092eSVlad Zakharov u-boot,dm-pre-reloc; 330c77092eSVlad Zakharov }; 340c77092eSVlad Zakharov }; 350c77092eSVlad Zakharov 360c77092eSVlad Zakharov ethernet@18000 { 370c77092eSVlad Zakharov compatible = "altr,socfpga-stmmac"; 380c77092eSVlad Zakharov reg = < 0x18000 0x2000 >; 390c77092eSVlad Zakharov phy-mode = "gmii"; 400c77092eSVlad Zakharov snps,pbl = < 32 >; 410c77092eSVlad Zakharov clocks = <&apbclk>; 420c77092eSVlad Zakharov clock-names = "stmmaceth"; 430c77092eSVlad Zakharov max-speed = <100>; 440c77092eSVlad Zakharov }; 450c77092eSVlad Zakharov 460c77092eSVlad Zakharov ehci@0x40000 { 470c77092eSVlad Zakharov compatible = "generic-ehci"; 480c77092eSVlad Zakharov reg = < 0x40000 0x100 >; 490c77092eSVlad Zakharov }; 500c77092eSVlad Zakharov 510c77092eSVlad Zakharov ohci@0x60000 { 520c77092eSVlad Zakharov compatible = "generic-ohci"; 530c77092eSVlad Zakharov reg = < 0x60000 0x100 >; 540c77092eSVlad Zakharov }; 550c77092eSVlad Zakharov 560c77092eSVlad Zakharov uart0: serial0@22000 { 570c77092eSVlad Zakharov compatible = "snps,dw-apb-uart"; 580c77092eSVlad Zakharov reg = <0x22000 0x100>; 590c77092eSVlad Zakharov clocks = <&uartclk>; 600c77092eSVlad Zakharov reg-shift = <2>; 610c77092eSVlad Zakharov reg-io-width = <4>; 620c77092eSVlad Zakharov }; 63*cdfe6913SEugeniy Paltsev 64*cdfe6913SEugeniy Paltsev spi0: spi@0 { 65*cdfe6913SEugeniy Paltsev compatible = "snps,dw-apb-ssi"; 66*cdfe6913SEugeniy Paltsev reg = <0x0 0x100>; 67*cdfe6913SEugeniy Paltsev #address-cells = <1>; 68*cdfe6913SEugeniy Paltsev #size-cells = <0>; 69*cdfe6913SEugeniy Paltsev spi-max-frequency = <4000000>; 70*cdfe6913SEugeniy Paltsev clocks = <&apbclk>; 71*cdfe6913SEugeniy Paltsev clock-names = "spi_clk"; 72*cdfe6913SEugeniy Paltsev cs-gpio = <&cs_gpio 0>; 73*cdfe6913SEugeniy Paltsev spi_flash@0 { 74*cdfe6913SEugeniy Paltsev compatible = "spi-flash"; 75*cdfe6913SEugeniy Paltsev reg = <0>; 76*cdfe6913SEugeniy Paltsev spi-max-frequency = <4000000>; 77*cdfe6913SEugeniy Paltsev }; 78*cdfe6913SEugeniy Paltsev }; 79*cdfe6913SEugeniy Paltsev 80*cdfe6913SEugeniy Paltsev cs_gpio: gpio@11218 { 81*cdfe6913SEugeniy Paltsev compatible = "snps,creg-gpio"; 82*cdfe6913SEugeniy Paltsev reg = <0x11218 0x4>; 83*cdfe6913SEugeniy Paltsev gpio-controller; 84*cdfe6913SEugeniy Paltsev #gpio-cells = <1>; 85*cdfe6913SEugeniy Paltsev gpio-bank-name = "axs-spi-cs"; 86*cdfe6913SEugeniy Paltsev gpio-count = <1>; 87*cdfe6913SEugeniy Paltsev gpio-first-shift = <0>; 88*cdfe6913SEugeniy Paltsev gpio-bit-per-line = <2>; 89*cdfe6913SEugeniy Paltsev gpio-activate-val = <1>; 90*cdfe6913SEugeniy Paltsev gpio-deactivate-val = <3>; 91*cdfe6913SEugeniy Paltsev gpio-default-val = <1>; 92*cdfe6913SEugeniy Paltsev }; 930c77092eSVlad Zakharov }; 940c77092eSVlad Zakharov}; 95