Lines Matching +full:dw +full:- +full:apb +full:- +full:ssi
1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
6 #include <dt-bindings/clock/k210-clk.h>
7 #include <dt-bindings/pinctrl/k210-fpioa.h>
8 #include <dt-bindings/reset/k210-rst.h>
12 * Although the K210 is a 64-bit CPU, the address bus is only 32-bits
15 #address-cells = <1>;
16 #size-cells = <1>;
17 compatible = "canaan,kendryte-k210";
28 * Since this is a non-ratified draft specification, the kernel does not
33 #address-cells = <1>;
34 #size-cells = <0>;
35 timebase-frequency = <7800000>;
41 mmu-type = "riscv,none";
42 i-cache-block-size = <64>;
43 i-cache-size = <0x8000>;
44 d-cache-block-size = <64>;
45 d-cache-size = <0x8000>;
46 cpu0_intc: interrupt-controller {
47 #interrupt-cells = <1>;
48 interrupt-controller;
49 compatible = "riscv,cpu-intc";
57 mmu-type = "riscv,none";
58 i-cache-block-size = <64>;
59 i-cache-size = <0x8000>;
60 d-cache-block-size = <64>;
61 d-cache-size = <0x8000>;
62 cpu1_intc: interrupt-controller {
63 #interrupt-cells = <1>;
64 interrupt-controller;
65 compatible = "riscv,cpu-intc";
69 cpu-map {
89 sram_controller: memory-controller {
90 compatible = "canaan,k210-sram";
94 clock-names = "sram0", "sram1", "aisram";
99 compatible = "fixed-clock";
100 #clock-cells = <0>;
101 clock-frequency = <26000000>;
106 #address-cells = <1>;
107 #size-cells = <1>;
108 compatible = "simple-bus";
110 interrupt-parent = <&plic0>;
114 read-only;
118 compatible = "canaan,k210-clint", "sifive,clint0";
120 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
124 plic0: interrupt-controller@c000000 {
125 #interrupt-cells = <1>;
126 #address-cells = <0>;
127 compatible = "canaan,k210-plic", "sifive,plic-1.0.0";
129 interrupt-controller;
130 interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
136 compatible = "canaan,k210-uarths", "sifive,uart0";
142 gpio0: gpio-controller@38001000 {
143 #interrupt-cells = <2>;
144 #gpio-cells = <2>;
145 compatible = "canaan,k210-gpiohs", "sifive,gpio0";
147 interrupt-controller;
153 gpio-controller;
157 dmac0: dma-controller@50000000 {
158 compatible = "snps,axi-dma-1.01a";
161 #dma-cells = <1>;
163 clock-names = "core-clk", "cfgr-clk";
165 dma-channels = <6>;
166 snps,dma-masters = <2>;
168 snps,data-width = <5>;
169 snps,block-size = <0x200000 0x200000 0x200000
171 snps,axi-max-burst-len = <256>;
175 #address-cells = <1>;
176 #size-cells = <1>;
177 compatible = "simple-pm-bus";
182 #address-cells = <1>;
183 #size-cells = <0>;
184 compatible = "snps,dw-apb-gpio";
188 clock-names = "bus", "db";
191 gpio1_0: gpio-port@0 {
192 #gpio-cells = <2>;
193 #interrupt-cells = <2>;
194 compatible = "snps,dw-apb-gpio-port";
196 interrupt-controller;
198 gpio-controller;
204 compatible = "snps,dw-apb-uart";
209 clock-names = "baudclk", "apb_pclk";
211 reg-io-width = <4>;
212 reg-shift = <2>;
213 dcd-override;
214 dsr-override;
215 cts-override;
216 ri-override;
220 compatible = "snps,dw-apb-uart";
225 clock-names = "baudclk", "apb_pclk";
227 reg-io-width = <4>;
228 reg-shift = <2>;
229 dcd-override;
230 dsr-override;
231 cts-override;
232 ri-override;
236 compatible = "snps,dw-apb-uart";
241 clock-names = "baudclk", "apb_pclk";
243 reg-io-width = <4>;
244 reg-shift = <2>;
245 dcd-override;
246 dsr-override;
247 cts-override;
248 ri-override;
252 compatible = "canaan,k210-spi";
253 spi-slave;
255 #address-cells = <0>;
256 #size-cells = <0>;
260 clock-names = "ssi_clk", "pclk";
265 compatible = "canaan,k210-i2s", "snps,designware-i2s";
269 clock-names = "i2sclk";
274 compatible = "canaan,k210-i2s", "snps,designware-i2s";
278 clock-names = "i2sclk";
283 compatible = "canaan,k210-i2s", "snps,designware-i2s";
287 clock-names = "i2sclk";
292 compatible = "snps,designware-i2c";
297 clock-names = "ref", "pclk";
302 compatible = "snps,designware-i2c";
307 clock-names = "ref", "pclk";
312 compatible = "snps,designware-i2c";
317 clock-names = "ref", "pclk";
322 compatible = "canaan,k210-fpioa";
326 clock-names = "ref", "pclk";
328 canaan,k210-sysctl-power = <&sysctl 108>;
332 compatible = "snps,dw-apb-timer";
337 clock-names = "timer", "pclk";
342 compatible = "snps,dw-apb-timer";
347 clock-names = "timer", "pclk";
352 compatible = "snps,dw-apb-timer";
357 clock-names = "timer", "pclk";
362 compatible = "snps,dw-apb-timer";
367 clock-names = "timer", "pclk";
372 compatible = "snps,dw-apb-timer";
377 clock-names = "timer", "pclk";
382 compatible = "snps,dw-apb-timer";
387 clock-names = "timer", "pclk";
393 #address-cells = <1>;
394 #size-cells = <1>;
395 compatible = "simple-pm-bus";
400 compatible = "snps,dw-wdt";
405 clock-names = "tclk", "pclk";
410 compatible = "snps,dw-wdt";
415 clock-names = "tclk", "pclk";
420 compatible = "canaan,k210-sysctl",
421 "syscon", "simple-mfd";
424 clock-names = "pclk";
426 sysclk: clock-controller {
427 #clock-cells = <1>;
428 compatible = "canaan,k210-clk";
432 sysrst: reset-controller {
433 compatible = "canaan,k210-rst";
434 #reset-cells = <1>;
437 reboot: syscon-reboot {
438 compatible = "syscon-reboot";
448 #address-cells = <1>;
449 #size-cells = <1>;
450 compatible = "simple-pm-bus";
455 #address-cells = <1>;
456 #size-cells = <0>;
457 compatible = "canaan,k210-spi";
462 clock-names = "ssi_clk", "pclk";
464 reset-names = "spi";
465 num-cs = <4>;
466 reg-io-width = <4>;
470 #address-cells = <1>;
471 #size-cells = <0>;
472 compatible = "canaan,k210-spi";
477 clock-names = "ssi_clk", "pclk";
479 reset-names = "spi";
480 num-cs = <4>;
481 reg-io-width = <4>;
485 #address-cells = <1>;
486 #size-cells = <0>;
487 compatible = "snps,dwc-ssi-1.01a";
492 clock-names = "ssi_clk", "pclk";
494 reset-names = "spi";
496 num-cs = <4>;
497 reg-io-width = <4>;