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/openbmc/linux/drivers/memory/
H A Dstm32-fmc2-ebi.c1 // SPDX-License-Identifier: GPL-2.0
148 * struct stm32_fmc2_prop - STM32 FMC2 EBI property
172 const struct stm32_fmc2_prop *prop, int cs);
173 u32 (*calculate)(struct stm32_fmc2_ebi *ebi, int cs, u32 setup);
176 int cs, u32 setup);
181 int cs) in stm32_fmc2_ebi_check_mux() argument
186 ret = regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); in stm32_fmc2_ebi_check_mux()
193 return -EINVAL; in stm32_fmc2_ebi_check_mux()
198 int cs) in stm32_fmc2_ebi_check_waitcfg() argument
203 ret = regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); in stm32_fmc2_ebi_check_waitcfg()
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H A Dti-aemif.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2010 - 2013 Texas Instruments Incorporated. http://www.ti.com/
8 * Murali Karicheri <m-karicheri2@ti.com>
20 #include <linux/platform_data/ti-aemif.h>
84 * struct aemif_cs_data: structure to hold cs parameters
85 * @cs: chip-select number
88 * @wsetup: write setup width, ns
90 * @rsetup: read setup width, ns
98 u8 cs; member
116 * @num_cs: number of assigned chip-selects
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/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dst,stm32-fmc2-ebi-props.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Christophe Kerello <christophe.kerello@foss.st.com>
11 - Marek Vasut <marex@denx.de>
14 st,fmc2-ebi-cs-transaction-type:
33 st,fmc2-ebi-cs-cclk-enable:
40 st,fmc2-ebi-cs-mux-enable:
46 st,fmc2-ebi-cs-buswidth:
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H A Dti-aemif.txt4 provide a glue-less interface to a variety of asynchronous memory devices like
11 Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
12 OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
13 Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
17 - compatible: "ti,davinci-aemif"
18 "ti,keystone-aemif"
19 "ti,da850-aemif"
21 - reg: contains offset/length value for AEMIF control registers
24 - #address-cells: Must be 2. The partition number has to be encoded in the
25 first address cell and it may accept values 0..N-1
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H A Datmel,ebi.txt5 The EBI provides a glue-less interface to asynchronous memories through the SMC
10 - compatible: "atmel,at91sam9260-ebi"
11 "atmel,at91sam9261-ebi"
12 "atmel,at91sam9263-ebi0"
13 "atmel,at91sam9263-ebi1"
14 "atmel,at91sam9rl-ebi"
15 "atmel,at91sam9g45-ebi"
16 "atmel,at91sam9x5-ebi"
17 "atmel,sama5d3-ebi"
18 "microchip,sam9x60-ebi"
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H A Dst,stm32-fmc2-ebi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 asynchronous static devices (such as PSNOR, PSRAM or other memory-mapped
14 - to translate AXI transactions into the appropriate external device
16 - to meet the access time requirements of the external devices
22 - Christophe Kerello <christophe.kerello@foss.st.com>
26 const: st,stm32mp1-fmc2-ebi
37 "#address-cells":
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/openbmc/linux/drivers/mfd/
H A Datmel-smc.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
11 #include <linux/mfd/syscon/atmel-smc.h>
15 * atmel_smc_cs_conf_init - initialize a SMC CS conf
16 * @conf: the SMC CS conf to initialize
27 * atmel_smc_cs_encode_ncycles - encode a number of MCK clk cycles in the
36 * (section "SMC Setup/Pulse/Cycle/Timings Register"). This is a generic
40 * If the @ncycles value is too big to be encoded, -ERANGE is returned and
49 unsigned int lsbmask = GENMASK(msbpos - 1, 0); in atmel_smc_cs_encode_ncycles()
50 unsigned int msbmask = GENMASK(msbwidth - 1, 0); in atmel_smc_cs_encode_ncycles()
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/openbmc/u-boot/arch/arm/mach-omap2/omap3/
H A Dsdrc.c1 // SPDX-License-Identifier: GPL-2.0+
9 * Copyright (C) 2004-2010
10 * Texas Instruments Incorporated - http://www.ti.com/
13 * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de>
35 * is_mem_sdr -
36 * - Return 1 if mem type in use is SDR
40 if (readl(&sdrc_base->cs[CS0].mr) == SDRC_MR_0_SDR) in is_mem_sdr()
46 * make_cs1_contiguous -
47 * - When we have CS1 populated we want to have it mapped after cs0 to allow
59 writel((a_add_high | a_add_low), &sdrc_base->cs_cfg); in make_cs1_contiguous()
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/openbmc/u-boot/cmd/
H A Dmmc_spi.c2 * Command for mmc_spi setup.
5 * Licensed under the GPL-2 or later.
35 uint cs = CONFIG_MMC_SPI_CS; in do_mmc_spi() local
44 cs = simple_strtoul(argv[1], &endp, 0); in do_mmc_spi()
50 bus = cs; in do_mmc_spi()
51 cs = simple_strtoul(endp + 1, &endp, 0); in do_mmc_spi()
65 if (!spi_cs_is_valid(bus, cs)) { in do_mmc_spi()
66 printf("Invalid SPI bus %u cs %u\n", bus, cs); in do_mmc_spi()
70 mmc = mmc_spi_init(bus, cs, speed, mode); in do_mmc_spi()
75 printf("%s: %d at %u:%u hz %u mode %u\n", mmc->cfg->name, in do_mmc_spi()
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/openbmc/linux/include/linux/mfd/syscon/
H A Datmel-smc.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
18 #define ATMEL_SMC_SETUP(cs) (((cs) * 0x10)) argument
19 #define ATMEL_HSMC_SETUP(layout, cs) \ argument
20 ((layout)->timing_regs_offset + ((cs) * 0x14))
21 #define ATMEL_SMC_PULSE(cs) (((cs) * 0x10) + 0x4) argument
22 #define ATMEL_HSMC_PULSE(layout, cs) \ argument
23 ((layout)->timing_regs_offset + ((cs) * 0x14) + 0x4)
24 #define ATMEL_SMC_CYCLE(cs) (((cs) * 0x10) + 0x8) argument
25 #define ATMEL_HSMC_CYCLE(layout, cs) \ argument
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/openbmc/linux/include/linux/platform_data/
H A Dgpmc-omap.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2014 Texas Instruments, Inc. - https://www.ti.com
34 /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
59 u32 access; /* Start-cycle to first data valid delay */
78 u32 t_ceasu; /* address setup to CS valid */
79 u32 t_avdasu; /* address setup to ADV valid */
90 u32 t_oeasu; /* address setup to OE valid */
94 u32 t_ce; /* access time from CS asertion */
96 u32 t_cez_r; /* read CS deassertion to high Z */
97 u32 t_cez_w; /* write CS deassertion to high Z */
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/openbmc/linux/arch/mips/bcm63xx/
H A Dcs.c24 static int is_valid_cs(unsigned int cs) in is_valid_cs() argument
26 if (cs > 6) in is_valid_cs()
35 int bcm63xx_set_cs_base(unsigned int cs, u32 base, unsigned int size) in bcm63xx_set_cs_base() argument
40 if (!is_valid_cs(cs)) in bcm63xx_set_cs_base()
41 return -EINVAL; in bcm63xx_set_cs_base()
45 return -EINVAL; in bcm63xx_set_cs_base()
48 return -EINVAL; in bcm63xx_set_cs_base()
51 /* 8k => 0 - 256M => 15 */ in bcm63xx_set_cs_base()
52 val |= (ilog2(size) - ilog2(8 * 1024)) << MPI_CSBASE_SIZE_SHIFT; in bcm63xx_set_cs_base()
55 bcm_mpi_writel(val, MPI_CSBASE_REG(cs)); in bcm63xx_set_cs_base()
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/openbmc/u-boot/board/atmel/at91sam9261ek/
H A Dat91sam9261ek.c1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2007-2008
24 #include <asm/mach-types.h>
28 /* ------------------------------------------------------------------------- */
41 csa = readl(&matrix->ebicsa); in at91sam9261ek_nand_hw_init()
44 writel(csa, &matrix->ebicsa); in at91sam9261ek_nand_hw_init()
50 &smc->cs[3].setup); in at91sam9261ek_nand_hw_init()
53 &smc->cs[3].pulse); in at91sam9261ek_nand_hw_init()
55 &smc->cs[3].cycle); in at91sam9261ek_nand_hw_init()
59 &smc->cs[3].setup); in at91sam9261ek_nand_hw_init()
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/openbmc/u-boot/arch/sandbox/include/asm/
H A Dspi.h4 * Copyright (c) 2011-2013 The Chromium OS Authors.
8 * Licensed under the GPL-2 or later.
23 /* The bus wants to instantiate a new client, so setup everything */
24 int (*setup)(void **priv, const char *spec); member
27 /* The CS has been "activated" -- we won't worry about low/high */
29 /* The CS has been "deactivated" -- we won't worry about low/high */
31 /* The client is rx-ing bytes from the bus, so it should tx some */
36 * Extract the bus/cs from the spi spec and return the start of the spi
37 * client spec. If the bus/cs are invalid for the current config, then
40 * Example: arg="0:1:foo" will set bus to 0, cs to 1, and return "foo"
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/openbmc/linux/drivers/spi/
H A Dspi-bitbang.c1 // SPDX-License-Identifier: GPL-2.0-or-later
21 /*----------------------------------------------------------------------*/
24 * FIRST PART (OPTIONAL): word-at-a-time spi_transfer support.
25 * Use this for GPIO or shift-register level hardware APIs.
27 * spi_bitbang_cs is in spi_device->controller_state, which is unavailable
28 * to glue code. These bitbang setup() and cleanup() routines are always
29 * used, though maybe they're called from controller-aware code.
31 * chipselect() and friends may use spi_device->controller_data and
65 unsigned bits = t->bits_per_word; in bitbang_txrx_8()
66 unsigned count = t->len; in bitbang_txrx_8()
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/openbmc/linux/arch/arm/boot/dts/st/
H A Dstm32mp15xx-dhcor-drc-compact.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
21 stdout-path = "serial0:115200n8";
25 compatible = "gpio-leds";
29 default-state = "off";
35 default-state = "off";
40 compatible = "regulator-fixed";
41 regulator-name = "vio";
42 regulator-min-microvolt = <3300000>;
43 regulator-max-microvolt = <3300000>;
45 regulator-always-on;
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/openbmc/qemu/bsd-user/x86_64/
H A Dtarget_arch_cpu.h23 #include "signal-common.h"
32 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK; in target_cpu_init()
33 env->hflags |= HF_PE_MASK | HF_CPL_MASK; in target_cpu_init()
34 if (env->features[FEAT_1_EDX] & CPUID_SSE) { in target_cpu_init()
35 env->cr[4] |= CR4_OSFXSR_MASK; in target_cpu_init()
36 env->hflags |= HF_OSFXSR_MASK; in target_cpu_init()
40 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM)) { in target_cpu_init()
44 env->cr[4] |= CR4_PAE_MASK; in target_cpu_init()
45 env->efer |= MSR_EFER_LMA | MSR_EFER_LME; in target_cpu_init()
46 env->hflags |= HF_LMA_MASK; in target_cpu_init()
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/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_init.c1 // SPDX-License-Identifier: GPL-2.0
76 puts("\n########### LOG LEVEL 1 (D-UNIT SETUP)###########\n"); in print_dunit_setup()
79 puts("\nStatic D-UNIT Setup:\n"); in print_dunit_setup()
82 puts("\nDynamic(using SPD) D-UNIT Setup:\n"); in print_dunit_setup()
140 u32 ui, reg, cs; in ddr3_restore_and_set_final_windows() local
157 /* Return XBAR windows 4-7 or 16-19 init configuration */ in ddr3_restore_and_set_final_windows()
161 DEBUG_INIT_FULL_S("DDR3 Training Sequence - Switching XBAR Window to FastPath Window\n"); in ddr3_restore_and_set_final_windows()
168 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_restore_and_set_final_windows()
169 if (cs_ena & (1 << cs)) { in ddr3_restore_and_set_final_windows()
170 /* set fast path window control for the cs */ in ddr3_restore_and_set_final_windows()
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/openbmc/u-boot/arch/arm/dts/
H A Dkeystone-k2l-evm.dts10 /dts-v1/;
13 #include "keystone-k2l.dtsi"
16 compatible = "ti,k2l-evm","ti,keystone";
22 #clock-cells = <0>;
23 compatible = "fixed-clock";
24 clock-frequency = <122880000>;
25 clock-output-names = "refclk-sys";
48 #address-cells = <2>;
49 #size-cells = <1>;
50 clock-ranges;
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H A Dkeystone-k2e-evm.dts2 * Copyright 2013-2014 Texas Instruments, Inc.
10 /dts-v1/;
13 #include "keystone-k2e.dtsi"
16 compatible = "ti,k2e-evm","ti,keystone";
23 #clock-cells = <0>;
24 compatible = "fixed-clock";
25 clock-frequency = <100000000>;
26 clock-output-names = "refclk-sys";
30 #clock-cells = <0>;
31 compatible = "fixed-clock";
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/openbmc/linux/Documentation/devicetree/bindings/display/samsung/
H A Dsamsung,fimd.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Inki Dae <inki.dae@samsung.com>
11 - Seung-Woo Kim <sw0312.kim@samsung.com>
12 - Kyungmin Park <kyungmin.park@samsung.com>
13 - Krzysztof Kozlowski <krzk@kernel.org>
18 - samsung,s3c2443-fimd
19 - samsung,s3c6400-fimd
20 - samsung,s5pv210-fimd
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/openbmc/qemu/bsd-user/i386/
H A Dtarget_arch_cpu.h23 #include "signal-common.h"
32 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK; in target_cpu_init()
33 env->hflags |= HF_PE_MASK | HF_CPL_MASK; in target_cpu_init()
34 if (env->features[FEAT_1_EDX] & CPUID_SSE) { in target_cpu_init()
35 env->cr[4] |= CR4_OSFXSR_MASK; in target_cpu_init()
36 env->hflags |= HF_OSFXSR_MASK; in target_cpu_init()
39 /* flags setup : we activate the IRQs by default as in user mode */ in target_cpu_init()
40 env->eflags |= IF_MASK; in target_cpu_init()
42 /* register setup */ in target_cpu_init()
43 env->regs[R_EAX] = regs->eax; in target_cpu_init()
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/openbmc/u-boot/drivers/spi/
H A Dmxc_spi.c1 // SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/imx-regs.h>
15 #include <asm/mach-imx/spi.h>
27 __weak int board_spi_cs_gpio(unsigned bus, unsigned cs) in board_spi_cs_gpio() argument
29 return -1; in board_spi_cs_gpio()
63 dm_gpio_set_value(&mxcs->ss, 1); in mxc_spi_cs_activate()
65 if (mxcs->gpio > 0) in mxc_spi_cs_activate()
66 gpio_set_value(mxcs->gpio, mxcs->ss_pol); in mxc_spi_cs_activate()
73 dm_gpio_set_value(&mxcs->ss, 0); in mxc_spi_cs_deactivate()
75 if (mxcs->gpio > 0) in mxc_spi_cs_deactivate()
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/openbmc/linux/arch/arm/boot/dts/ti/keystone/
H A Dkeystone-k2l-evm.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/
7 /dts-v1/;
10 #include "keystone-k2l.dtsi"
13 compatible = "ti,k2l-evm", "ti,k2l", "ti,keystone";
16 reserved-memory {
17 #address-cells = <2>;
18 #size-cells = <2>;
21 dsp_common_memory: dsp-common-memory@81f800000 {
22 compatible = "shared-dma-pool";
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H A Dkeystone-k2e-evm.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
7 /dts-v1/;
10 #include "keystone-k2e.dtsi"
13 compatible = "ti,k2e-evm", "ti,k2e", "ti,keystone";
16 reserved-memory {
17 #address-cells = <2>;
18 #size-cells = <2>;
21 dsp_common_memory: dsp-common-memory@81f800000 {
22 compatible = "shared-dma-pool";
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