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/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dmediatek,mt7986-afe.yaml155 assigned-clock-parents = <&topckgen CLK_TOP_APLL2_D4>,
157 <&topckgen CLK_TOP_APLL2_D4>;
H A Dmediatek,mt8188-afe.yaml212 <&topckgen 133>, //CLK_TOP_APLL2_D4
/openbmc/linux/include/dt-bindings/clock/
H A Dmt7986-clk.h38 #define CLK_TOP_APLL2_D4 15 macro
H A Dmediatek,mt7981-clk.h31 #define CLK_TOP_APLL2_D4 18 macro
H A Dmt8516-clk.h71 #define CLK_TOP_APLL2_D4 39 macro
H A Dmediatek,mt8365-clk.h60 #define CLK_TOP_APLL2_D4 50 macro
H A Dmt2712-clk.h81 #define CLK_TOP_APLL2_D4 50 macro
H A Dmt8183-clk.h114 #define CLK_TOP_APLL2_D4 78 macro
H A Dmt8186-clk.h122 #define CLK_TOP_APLL2_D4 103 macro
H A Dmt6779-clk.h89 #define CLK_TOP_APLL2_D4 79 macro
H A Dmt8192-clk.h119 #define CLK_TOP_APLL2_D4 107 macro
H A Dmediatek,mt8188-clk.h145 #define CLK_TOP_APLL2_D4 134 macro
H A Dmt8195-clk.h178 #define CLK_TOP_APLL2_D4 166 macro
/openbmc/linux/sound/soc/mediatek/mt8192/
H A Dmt8192-afe-clk.c37 [CLK_TOP_APLL2_D4] = "top_apll2_d4",
171 afe_priv->clk[CLK_TOP_APLL2_D4]); in apll2_mux_setting()
175 aud_clks[CLK_TOP_APLL2_D4], ret); in apll2_mux_setting()
H A Dmt8192-afe-clk.h194 CLK_TOP_APLL2_D4, enumerator
/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt7986-topckgen.c44 FACTOR(CLK_TOP_APLL2_D4, "top_apll2_d4", "apll2", 1, 4),
H A Dclk-mt7981-topckgen.c41 FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
H A Dclk-mt8516.c66 FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "rg_apll2_d2_en", 1, 2),
H A Dclk-mt8186-topckgen.c57 FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
H A Dclk-mt8167.c73 FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "rg_apll2_d2_en", 1, 2),
H A Dclk-mt8365.c82 FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2_ck", 1, 4),
H A Dclk-mt8183.c77 FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
H A Dclk-mt2712.c89 FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2_ck", 1, 4),
H A Dclk-mt8192.c65 FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
H A Dclk-mt6779.c75 FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),

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