167ea1516SFabien Parent /* SPDX-License-Identifier: GPL-2.0 */ 267ea1516SFabien Parent /* 367ea1516SFabien Parent * Copyright (c) 2019 MediaTek Inc. 467ea1516SFabien Parent * Copyright (c) 2019 BayLibre, SAS. 567ea1516SFabien Parent * Author: James Liao <jamesjj.liao@mediatek.com> 667ea1516SFabien Parent */ 767ea1516SFabien Parent 867ea1516SFabien Parent #ifndef _DT_BINDINGS_CLK_MT8516_H 967ea1516SFabien Parent #define _DT_BINDINGS_CLK_MT8516_H 1067ea1516SFabien Parent 11699480d0SFabien Parent /* APMIXEDSYS */ 12699480d0SFabien Parent 13699480d0SFabien Parent #define CLK_APMIXED_ARMPLL 0 14699480d0SFabien Parent #define CLK_APMIXED_MAINPLL 1 15699480d0SFabien Parent #define CLK_APMIXED_UNIVPLL 2 16699480d0SFabien Parent #define CLK_APMIXED_MMPLL 3 17699480d0SFabien Parent #define CLK_APMIXED_APLL1 4 18699480d0SFabien Parent #define CLK_APMIXED_APLL2 5 19699480d0SFabien Parent #define CLK_APMIXED_NR_CLK 6 20699480d0SFabien Parent 21eb2814bcSFabien Parent /* INFRACFG */ 22eb2814bcSFabien Parent 23eb2814bcSFabien Parent #define CLK_IFR_MUX1_SEL 0 24eb2814bcSFabien Parent #define CLK_IFR_ETH_25M_SEL 1 25eb2814bcSFabien Parent #define CLK_IFR_I2C0_SEL 2 26eb2814bcSFabien Parent #define CLK_IFR_I2C1_SEL 3 27eb2814bcSFabien Parent #define CLK_IFR_I2C2_SEL 4 28eb2814bcSFabien Parent #define CLK_IFR_NR_CLK 5 29eb2814bcSFabien Parent 3067ea1516SFabien Parent /* TOPCKGEN */ 3167ea1516SFabien Parent 3267ea1516SFabien Parent #define CLK_TOP_CLK_NULL 0 3367ea1516SFabien Parent #define CLK_TOP_I2S_INFRA_BCK 1 3467ea1516SFabien Parent #define CLK_TOP_MEMPLL 2 3567ea1516SFabien Parent #define CLK_TOP_DMPLL 3 3667ea1516SFabien Parent #define CLK_TOP_MAINPLL_D2 4 3767ea1516SFabien Parent #define CLK_TOP_MAINPLL_D4 5 3867ea1516SFabien Parent #define CLK_TOP_MAINPLL_D8 6 3967ea1516SFabien Parent #define CLK_TOP_MAINPLL_D16 7 4067ea1516SFabien Parent #define CLK_TOP_MAINPLL_D11 8 4167ea1516SFabien Parent #define CLK_TOP_MAINPLL_D22 9 4267ea1516SFabien Parent #define CLK_TOP_MAINPLL_D3 10 4367ea1516SFabien Parent #define CLK_TOP_MAINPLL_D6 11 4467ea1516SFabien Parent #define CLK_TOP_MAINPLL_D12 12 4567ea1516SFabien Parent #define CLK_TOP_MAINPLL_D5 13 4667ea1516SFabien Parent #define CLK_TOP_MAINPLL_D10 14 4767ea1516SFabien Parent #define CLK_TOP_MAINPLL_D20 15 4867ea1516SFabien Parent #define CLK_TOP_MAINPLL_D40 16 4967ea1516SFabien Parent #define CLK_TOP_MAINPLL_D7 17 5067ea1516SFabien Parent #define CLK_TOP_MAINPLL_D14 18 5167ea1516SFabien Parent #define CLK_TOP_UNIVPLL_D2 19 5267ea1516SFabien Parent #define CLK_TOP_UNIVPLL_D4 20 5367ea1516SFabien Parent #define CLK_TOP_UNIVPLL_D8 21 5467ea1516SFabien Parent #define CLK_TOP_UNIVPLL_D16 22 5567ea1516SFabien Parent #define CLK_TOP_UNIVPLL_D3 23 5667ea1516SFabien Parent #define CLK_TOP_UNIVPLL_D6 24 5767ea1516SFabien Parent #define CLK_TOP_UNIVPLL_D12 25 5867ea1516SFabien Parent #define CLK_TOP_UNIVPLL_D24 26 5967ea1516SFabien Parent #define CLK_TOP_UNIVPLL_D5 27 6067ea1516SFabien Parent #define CLK_TOP_UNIVPLL_D20 28 6167ea1516SFabien Parent #define CLK_TOP_MMPLL380M 29 6267ea1516SFabien Parent #define CLK_TOP_MMPLL_D2 30 6367ea1516SFabien Parent #define CLK_TOP_MMPLL_200M 31 6467ea1516SFabien Parent #define CLK_TOP_USB_PHY48M 32 6567ea1516SFabien Parent #define CLK_TOP_APLL1 33 6667ea1516SFabien Parent #define CLK_TOP_APLL1_D2 34 6767ea1516SFabien Parent #define CLK_TOP_APLL1_D4 35 6867ea1516SFabien Parent #define CLK_TOP_APLL1_D8 36 6967ea1516SFabien Parent #define CLK_TOP_APLL2 37 7067ea1516SFabien Parent #define CLK_TOP_APLL2_D2 38 7167ea1516SFabien Parent #define CLK_TOP_APLL2_D4 39 7267ea1516SFabien Parent #define CLK_TOP_APLL2_D8 40 7367ea1516SFabien Parent #define CLK_TOP_CLK26M 41 7467ea1516SFabien Parent #define CLK_TOP_CLK26M_D2 42 7567ea1516SFabien Parent #define CLK_TOP_AHB_INFRA_D2 43 7667ea1516SFabien Parent #define CLK_TOP_NFI1X 44 7767ea1516SFabien Parent #define CLK_TOP_ETH_D2 45 7867ea1516SFabien Parent #define CLK_TOP_THEM 46 7967ea1516SFabien Parent #define CLK_TOP_APDMA 47 8067ea1516SFabien Parent #define CLK_TOP_I2C0 48 8167ea1516SFabien Parent #define CLK_TOP_I2C1 49 8267ea1516SFabien Parent #define CLK_TOP_AUXADC1 50 8367ea1516SFabien Parent #define CLK_TOP_NFI 51 8467ea1516SFabien Parent #define CLK_TOP_NFIECC 52 8567ea1516SFabien Parent #define CLK_TOP_DEBUGSYS 53 8667ea1516SFabien Parent #define CLK_TOP_PWM 54 8767ea1516SFabien Parent #define CLK_TOP_UART0 55 8867ea1516SFabien Parent #define CLK_TOP_UART1 56 8967ea1516SFabien Parent #define CLK_TOP_BTIF 57 9067ea1516SFabien Parent #define CLK_TOP_USB 58 9167ea1516SFabien Parent #define CLK_TOP_FLASHIF_26M 59 9267ea1516SFabien Parent #define CLK_TOP_AUXADC2 60 9367ea1516SFabien Parent #define CLK_TOP_I2C2 61 9467ea1516SFabien Parent #define CLK_TOP_MSDC0 62 9567ea1516SFabien Parent #define CLK_TOP_MSDC1 63 9667ea1516SFabien Parent #define CLK_TOP_NFI2X 64 9767ea1516SFabien Parent #define CLK_TOP_PMICWRAP_AP 65 9867ea1516SFabien Parent #define CLK_TOP_SEJ 66 9967ea1516SFabien Parent #define CLK_TOP_MEMSLP_DLYER 67 10067ea1516SFabien Parent #define CLK_TOP_SPI 68 10167ea1516SFabien Parent #define CLK_TOP_APXGPT 69 10267ea1516SFabien Parent #define CLK_TOP_AUDIO 70 10367ea1516SFabien Parent #define CLK_TOP_PMICWRAP_MD 71 10467ea1516SFabien Parent #define CLK_TOP_PMICWRAP_CONN 72 10567ea1516SFabien Parent #define CLK_TOP_PMICWRAP_26M 73 10667ea1516SFabien Parent #define CLK_TOP_AUX_ADC 74 10767ea1516SFabien Parent #define CLK_TOP_AUX_TP 75 10867ea1516SFabien Parent #define CLK_TOP_MSDC2 76 10967ea1516SFabien Parent #define CLK_TOP_RBIST 77 11067ea1516SFabien Parent #define CLK_TOP_NFI_BUS 78 11167ea1516SFabien Parent #define CLK_TOP_GCE 79 11267ea1516SFabien Parent #define CLK_TOP_TRNG 80 11367ea1516SFabien Parent #define CLK_TOP_SEJ_13M 81 11467ea1516SFabien Parent #define CLK_TOP_AES 82 11567ea1516SFabien Parent #define CLK_TOP_PWM_B 83 11667ea1516SFabien Parent #define CLK_TOP_PWM1_FB 84 11767ea1516SFabien Parent #define CLK_TOP_PWM2_FB 85 11867ea1516SFabien Parent #define CLK_TOP_PWM3_FB 86 11967ea1516SFabien Parent #define CLK_TOP_PWM4_FB 87 12067ea1516SFabien Parent #define CLK_TOP_PWM5_FB 88 12167ea1516SFabien Parent #define CLK_TOP_USB_1P 89 12267ea1516SFabien Parent #define CLK_TOP_FLASHIF_FREERUN 90 12367ea1516SFabien Parent #define CLK_TOP_66M_ETH 91 12467ea1516SFabien Parent #define CLK_TOP_133M_ETH 92 12567ea1516SFabien Parent #define CLK_TOP_FETH_25M 93 12667ea1516SFabien Parent #define CLK_TOP_FETH_50M 94 12767ea1516SFabien Parent #define CLK_TOP_FLASHIF_AXI 95 12867ea1516SFabien Parent #define CLK_TOP_USBIF 96 12967ea1516SFabien Parent #define CLK_TOP_UART2 97 13067ea1516SFabien Parent #define CLK_TOP_BSI 98 13167ea1516SFabien Parent #define CLK_TOP_RG_SPINOR 99 13267ea1516SFabien Parent #define CLK_TOP_RG_MSDC2 100 13367ea1516SFabien Parent #define CLK_TOP_RG_ETH 101 13467ea1516SFabien Parent #define CLK_TOP_RG_AUD1 102 13567ea1516SFabien Parent #define CLK_TOP_RG_AUD2 103 13667ea1516SFabien Parent #define CLK_TOP_RG_AUD_ENGEN1 104 13767ea1516SFabien Parent #define CLK_TOP_RG_AUD_ENGEN2 105 13867ea1516SFabien Parent #define CLK_TOP_RG_I2C 106 13967ea1516SFabien Parent #define CLK_TOP_RG_PWM_INFRA 107 14067ea1516SFabien Parent #define CLK_TOP_RG_AUD_SPDIF_IN 108 14167ea1516SFabien Parent #define CLK_TOP_RG_UART2 109 14267ea1516SFabien Parent #define CLK_TOP_RG_BSI 110 14367ea1516SFabien Parent #define CLK_TOP_RG_DBG_ATCLK 111 14467ea1516SFabien Parent #define CLK_TOP_RG_NFIECC 112 14567ea1516SFabien Parent #define CLK_TOP_RG_APLL1_D2_EN 113 14667ea1516SFabien Parent #define CLK_TOP_RG_APLL1_D4_EN 114 14767ea1516SFabien Parent #define CLK_TOP_RG_APLL1_D8_EN 115 14867ea1516SFabien Parent #define CLK_TOP_RG_APLL2_D2_EN 116 14967ea1516SFabien Parent #define CLK_TOP_RG_APLL2_D4_EN 117 15067ea1516SFabien Parent #define CLK_TOP_RG_APLL2_D8_EN 118 15167ea1516SFabien Parent #define CLK_TOP_APLL12_DIV0 119 15267ea1516SFabien Parent #define CLK_TOP_APLL12_DIV1 120 15367ea1516SFabien Parent #define CLK_TOP_APLL12_DIV2 121 15467ea1516SFabien Parent #define CLK_TOP_APLL12_DIV3 122 15567ea1516SFabien Parent #define CLK_TOP_APLL12_DIV4 123 15667ea1516SFabien Parent #define CLK_TOP_APLL12_DIV4B 124 15767ea1516SFabien Parent #define CLK_TOP_APLL12_DIV5 125 15867ea1516SFabien Parent #define CLK_TOP_APLL12_DIV5B 126 15967ea1516SFabien Parent #define CLK_TOP_APLL12_DIV6 127 16067ea1516SFabien Parent #define CLK_TOP_UART0_SEL 128 16167ea1516SFabien Parent #define CLK_TOP_EMI_DDRPHY_SEL 129 16267ea1516SFabien Parent #define CLK_TOP_AHB_INFRA_SEL 130 16367ea1516SFabien Parent #define CLK_TOP_MSDC0_SEL 131 16467ea1516SFabien Parent #define CLK_TOP_UART1_SEL 132 16567ea1516SFabien Parent #define CLK_TOP_MSDC1_SEL 133 16667ea1516SFabien Parent #define CLK_TOP_PMICSPI_SEL 134 16767ea1516SFabien Parent #define CLK_TOP_QAXI_AUD26M_SEL 135 16867ea1516SFabien Parent #define CLK_TOP_AUD_INTBUS_SEL 136 16967ea1516SFabien Parent #define CLK_TOP_NFI2X_PAD_SEL 137 17067ea1516SFabien Parent #define CLK_TOP_NFI1X_PAD_SEL 138 17167ea1516SFabien Parent #define CLK_TOP_DDRPHYCFG_SEL 139 17267ea1516SFabien Parent #define CLK_TOP_USB_78M_SEL 140 17367ea1516SFabien Parent #define CLK_TOP_SPINOR_SEL 141 17467ea1516SFabien Parent #define CLK_TOP_MSDC2_SEL 142 17567ea1516SFabien Parent #define CLK_TOP_ETH_SEL 143 17667ea1516SFabien Parent #define CLK_TOP_AUD1_SEL 144 17767ea1516SFabien Parent #define CLK_TOP_AUD2_SEL 145 17867ea1516SFabien Parent #define CLK_TOP_AUD_ENGEN1_SEL 146 17967ea1516SFabien Parent #define CLK_TOP_AUD_ENGEN2_SEL 147 18067ea1516SFabien Parent #define CLK_TOP_I2C_SEL 148 18167ea1516SFabien Parent #define CLK_TOP_AUD_I2S0_M_SEL 149 18267ea1516SFabien Parent #define CLK_TOP_AUD_I2S1_M_SEL 150 18367ea1516SFabien Parent #define CLK_TOP_AUD_I2S2_M_SEL 151 18467ea1516SFabien Parent #define CLK_TOP_AUD_I2S3_M_SEL 152 18567ea1516SFabien Parent #define CLK_TOP_AUD_I2S4_M_SEL 153 18667ea1516SFabien Parent #define CLK_TOP_AUD_I2S5_M_SEL 154 18767ea1516SFabien Parent #define CLK_TOP_AUD_SPDIF_B_SEL 155 18867ea1516SFabien Parent #define CLK_TOP_PWM_SEL 156 18967ea1516SFabien Parent #define CLK_TOP_SPI_SEL 157 19067ea1516SFabien Parent #define CLK_TOP_AUD_SPDIFIN_SEL 158 19167ea1516SFabien Parent #define CLK_TOP_UART2_SEL 159 19267ea1516SFabien Parent #define CLK_TOP_BSI_SEL 160 19367ea1516SFabien Parent #define CLK_TOP_DBG_ATCLK_SEL 161 19467ea1516SFabien Parent #define CLK_TOP_CSW_NFIECC_SEL 162 19567ea1516SFabien Parent #define CLK_TOP_NFIECC_SEL 163 19667ea1516SFabien Parent #define CLK_TOP_APLL12_CK_DIV0 164 19767ea1516SFabien Parent #define CLK_TOP_APLL12_CK_DIV1 165 19867ea1516SFabien Parent #define CLK_TOP_APLL12_CK_DIV2 166 19967ea1516SFabien Parent #define CLK_TOP_APLL12_CK_DIV3 167 20067ea1516SFabien Parent #define CLK_TOP_APLL12_CK_DIV4 168 20167ea1516SFabien Parent #define CLK_TOP_APLL12_CK_DIV4B 169 20267ea1516SFabien Parent #define CLK_TOP_APLL12_CK_DIV5 170 20367ea1516SFabien Parent #define CLK_TOP_APLL12_CK_DIV5B 171 20467ea1516SFabien Parent #define CLK_TOP_APLL12_CK_DIV6 172 20567ea1516SFabien Parent #define CLK_TOP_USB_78M 173 20667ea1516SFabien Parent #define CLK_TOP_MSDC0_INFRA 174 20767ea1516SFabien Parent #define CLK_TOP_MSDC1_INFRA 175 20867ea1516SFabien Parent #define CLK_TOP_MSDC2_INFRA 176 20967ea1516SFabien Parent #define CLK_TOP_NR_CLK 177 21067ea1516SFabien Parent 2113d8b6e9cSFabien Parent /* AUDSYS */ 2123d8b6e9cSFabien Parent 2133d8b6e9cSFabien Parent #define CLK_AUD_AFE 0 2143d8b6e9cSFabien Parent #define CLK_AUD_I2S 1 2153d8b6e9cSFabien Parent #define CLK_AUD_22M 2 2163d8b6e9cSFabien Parent #define CLK_AUD_24M 3 2173d8b6e9cSFabien Parent #define CLK_AUD_INTDIR 4 2183d8b6e9cSFabien Parent #define CLK_AUD_APLL2_TUNER 5 2193d8b6e9cSFabien Parent #define CLK_AUD_APLL_TUNER 6 2203d8b6e9cSFabien Parent #define CLK_AUD_HDMI 7 2213d8b6e9cSFabien Parent #define CLK_AUD_SPDF 8 2223d8b6e9cSFabien Parent #define CLK_AUD_ADC 9 2233d8b6e9cSFabien Parent #define CLK_AUD_DAC 10 2243d8b6e9cSFabien Parent #define CLK_AUD_DAC_PREDIS 11 2253d8b6e9cSFabien Parent #define CLK_AUD_TML 12 2263d8b6e9cSFabien Parent #define CLK_AUD_NR_CLK 13 2273d8b6e9cSFabien Parent 22867ea1516SFabien Parent #endif /* _DT_BINDINGS_CLK_MT8516_H */ 229