1b4966a7dSSam Shih // SPDX-License-Identifier: GPL-2.0 2ec97d23cSSam Shih /* 3ec97d23cSSam Shih * Copyright (c) 2021 MediaTek Inc. 4ec97d23cSSam Shih * Author: Sam Shih <sam.shih@mediatek.com> 5ec97d23cSSam Shih * Author: Wenzhen Yu <wenzhen.yu@mediatek.com> 6ec97d23cSSam Shih */ 7ec97d23cSSam Shih 8ec97d23cSSam Shih #include <linux/clk-provider.h> 9*a96cbb14SRob Herring #include <linux/mod_devicetable.h> 10ec97d23cSSam Shih #include <linux/platform_device.h> 11ec97d23cSSam Shih #include "clk-mtk.h" 12ec97d23cSSam Shih #include "clk-gate.h" 13ec97d23cSSam Shih #include "clk-mux.h" 14ec97d23cSSam Shih 15ec97d23cSSam Shih #include <dt-bindings/clock/mt7986-clk.h> 16ec97d23cSSam Shih #include <linux/clk.h> 17ec97d23cSSam Shih 18ec97d23cSSam Shih static DEFINE_SPINLOCK(mt7986_clk_lock); 19ec97d23cSSam Shih 20ec97d23cSSam Shih static const struct mtk_fixed_clk top_fixed_clks[] = { 21ec97d23cSSam Shih FIXED_CLK(CLK_TOP_XTAL, "top_xtal", "clkxtal", 40000000), 22ec97d23cSSam Shih FIXED_CLK(CLK_TOP_JTAG, "top_jtag", "clkxtal", 50000000), 23ec97d23cSSam Shih }; 24ec97d23cSSam Shih 25ec97d23cSSam Shih static const struct mtk_fixed_factor top_divs[] = { 26ec97d23cSSam Shih /* XTAL */ 27ec97d23cSSam Shih FACTOR(CLK_TOP_XTAL_D2, "top_xtal_d2", "top_xtal", 1, 2), 28ec97d23cSSam Shih FACTOR(CLK_TOP_RTC_32K, "top_rtc_32k", "top_xtal", 1, 1250), 29ec97d23cSSam Shih FACTOR(CLK_TOP_RTC_32P7K, "top_rtc_32p7k", "top_xtal", 1, 1220), 30ec97d23cSSam Shih /* MPLL */ 31ec97d23cSSam Shih FACTOR(CLK_TOP_MPLL_D2, "top_mpll_d2", "mpll", 1, 2), 32ec97d23cSSam Shih FACTOR(CLK_TOP_MPLL_D4, "top_mpll_d4", "mpll", 1, 4), 33ec97d23cSSam Shih FACTOR(CLK_TOP_MPLL_D8, "top_mpll_d8", "mpll", 1, 8), 34ec97d23cSSam Shih FACTOR(CLK_TOP_MPLL_D8_D2, "top_mpll_d8_d2", "mpll", 1, 16), 35ec97d23cSSam Shih FACTOR(CLK_TOP_MPLL_D3_D2, "top_mpll_d3_d2", "mpll", 1, 6), 36ec97d23cSSam Shih /* MMPLL */ 37ec97d23cSSam Shih FACTOR(CLK_TOP_MMPLL_D2, "top_mmpll_d2", "mmpll", 1, 2), 38ec97d23cSSam Shih FACTOR(CLK_TOP_MMPLL_D4, "top_mmpll_d4", "mmpll", 1, 4), 39ec97d23cSSam Shih FACTOR(CLK_TOP_MMPLL_D8, "top_mmpll_d8", "mmpll", 1, 8), 40ec97d23cSSam Shih FACTOR(CLK_TOP_MMPLL_D8_D2, "top_mmpll_d8_d2", "mmpll", 1, 16), 41ec97d23cSSam Shih FACTOR(CLK_TOP_MMPLL_D3_D8, "top_mmpll_d3_d8", "mmpll", 1, 24), 42ec97d23cSSam Shih FACTOR(CLK_TOP_MMPLL_U2PHY, "top_mmpll_u2phy", "mmpll", 1, 30), 43ec97d23cSSam Shih /* APLL2 */ 44ec97d23cSSam Shih FACTOR(CLK_TOP_APLL2_D4, "top_apll2_d4", "apll2", 1, 4), 45ec97d23cSSam Shih /* NET1PLL */ 46ec97d23cSSam Shih FACTOR(CLK_TOP_NET1PLL_D4, "top_net1pll_d4", "net1pll", 1, 4), 47ec97d23cSSam Shih FACTOR(CLK_TOP_NET1PLL_D5, "top_net1pll_d5", "net1pll", 1, 5), 48ec97d23cSSam Shih FACTOR(CLK_TOP_NET1PLL_D5_D2, "top_net1pll_d5_d2", "net1pll", 1, 10), 49ec97d23cSSam Shih FACTOR(CLK_TOP_NET1PLL_D5_D4, "top_net1pll_d5_d4", "net1pll", 1, 20), 50ec97d23cSSam Shih FACTOR(CLK_TOP_NET1PLL_D8_D2, "top_net1pll_d8_d2", "net1pll", 1, 16), 51ec97d23cSSam Shih FACTOR(CLK_TOP_NET1PLL_D8_D4, "top_net1pll_d8_d4", "net1pll", 1, 32), 52ec97d23cSSam Shih /* NET2PLL */ 53ec97d23cSSam Shih FACTOR(CLK_TOP_NET2PLL_D4, "top_net2pll_d4", "net2pll", 1, 4), 54ec97d23cSSam Shih FACTOR(CLK_TOP_NET2PLL_D4_D2, "top_net2pll_d4_d2", "net2pll", 1, 8), 55ec97d23cSSam Shih FACTOR(CLK_TOP_NET2PLL_D3_D2, "top_net2pll_d3_d2", "net2pll", 1, 2), 56ec97d23cSSam Shih /* WEDMCUPLL */ 57ec97d23cSSam Shih FACTOR(CLK_TOP_WEDMCUPLL_D5_D2, "top_wedmcupll_d5_d2", "wedmcupll", 1, 58ec97d23cSSam Shih 10), 59ec97d23cSSam Shih }; 60ec97d23cSSam Shih 61ec97d23cSSam Shih static const char *const nfi1x_parents[] __initconst = { "top_xtal", 62ec97d23cSSam Shih "top_mmpll_d8", 63ec97d23cSSam Shih "top_net1pll_d8_d2", 64ec97d23cSSam Shih "top_net2pll_d3_d2", 65ec97d23cSSam Shih "top_mpll_d4", 66ec97d23cSSam Shih "top_mmpll_d8_d2", 67ec97d23cSSam Shih "top_wedmcupll_d5_d2", 68ec97d23cSSam Shih "top_mpll_d8" }; 69ec97d23cSSam Shih 70ec97d23cSSam Shih static const char *const spinfi_parents[] __initconst = { 71ec97d23cSSam Shih "top_xtal_d2", "top_xtal", "top_net1pll_d5_d4", 72ec97d23cSSam Shih "top_mpll_d4", "top_mmpll_d8_d2", "top_wedmcupll_d5_d2", 73ec97d23cSSam Shih "top_mmpll_d3_d8", "top_mpll_d8" 74ec97d23cSSam Shih }; 75ec97d23cSSam Shih 76ec97d23cSSam Shih static const char *const spi_parents[] __initconst = { 77ec97d23cSSam Shih "top_xtal", "top_mpll_d2", "top_mmpll_d8", 78ec97d23cSSam Shih "top_net1pll_d8_d2", "top_net2pll_d3_d2", "top_net1pll_d5_d4", 79ec97d23cSSam Shih "top_mpll_d4", "top_wedmcupll_d5_d2" 80ec97d23cSSam Shih }; 81ec97d23cSSam Shih 82ec97d23cSSam Shih static const char *const uart_parents[] __initconst = { "top_xtal", 83ec97d23cSSam Shih "top_mpll_d8", 84ec97d23cSSam Shih "top_mpll_d8_d2" }; 85ec97d23cSSam Shih 86ec97d23cSSam Shih static const char *const pwm_parents[] __initconst = { 87ec97d23cSSam Shih "top_xtal", "top_net1pll_d8_d2", "top_net1pll_d5_d4", "top_mpll_d4" 88ec97d23cSSam Shih }; 89ec97d23cSSam Shih 90ec97d23cSSam Shih static const char *const i2c_parents[] __initconst = { 91ec97d23cSSam Shih "top_xtal", "top_net1pll_d5_d4", "top_mpll_d4", "top_net1pll_d8_d4" 92ec97d23cSSam Shih }; 93ec97d23cSSam Shih 94ec97d23cSSam Shih static const char *const pextp_tl_ck_parents[] __initconst = { 95ec97d23cSSam Shih "top_xtal", "top_net1pll_d5_d4", "top_net2pll_d4_d2", "top_rtc_32k" 96ec97d23cSSam Shih }; 97ec97d23cSSam Shih 98ec97d23cSSam Shih static const char *const emmc_250m_parents[] __initconst = { 99ec97d23cSSam Shih "top_xtal", "top_net1pll_d5_d2" 100ec97d23cSSam Shih }; 101ec97d23cSSam Shih 102ec97d23cSSam Shih static const char *const emmc_416m_parents[] __initconst = { "top_xtal", 103ec97d23cSSam Shih "mpll" }; 104ec97d23cSSam Shih 105ec97d23cSSam Shih static const char *const f_26m_adc_parents[] __initconst = { "top_xtal", 106ec97d23cSSam Shih "top_mpll_d8_d2" }; 107ec97d23cSSam Shih 108ec97d23cSSam Shih static const char *const dramc_md32_parents[] __initconst = { "top_xtal", 109ec97d23cSSam Shih "top_mpll_d2" }; 110ec97d23cSSam Shih 111ec97d23cSSam Shih static const char *const sysaxi_parents[] __initconst = { "top_xtal", 112ec97d23cSSam Shih "top_net1pll_d8_d2", 113ec97d23cSSam Shih "top_net2pll_d4" }; 114ec97d23cSSam Shih 115ec97d23cSSam Shih static const char *const sysapb_parents[] __initconst = { "top_xtal", 116ec97d23cSSam Shih "top_mpll_d3_d2", 117ec97d23cSSam Shih "top_net2pll_d4_d2" }; 118ec97d23cSSam Shih 119ec97d23cSSam Shih static const char *const arm_db_main_parents[] __initconst = { 120ec97d23cSSam Shih "top_xtal", "top_net2pll_d3_d2" 121ec97d23cSSam Shih }; 122ec97d23cSSam Shih 123ec97d23cSSam Shih static const char *const arm_db_jtsel_parents[] __initconst = { "top_jtag", 124ec97d23cSSam Shih "top_xtal" }; 125ec97d23cSSam Shih 126ec97d23cSSam Shih static const char *const netsys_parents[] __initconst = { "top_xtal", 127ec97d23cSSam Shih "top_mmpll_d4" }; 128ec97d23cSSam Shih 129ec97d23cSSam Shih static const char *const netsys_500m_parents[] __initconst = { 130ec97d23cSSam Shih "top_xtal", "top_net1pll_d5" 131ec97d23cSSam Shih }; 132ec97d23cSSam Shih 133ec97d23cSSam Shih static const char *const netsys_mcu_parents[] __initconst = { 134ec97d23cSSam Shih "top_xtal", "wedmcupll", "top_mmpll_d2", "top_net1pll_d4", 135ec97d23cSSam Shih "top_net1pll_d5" 136ec97d23cSSam Shih }; 137ec97d23cSSam Shih 138ec97d23cSSam Shih static const char *const netsys_2x_parents[] __initconst = { 139ec97d23cSSam Shih "top_xtal", "net2pll", "wedmcupll", "top_mmpll_d2" 140ec97d23cSSam Shih }; 141ec97d23cSSam Shih 142ec97d23cSSam Shih static const char *const sgm_325m_parents[] __initconst = { "top_xtal", 143ec97d23cSSam Shih "sgmpll" }; 144ec97d23cSSam Shih 145ec97d23cSSam Shih static const char *const sgm_reg_parents[] __initconst = { 146ec97d23cSSam Shih "top_xtal", "top_net1pll_d8_d4" 147ec97d23cSSam Shih }; 148ec97d23cSSam Shih 149ec97d23cSSam Shih static const char *const a1sys_parents[] __initconst = { "top_xtal", 150ec97d23cSSam Shih "top_apll2_d4" }; 151ec97d23cSSam Shih 152ec97d23cSSam Shih static const char *const conn_mcusys_parents[] __initconst = { "top_xtal", 153ec97d23cSSam Shih "top_mmpll_d2" }; 154ec97d23cSSam Shih 155ec97d23cSSam Shih static const char *const eip_b_parents[] __initconst = { "top_xtal", 156ec97d23cSSam Shih "net2pll" }; 157ec97d23cSSam Shih 158ec97d23cSSam Shih static const char *const aud_l_parents[] __initconst = { "top_xtal", "apll2", 159ec97d23cSSam Shih "top_mpll_d8_d2" }; 160ec97d23cSSam Shih 161ec97d23cSSam Shih static const char *const a_tuner_parents[] __initconst = { "top_xtal", 162ec97d23cSSam Shih "top_apll2_d4", 163ec97d23cSSam Shih "top_mpll_d8_d2" }; 164ec97d23cSSam Shih 165ec97d23cSSam Shih static const char *const u2u3_sys_parents[] __initconst = { 166ec97d23cSSam Shih "top_xtal", "top_net1pll_d5_d4" 167ec97d23cSSam Shih }; 168ec97d23cSSam Shih 169ec97d23cSSam Shih static const char *const da_u2_refsel_parents[] __initconst = { 170ec97d23cSSam Shih "top_xtal", "top_mmpll_u2phy" 171ec97d23cSSam Shih }; 172ec97d23cSSam Shih 173ec97d23cSSam Shih static const struct mtk_mux top_muxes[] = { 174ec97d23cSSam Shih /* CLK_CFG_0 */ 175ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 176ec97d23cSSam Shih 0x000, 0x004, 0x008, 0, 3, 7, 0x1C0, 0), 177ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 178ec97d23cSSam Shih 0x000, 0x004, 0x008, 8, 3, 15, 0x1C0, 1), 179ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x000, 180ec97d23cSSam Shih 0x004, 0x008, 16, 3, 23, 0x1C0, 2), 181ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 182ec97d23cSSam Shih 0x000, 0x004, 0x008, 24, 3, 31, 0x1C0, 3), 183ec97d23cSSam Shih /* CLK_CFG_1 */ 184ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x010, 185ec97d23cSSam Shih 0x014, 0x018, 0, 2, 7, 0x1C0, 4), 186ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x010, 187ec97d23cSSam Shih 0x014, 0x018, 8, 2, 15, 0x1C0, 5), 188ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x010, 189ec97d23cSSam Shih 0x014, 0x018, 16, 2, 23, 0x1C0, 6), 190ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", 191ec97d23cSSam Shih pextp_tl_ck_parents, 0x010, 0x014, 0x018, 24, 2, 192ec97d23cSSam Shih 31, 0x1C0, 7), 193ec97d23cSSam Shih /* CLK_CFG_2 */ 194f235f6aeSAngeloGioacchino Del Regno MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel", 195ec97d23cSSam Shih emmc_250m_parents, 0x020, 0x024, 0x028, 0, 1, 7, 196f235f6aeSAngeloGioacchino Del Regno 0x1C0, 8, 0), 197f235f6aeSAngeloGioacchino Del Regno MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_EMMC_416M_SEL, "emmc_416m_sel", 198ec97d23cSSam Shih emmc_416m_parents, 0x020, 0x024, 0x028, 8, 1, 15, 199f235f6aeSAngeloGioacchino Del Regno 0x1C0, 9, 0), 200ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_F_26M_ADC_SEL, "f_26m_adc_sel", 201ec97d23cSSam Shih f_26m_adc_parents, 0x020, 0x024, 0x028, 16, 1, 23, 202ec97d23cSSam Shih 0x1C0, 10), 203a0c3ef25SAngeloGioacchino Del Regno MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel", 204a0c3ef25SAngeloGioacchino Del Regno f_26m_adc_parents, 0x020, 0x024, 0x028, 205a0c3ef25SAngeloGioacchino Del Regno 24, 1, 31, 0x1C0, 11, 206a0c3ef25SAngeloGioacchino Del Regno CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 207ec97d23cSSam Shih /* CLK_CFG_3 */ 208a0c3ef25SAngeloGioacchino Del Regno MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", 209a0c3ef25SAngeloGioacchino Del Regno dramc_md32_parents, 0x030, 0x034, 0x038, 210a0c3ef25SAngeloGioacchino Del Regno 0, 1, 7, 0x1C0, 12, 211a0c3ef25SAngeloGioacchino Del Regno CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 212a0c3ef25SAngeloGioacchino Del Regno MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", 213a0c3ef25SAngeloGioacchino Del Regno sysaxi_parents, 0x030, 0x034, 0x038, 214a0c3ef25SAngeloGioacchino Del Regno 8, 2, 15, 0x1C0, 13, 215a0c3ef25SAngeloGioacchino Del Regno CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 216a0c3ef25SAngeloGioacchino Del Regno MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel", 217a0c3ef25SAngeloGioacchino Del Regno sysapb_parents, 0x030, 0x034, 0x038, 218a0c3ef25SAngeloGioacchino Del Regno 16, 2, 23, 0x1C0, 14, 219a0c3ef25SAngeloGioacchino Del Regno CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 220ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel", 221ec97d23cSSam Shih arm_db_main_parents, 0x030, 0x034, 0x038, 24, 1, 222ec97d23cSSam Shih 31, 0x1C0, 15), 223ec97d23cSSam Shih /* CLK_CFG_4 */ 224ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_JTSEL, "arm_db_jtsel", 225ec97d23cSSam Shih arm_db_jtsel_parents, 0x040, 0x044, 0x048, 0, 1, 7, 226ec97d23cSSam Shih 0x1C0, 16), 227ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 228ec97d23cSSam Shih 0x040, 0x044, 0x048, 8, 1, 15, 0x1C0, 17), 229ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", 230ec97d23cSSam Shih netsys_500m_parents, 0x040, 0x044, 0x048, 16, 1, 231ec97d23cSSam Shih 23, 0x1C0, 18), 232ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", 233ec97d23cSSam Shih netsys_mcu_parents, 0x040, 0x044, 0x048, 24, 3, 31, 234ec97d23cSSam Shih 0x1C0, 19), 235ec97d23cSSam Shih /* CLK_CFG_5 */ 236ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", 237ec97d23cSSam Shih netsys_2x_parents, 0x050, 0x054, 0x058, 0, 2, 7, 238ec97d23cSSam Shih 0x1C0, 20), 239ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel", 240ec97d23cSSam Shih sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15, 241ec97d23cSSam Shih 0x1C0, 21), 242a0c3ef25SAngeloGioacchino Del Regno MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", 243a0c3ef25SAngeloGioacchino Del Regno sgm_reg_parents, 0x050, 0x054, 0x058, 244a0c3ef25SAngeloGioacchino Del Regno 16, 1, 23, 0x1C0, 22, 245a0c3ef25SAngeloGioacchino Del Regno CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 246ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 247ec97d23cSSam Shih 0x050, 0x054, 0x058, 24, 1, 31, 0x1C0, 23), 248ec97d23cSSam Shih /* CLK_CFG_6 */ 249ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_CONN_MCUSYS_SEL, "conn_mcusys_sel", 250ec97d23cSSam Shih conn_mcusys_parents, 0x060, 0x064, 0x068, 0, 1, 7, 251ec97d23cSSam Shih 0x1C0, 24), 252ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP_B_SEL, "eip_b_sel", eip_b_parents, 253ec97d23cSSam Shih 0x060, 0x064, 0x068, 8, 1, 15, 0x1C0, 25), 254ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_PCIE_PHY_SEL, "pcie_phy_sel", 255ec97d23cSSam Shih f_26m_adc_parents, 0x060, 0x064, 0x068, 16, 1, 23, 256ec97d23cSSam Shih 0x1C0, 26), 257ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_USB3_PHY_SEL, "usb3_phy_sel", 258ec97d23cSSam Shih f_26m_adc_parents, 0x060, 0x064, 0x068, 24, 1, 31, 259ec97d23cSSam Shih 0x1C0, 27), 260ec97d23cSSam Shih /* CLK_CFG_7 */ 261a0c3ef25SAngeloGioacchino Del Regno MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_F26M_SEL, "csw_f26m_sel", 262a0c3ef25SAngeloGioacchino Del Regno f_26m_adc_parents, 0x070, 0x074, 0x078, 263a0c3ef25SAngeloGioacchino Del Regno 0, 1, 7, 0x1C0, 28, 264a0c3ef25SAngeloGioacchino Del Regno CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 265ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 266ec97d23cSSam Shih 0x070, 0x074, 0x078, 8, 2, 15, 0x1C0, 29), 267ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", 268ec97d23cSSam Shih a_tuner_parents, 0x070, 0x074, 0x078, 16, 2, 23, 269ec97d23cSSam Shih 0x1C0, 30), 270ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SEL, "u2u3_sel", f_26m_adc_parents, 271ec97d23cSSam Shih 0x070, 0x074, 0x078, 24, 1, 31, 0x1C4, 0), 272ec97d23cSSam Shih /* CLK_CFG_8 */ 273ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel", 274ec97d23cSSam Shih u2u3_sys_parents, 0x080, 0x084, 0x088, 0, 1, 7, 275ec97d23cSSam Shih 0x1C4, 1), 276ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel", 277ec97d23cSSam Shih u2u3_sys_parents, 0x080, 0x084, 0x088, 8, 1, 15, 278ec97d23cSSam Shih 0x1C4, 2), 279ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_U2_REFSEL, "da_u2_refsel", 280ec97d23cSSam Shih da_u2_refsel_parents, 0x080, 0x084, 0x088, 16, 1, 281ec97d23cSSam Shih 23, 0x1C4, 3), 282ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_U2_CK_1P_SEL, "da_u2_ck_1p_sel", 283ec97d23cSSam Shih da_u2_refsel_parents, 0x080, 0x084, 0x088, 24, 1, 284ec97d23cSSam Shih 31, 0x1C4, 4), 285ec97d23cSSam Shih /* CLK_CFG_9 */ 286ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel", 287ec97d23cSSam Shih sgm_reg_parents, 0x090, 0x094, 0x098, 0, 1, 7, 288ec97d23cSSam Shih 0x1C4, 5), 289ec97d23cSSam Shih }; 290ec97d23cSSam Shih 2919d8d1fe5SAngeloGioacchino Del Regno static const struct mtk_clk_desc topck_desc = { 2929d8d1fe5SAngeloGioacchino Del Regno .fixed_clks = top_fixed_clks, 2939d8d1fe5SAngeloGioacchino Del Regno .num_fixed_clks = ARRAY_SIZE(top_fixed_clks), 2949d8d1fe5SAngeloGioacchino Del Regno .factor_clks = top_divs, 2959d8d1fe5SAngeloGioacchino Del Regno .num_factor_clks = ARRAY_SIZE(top_divs), 2969d8d1fe5SAngeloGioacchino Del Regno .mux_clks = top_muxes, 2979d8d1fe5SAngeloGioacchino Del Regno .num_mux_clks = ARRAY_SIZE(top_muxes), 2989d8d1fe5SAngeloGioacchino Del Regno .clk_lock = &mt7986_clk_lock, 2999d8d1fe5SAngeloGioacchino Del Regno }; 300ec97d23cSSam Shih 301ec97d23cSSam Shih static const struct of_device_id of_match_clk_mt7986_topckgen[] = { 3029d8d1fe5SAngeloGioacchino Del Regno { .compatible = "mediatek,mt7986-topckgen", .data = &topck_desc }, 3039d8d1fe5SAngeloGioacchino Del Regno { /* sentinel */ } 304ec97d23cSSam Shih }; 30565c9ad77SAngeloGioacchino Del Regno MODULE_DEVICE_TABLE(of, of_match_clk_mt7986_topckgen); 306ec97d23cSSam Shih 307ec97d23cSSam Shih static struct platform_driver clk_mt7986_topckgen_drv = { 3089d8d1fe5SAngeloGioacchino Del Regno .probe = mtk_clk_simple_probe, 30961ca6ee7SUwe Kleine-König .remove_new = mtk_clk_simple_remove, 310ec97d23cSSam Shih .driver = { 311ec97d23cSSam Shih .name = "clk-mt7986-topckgen", 312ec97d23cSSam Shih .of_match_table = of_match_clk_mt7986_topckgen, 313ec97d23cSSam Shih }, 314ec97d23cSSam Shih }; 315164d240dSAngeloGioacchino Del Regno module_platform_driver(clk_mt7986_topckgen_drv); 316a451da86SAngeloGioacchino Del Regno MODULE_LICENSE("GPL"); 317