1d46adccbSFabien Parent // SPDX-License-Identifier: GPL-2.0 2d46adccbSFabien Parent /* 3d46adccbSFabien Parent * Copyright (C) 2022 MediaTek Inc. 4905b7430SAngeloGioacchino Del Regno * Copyright (C) 2023 Collabora Ltd. 5905b7430SAngeloGioacchino Del Regno * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> 6d46adccbSFabien Parent */ 7d46adccbSFabien Parent 8d46adccbSFabien Parent #include <dt-bindings/clock/mediatek,mt8365-clk.h> 9d46adccbSFabien Parent #include <linux/clk.h> 10d46adccbSFabien Parent #include <linux/clk-provider.h> 11d46adccbSFabien Parent #include <linux/delay.h> 12d46adccbSFabien Parent #include <linux/mfd/syscon.h> 13*a96cbb14SRob Herring #include <linux/mod_devicetable.h> 14d46adccbSFabien Parent #include <linux/platform_device.h> 15d46adccbSFabien Parent #include <linux/slab.h> 16d46adccbSFabien Parent 17d46adccbSFabien Parent #include "clk-gate.h" 18d46adccbSFabien Parent #include "clk-mtk.h" 19d46adccbSFabien Parent #include "clk-mux.h" 20d46adccbSFabien Parent 21d46adccbSFabien Parent static DEFINE_SPINLOCK(mt8365_clk_lock); 22d46adccbSFabien Parent 23d46adccbSFabien Parent static const struct mtk_fixed_clk top_fixed_clks[] = { 243d6f6d2bSAlexandre Mergnat FIXED_CLK(CLK_TOP_CLK_NULL, "clk_null", NULL, 0), 25d46adccbSFabien Parent FIXED_CLK(CLK_TOP_I2S0_BCK, "i2s0_bck", NULL, 26000000), 26d46adccbSFabien Parent FIXED_CLK(CLK_TOP_DSI0_LNTC_DSICK, "dsi0_lntc_dsick", "clk26m", 27d46adccbSFabien Parent 75000000), 28d46adccbSFabien Parent FIXED_CLK(CLK_TOP_VPLL_DPIX, "vpll_dpix", "clk26m", 75000000), 29d46adccbSFabien Parent FIXED_CLK(CLK_TOP_LVDSTX_CLKDIG_CTS, "lvdstx_dig_cts", "clk26m", 30d46adccbSFabien Parent 52500000), 31d46adccbSFabien Parent }; 32d46adccbSFabien Parent 33d46adccbSFabien Parent static const struct mtk_fixed_factor top_divs[] = { 34d46adccbSFabien Parent FACTOR(CLK_TOP_SYS_26M_D2, "sys_26m_d2", "clk26m", 1, 2), 35d46adccbSFabien Parent FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2), 36d46adccbSFabien Parent FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "mainpll", 1, 4), 37d46adccbSFabien Parent FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "mainpll", 1, 8), 38d46adccbSFabien Parent FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "mainpll", 1, 16), 39d46adccbSFabien Parent FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "mainpll", 1, 32), 40d46adccbSFabien Parent FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 3), 41d46adccbSFabien Parent FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "mainpll", 1, 6), 42d46adccbSFabien Parent FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "mainpll", 1, 12), 43d46adccbSFabien Parent FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "mainpll", 1, 24), 44d46adccbSFabien Parent FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5), 45d46adccbSFabien Parent FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "mainpll", 1, 10), 46d46adccbSFabien Parent FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "mainpll", 1, 20), 47d46adccbSFabien Parent FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7), 48d46adccbSFabien Parent FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "mainpll", 1, 14), 49d46adccbSFabien Parent FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "mainpll", 1, 28), 50d46adccbSFabien Parent FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ_en", 1, 2), 51d46adccbSFabien Parent FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2), 52d46adccbSFabien Parent FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll", 1, 4), 53d46adccbSFabien Parent FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll", 1, 8), 54d46adccbSFabien Parent FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3), 55d46adccbSFabien Parent FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll", 1, 6), 56d46adccbSFabien Parent FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll", 1, 12), 57d46adccbSFabien Parent FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll", 1, 24), 58d46adccbSFabien Parent FACTOR(CLK_TOP_UNIVPLL2_D32, "univpll2_d32", "univpll", 1, 96), 59d46adccbSFabien Parent FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5), 60d46adccbSFabien Parent FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll", 1, 10), 61d46adccbSFabien Parent FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll", 1, 20), 62d46adccbSFabien Parent FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, 1), 63d46adccbSFabien Parent FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2), 64d46adccbSFabien Parent FACTOR(CLK_TOP_MFGPLL, "mfgpll_ck", "mfgpll", 1, 1), 65d46adccbSFabien Parent FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll", 1, 2), 66d46adccbSFabien Parent FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll", 1, 4), 67d46adccbSFabien Parent FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll", 1, 8), 68d46adccbSFabien Parent FACTOR(CLK_TOP_LVDSPLL_D16, "lvdspll_d16", "lvdspll", 1, 16), 69d46adccbSFabien Parent FACTOR(CLK_TOP_USB20_192M, "usb20_192m_ck", "usb20_en", 1, 13), 70d46adccbSFabien Parent FACTOR(CLK_TOP_USB20_192M_D4, "usb20_192m_d4", "usb20_192m_ck", 1, 4), 71d46adccbSFabien Parent FACTOR(CLK_TOP_USB20_192M_D8, "usb20_192m_d8", "usb20_192m_ck", 1, 8), 72d46adccbSFabien Parent FACTOR(CLK_TOP_USB20_192M_D16, "usb20_192m_d16", "usb20_192m_ck", 73d46adccbSFabien Parent 1, 16), 74d46adccbSFabien Parent FACTOR(CLK_TOP_USB20_192M_D32, "usb20_192m_d32", "usb20_192m_ck", 75d46adccbSFabien Parent 1, 32), 76d46adccbSFabien Parent FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1), 77d46adccbSFabien Parent FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1_ck", 1, 2), 78d46adccbSFabien Parent FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1_ck", 1, 4), 79d46adccbSFabien Parent FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1_ck", 1, 8), 80d46adccbSFabien Parent FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1), 81d46adccbSFabien Parent FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2_ck", 1, 2), 82d46adccbSFabien Parent FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2_ck", 1, 4), 83d46adccbSFabien Parent FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2_ck", 1, 8), 84d46adccbSFabien Parent FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1), 85d46adccbSFabien Parent FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2), 86d46adccbSFabien Parent FACTOR(CLK_TOP_DSPPLL, "dsppll_ck", "dsppll", 1, 1), 87d46adccbSFabien Parent FACTOR(CLK_TOP_DSPPLL_D2, "dsppll_d2", "dsppll", 1, 2), 88d46adccbSFabien Parent FACTOR(CLK_TOP_DSPPLL_D4, "dsppll_d4", "dsppll", 1, 4), 89d46adccbSFabien Parent FACTOR(CLK_TOP_DSPPLL_D8, "dsppll_d8", "dsppll", 1, 8), 90d46adccbSFabien Parent FACTOR(CLK_TOP_APUPLL, "apupll_ck", "apupll", 1, 1), 91d46adccbSFabien Parent FACTOR(CLK_TOP_CLK26M_D52, "clk26m_d52", "clk26m", 1, 52), 92d46adccbSFabien Parent }; 93d46adccbSFabien Parent 94d46adccbSFabien Parent static const char * const axi_parents[] = { 95d46adccbSFabien Parent "clk26m", 96d46adccbSFabien Parent "syspll_d7", 97d46adccbSFabien Parent "syspll1_d4", 98d46adccbSFabien Parent "syspll3_d2" 99d46adccbSFabien Parent }; 100d46adccbSFabien Parent 101d46adccbSFabien Parent static const char * const mem_parents[] = { 102d46adccbSFabien Parent "clk26m", 103d46adccbSFabien Parent "mmpll_ck", 104d46adccbSFabien Parent "syspll_d3", 105d46adccbSFabien Parent "syspll1_d2" 106d46adccbSFabien Parent }; 107d46adccbSFabien Parent 108d46adccbSFabien Parent static const char * const mm_parents[] = { 109d46adccbSFabien Parent "clk26m", 110d46adccbSFabien Parent "mmpll_ck", 111d46adccbSFabien Parent "syspll1_d2", 112d46adccbSFabien Parent "syspll_d5", 113d46adccbSFabien Parent "syspll1_d4", 114d46adccbSFabien Parent "univpll_d5", 115d46adccbSFabien Parent "univpll1_d2", 116d46adccbSFabien Parent "mmpll_d2" 117d46adccbSFabien Parent }; 118d46adccbSFabien Parent 119d46adccbSFabien Parent static const char * const scp_parents[] = { 120d46adccbSFabien Parent "clk26m", 121d46adccbSFabien Parent "syspll4_d2", 122d46adccbSFabien Parent "univpll2_d2", 123d46adccbSFabien Parent "syspll1_d2", 124d46adccbSFabien Parent "univpll1_d2", 125d46adccbSFabien Parent "syspll_d3", 126d46adccbSFabien Parent "univpll_d3" 127d46adccbSFabien Parent }; 128d46adccbSFabien Parent 129d46adccbSFabien Parent static const char * const mfg_parents[] = { 130d46adccbSFabien Parent "clk26m", 131d46adccbSFabien Parent "mfgpll_ck", 132d46adccbSFabien Parent "syspll_d3", 133d46adccbSFabien Parent "univpll_d3" 134d46adccbSFabien Parent }; 135d46adccbSFabien Parent 136d46adccbSFabien Parent static const char * const atb_parents[] = { 137d46adccbSFabien Parent "clk26m", 138d46adccbSFabien Parent "syspll1_d4", 139d46adccbSFabien Parent "syspll1_d2" 140d46adccbSFabien Parent }; 141d46adccbSFabien Parent 142d46adccbSFabien Parent static const char * const camtg_parents[] = { 143d46adccbSFabien Parent "clk26m", 144d46adccbSFabien Parent "usb20_192m_d8", 145d46adccbSFabien Parent "univpll2_d8", 146d46adccbSFabien Parent "usb20_192m_d4", 147d46adccbSFabien Parent "univpll2_d32", 148d46adccbSFabien Parent "usb20_192m_d16", 149d46adccbSFabien Parent "usb20_192m_d32" 150d46adccbSFabien Parent }; 151d46adccbSFabien Parent 152d46adccbSFabien Parent static const char * const uart_parents[] = { 153d46adccbSFabien Parent "clk26m", 154d46adccbSFabien Parent "univpll2_d8" 155d46adccbSFabien Parent }; 156d46adccbSFabien Parent 157d46adccbSFabien Parent static const char * const spi_parents[] = { 158d46adccbSFabien Parent "clk26m", 159d46adccbSFabien Parent "univpll2_d2", 160d46adccbSFabien Parent "univpll2_d4", 161d46adccbSFabien Parent "univpll2_d8" 162d46adccbSFabien Parent }; 163d46adccbSFabien Parent 164d46adccbSFabien Parent static const char * const msdc50_0_hc_parents[] = { 165d46adccbSFabien Parent "clk26m", 166d46adccbSFabien Parent "syspll1_d2", 167d46adccbSFabien Parent "univpll1_d4", 168d46adccbSFabien Parent "syspll2_d2" 169d46adccbSFabien Parent }; 170d46adccbSFabien Parent 171d46adccbSFabien Parent static const char * const msdc50_0_parents[] = { 172d46adccbSFabien Parent "clk26m", 173d46adccbSFabien Parent "msdcpll_ck", 174d46adccbSFabien Parent "univpll1_d2", 175d46adccbSFabien Parent "syspll1_d2", 176d46adccbSFabien Parent "univpll_d5", 177d46adccbSFabien Parent "syspll2_d2", 178d46adccbSFabien Parent "univpll1_d4", 179d46adccbSFabien Parent "syspll4_d2" 180d46adccbSFabien Parent }; 181d46adccbSFabien Parent 182d46adccbSFabien Parent static const char * const msdc50_2_parents[] = { 183d46adccbSFabien Parent "clk26m", 184d46adccbSFabien Parent "msdcpll_ck", 185d46adccbSFabien Parent "univpll_d3", 186d46adccbSFabien Parent "univpll1_d2", 187d46adccbSFabien Parent "syspll1_d2", 188d46adccbSFabien Parent "univpll2_d2", 189d46adccbSFabien Parent "syspll2_d2", 190d46adccbSFabien Parent "univpll1_d4" 191d46adccbSFabien Parent }; 192d46adccbSFabien Parent 193d46adccbSFabien Parent static const char * const msdc30_1_parents[] = { 194d46adccbSFabien Parent "clk26m", 195d46adccbSFabien Parent "msdcpll_d2", 196d46adccbSFabien Parent "univpll2_d2", 197d46adccbSFabien Parent "syspll2_d2", 198d46adccbSFabien Parent "univpll1_d4", 199d46adccbSFabien Parent "syspll1_d4", 200d46adccbSFabien Parent "syspll2_d4", 201d46adccbSFabien Parent "univpll2_d8" 202d46adccbSFabien Parent }; 203d46adccbSFabien Parent 204d46adccbSFabien Parent static const char * const audio_parents[] = { 205d46adccbSFabien Parent "clk26m", 206d46adccbSFabien Parent "syspll3_d4", 207d46adccbSFabien Parent "syspll4_d4", 208d46adccbSFabien Parent "syspll1_d16" 209d46adccbSFabien Parent }; 210d46adccbSFabien Parent 211d46adccbSFabien Parent static const char * const aud_intbus_parents[] = { 212d46adccbSFabien Parent "clk26m", 213d46adccbSFabien Parent "syspll1_d4", 214d46adccbSFabien Parent "syspll4_d2" 215d46adccbSFabien Parent }; 216d46adccbSFabien Parent 217d46adccbSFabien Parent static const char * const aud_1_parents[] = { 218d46adccbSFabien Parent "clk26m", 219d46adccbSFabien Parent "apll1_ck" 220d46adccbSFabien Parent }; 221d46adccbSFabien Parent 222d46adccbSFabien Parent static const char * const aud_2_parents[] = { 223d46adccbSFabien Parent "clk26m", 224d46adccbSFabien Parent "apll2_ck" 225d46adccbSFabien Parent }; 226d46adccbSFabien Parent 227d46adccbSFabien Parent static const char * const aud_engen1_parents[] = { 228d46adccbSFabien Parent "clk26m", 229d46adccbSFabien Parent "apll1_d2", 230d46adccbSFabien Parent "apll1_d4", 231d46adccbSFabien Parent "apll1_d8" 232d46adccbSFabien Parent }; 233d46adccbSFabien Parent 234d46adccbSFabien Parent static const char * const aud_engen2_parents[] = { 235d46adccbSFabien Parent "clk26m", 236d46adccbSFabien Parent "apll2_d2", 237d46adccbSFabien Parent "apll2_d4", 238d46adccbSFabien Parent "apll2_d8" 239d46adccbSFabien Parent }; 240d46adccbSFabien Parent 241d46adccbSFabien Parent static const char * const aud_spdif_parents[] = { 242d46adccbSFabien Parent "clk26m", 243d46adccbSFabien Parent "univpll_d2" 244d46adccbSFabien Parent }; 245d46adccbSFabien Parent 246d46adccbSFabien Parent static const char * const disp_pwm_parents[] = { 247d46adccbSFabien Parent "clk26m", 248d46adccbSFabien Parent "univpll2_d4" 249d46adccbSFabien Parent }; 250d46adccbSFabien Parent 251d46adccbSFabien Parent static const char * const dxcc_parents[] = { 252d46adccbSFabien Parent "clk26m", 253d46adccbSFabien Parent "syspll1_d2", 254d46adccbSFabien Parent "syspll1_d4", 255d46adccbSFabien Parent "syspll1_d8" 256d46adccbSFabien Parent }; 257d46adccbSFabien Parent 258d46adccbSFabien Parent static const char * const ssusb_sys_parents[] = { 259d46adccbSFabien Parent "clk26m", 260d46adccbSFabien Parent "univpll3_d4", 261d46adccbSFabien Parent "univpll2_d4", 262d46adccbSFabien Parent "univpll3_d2" 263d46adccbSFabien Parent }; 264d46adccbSFabien Parent 265d46adccbSFabien Parent static const char * const spm_parents[] = { 266d46adccbSFabien Parent "clk26m", 267d46adccbSFabien Parent "syspll1_d8" 268d46adccbSFabien Parent }; 269d46adccbSFabien Parent 270d46adccbSFabien Parent static const char * const i2c_parents[] = { 271d46adccbSFabien Parent "clk26m", 272d46adccbSFabien Parent "univpll3_d4", 273d46adccbSFabien Parent "univpll3_d2", 274d46adccbSFabien Parent "syspll1_d8", 275d46adccbSFabien Parent "syspll2_d8" 276d46adccbSFabien Parent }; 277d46adccbSFabien Parent 278d46adccbSFabien Parent static const char * const pwm_parents[] = { 279d46adccbSFabien Parent "clk26m", 280d46adccbSFabien Parent "univpll3_d4", 281d46adccbSFabien Parent "syspll1_d8" 282d46adccbSFabien Parent }; 283d46adccbSFabien Parent 284d46adccbSFabien Parent static const char * const senif_parents[] = { 285d46adccbSFabien Parent "clk26m", 286d46adccbSFabien Parent "univpll1_d4", 287d46adccbSFabien Parent "univpll1_d2", 288d46adccbSFabien Parent "univpll2_d2" 289d46adccbSFabien Parent }; 290d46adccbSFabien Parent 291d46adccbSFabien Parent static const char * const aes_fde_parents[] = { 292d46adccbSFabien Parent "clk26m", 293d46adccbSFabien Parent "msdcpll_ck", 294d46adccbSFabien Parent "univpll_d3", 295d46adccbSFabien Parent "univpll2_d2", 296d46adccbSFabien Parent "univpll1_d2", 297d46adccbSFabien Parent "syspll1_d2" 298d46adccbSFabien Parent }; 299d46adccbSFabien Parent 300d46adccbSFabien Parent static const char * const dpi0_parents[] = { 301d46adccbSFabien Parent "clk26m", 302d46adccbSFabien Parent "lvdspll_d2", 303d46adccbSFabien Parent "lvdspll_d4", 304d46adccbSFabien Parent "lvdspll_d8", 305d46adccbSFabien Parent "lvdspll_d16" 306d46adccbSFabien Parent }; 307d46adccbSFabien Parent 308d46adccbSFabien Parent static const char * const dsp_parents[] = { 309d46adccbSFabien Parent "clk26m", 310d46adccbSFabien Parent "sys_26m_d2", 311d46adccbSFabien Parent "dsppll_ck", 312d46adccbSFabien Parent "dsppll_d2", 313d46adccbSFabien Parent "dsppll_d4", 314d46adccbSFabien Parent "dsppll_d8" 315d46adccbSFabien Parent }; 316d46adccbSFabien Parent 317d46adccbSFabien Parent static const char * const nfi2x_parents[] = { 318d46adccbSFabien Parent "clk26m", 319d46adccbSFabien Parent "syspll2_d2", 320d46adccbSFabien Parent "syspll_d7", 321d46adccbSFabien Parent "syspll_d3", 322d46adccbSFabien Parent "syspll2_d4", 323d46adccbSFabien Parent "msdcpll_d2", 324d46adccbSFabien Parent "univpll1_d2", 325d46adccbSFabien Parent "univpll_d5" 326d46adccbSFabien Parent }; 327d46adccbSFabien Parent 328d46adccbSFabien Parent static const char * const nfiecc_parents[] = { 329d46adccbSFabien Parent "clk26m", 330d46adccbSFabien Parent "syspll4_d2", 331d46adccbSFabien Parent "univpll2_d4", 332d46adccbSFabien Parent "syspll_d7", 333d46adccbSFabien Parent "univpll1_d2", 334d46adccbSFabien Parent "syspll1_d2", 335d46adccbSFabien Parent "univpll2_d2", 336d46adccbSFabien Parent "syspll_d5" 337d46adccbSFabien Parent }; 338d46adccbSFabien Parent 339d46adccbSFabien Parent static const char * const ecc_parents[] = { 340d46adccbSFabien Parent "clk26m", 341d46adccbSFabien Parent "univpll2_d2", 342d46adccbSFabien Parent "univpll1_d2", 343d46adccbSFabien Parent "univpll_d3", 344d46adccbSFabien Parent "syspll_d2" 345d46adccbSFabien Parent }; 346d46adccbSFabien Parent 347d46adccbSFabien Parent static const char * const eth_parents[] = { 348d46adccbSFabien Parent "clk26m", 349d46adccbSFabien Parent "univpll2_d8", 350d46adccbSFabien Parent "syspll4_d4", 351d46adccbSFabien Parent "syspll1_d8", 352d46adccbSFabien Parent "syspll4_d2" 353d46adccbSFabien Parent }; 354d46adccbSFabien Parent 355d46adccbSFabien Parent static const char * const gcpu_parents[] = { 356d46adccbSFabien Parent "clk26m", 357d46adccbSFabien Parent "univpll_d3", 358d46adccbSFabien Parent "univpll2_d2", 359d46adccbSFabien Parent "syspll_d3", 360d46adccbSFabien Parent "syspll2_d2" 361d46adccbSFabien Parent }; 362d46adccbSFabien Parent 363d46adccbSFabien Parent static const char * const gcpu_cpm_parents[] = { 364d46adccbSFabien Parent "clk26m", 365d46adccbSFabien Parent "univpll2_d2", 366d46adccbSFabien Parent "syspll2_d2" 367d46adccbSFabien Parent }; 368d46adccbSFabien Parent 369d46adccbSFabien Parent static const char * const apu_parents[] = { 370d46adccbSFabien Parent "clk26m", 371d46adccbSFabien Parent "univpll_d2", 372d46adccbSFabien Parent "apupll_ck", 373d46adccbSFabien Parent "mmpll_ck", 374d46adccbSFabien Parent "syspll_d3", 375d46adccbSFabien Parent "univpll1_d2", 376d46adccbSFabien Parent "syspll1_d2", 377d46adccbSFabien Parent "syspll1_d4" 378d46adccbSFabien Parent }; 379d46adccbSFabien Parent 380d46adccbSFabien Parent static const char * const mbist_diag_parents[] = { 381d46adccbSFabien Parent "clk26m", 382d46adccbSFabien Parent "syspll4_d4", 383d46adccbSFabien Parent "univpll2_d8" 384d46adccbSFabien Parent }; 385d46adccbSFabien Parent 386ff962100SAngeloGioacchino Del Regno static const char * const apll_i2s_parents[] = { 387d46adccbSFabien Parent "aud_1_sel", 388d46adccbSFabien Parent "aud_2_sel" 389d46adccbSFabien Parent }; 390d46adccbSFabien Parent 391ff962100SAngeloGioacchino Del Regno static struct mtk_composite top_misc_muxes[] = { 392d46adccbSFabien Parent /* CLK_CFG_11 */ 393d46adccbSFabien Parent MUX_GATE(CLK_TOP_MBIST_DIAG_SEL, "mbist_diag_sel", mbist_diag_parents, 394d46adccbSFabien Parent 0x0ec, 0, 2, 7), 395ff962100SAngeloGioacchino Del Regno /* Audio MUX */ 396ff962100SAngeloGioacchino Del Regno MUX(CLK_TOP_APLL_I2S0_SEL, "apll_i2s0_sel", apll_i2s_parents, 0x0320, 11, 1), 397ff962100SAngeloGioacchino Del Regno MUX(CLK_TOP_APLL_I2S1_SEL, "apll_i2s1_sel", apll_i2s_parents, 0x0320, 12, 1), 398ff962100SAngeloGioacchino Del Regno MUX(CLK_TOP_APLL_I2S2_SEL, "apll_i2s2_sel", apll_i2s_parents, 0x0320, 13, 1), 399ff962100SAngeloGioacchino Del Regno MUX(CLK_TOP_APLL_I2S3_SEL, "apll_i2s3_sel", apll_i2s_parents, 0x0320, 14, 1), 400ff962100SAngeloGioacchino Del Regno MUX(CLK_TOP_APLL_TDMOUT_SEL, "apll_tdmout_sel", apll_i2s_parents, 0x0320, 15, 1), 401ff962100SAngeloGioacchino Del Regno MUX(CLK_TOP_APLL_TDMIN_SEL, "apll_tdmin_sel", apll_i2s_parents, 0x0320, 16, 1), 402ff962100SAngeloGioacchino Del Regno MUX(CLK_TOP_APLL_SPDIF_SEL, "apll_spdif_sel", apll_i2s_parents, 0x0320, 17, 1), 403d46adccbSFabien Parent }; 404d46adccbSFabien Parent 405d46adccbSFabien Parent #define CLK_CFG_UPDATE 0x004 406d46adccbSFabien Parent #define CLK_CFG_UPDATE1 0x008 407d46adccbSFabien Parent 408d46adccbSFabien Parent static const struct mtk_mux top_muxes[] = { 409d46adccbSFabien Parent /* CLK_CFG_0 */ 410d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 411d46adccbSFabien Parent 0x040, 0x044, 0x048, 0, 2, 7, CLK_CFG_UPDATE, 4121775790eSAngeloGioacchino Del Regno 0, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 413d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x040, 414d46adccbSFabien Parent 0x044, 0x048, 8, 2, 15, CLK_CFG_UPDATE, 1), 415d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x040, 0x044, 416d46adccbSFabien Parent 0x048, 16, 3, 23, CLK_CFG_UPDATE, 2), 417d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, 0x040, 418d46adccbSFabien Parent 0x044, 0x048, 24, 3, 31, CLK_CFG_UPDATE, 3), 419d46adccbSFabien Parent /* CLK_CFG_1 */ 420d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x050, 421d46adccbSFabien Parent 0x054, 0x058, 0, 2, 7, CLK_CFG_UPDATE, 4), 422d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, 0x050, 423d46adccbSFabien Parent 0x054, 0x058, 8, 2, 15, CLK_CFG_UPDATE, 5), 424d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents, 425d46adccbSFabien Parent 0x050, 0x054, 0x058, 16, 3, 23, CLK_CFG_UPDATE, 6), 426d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG1_SEL, "camtg1_sel", camtg_parents, 427d46adccbSFabien Parent 0x050, 0x054, 0x058, 24, 3, 31, CLK_CFG_UPDATE, 7), 428d46adccbSFabien Parent /* CLK_CFG_2 */ 429d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x060, 430d46adccbSFabien Parent 0x064, 0x068, 0, 1, 7, CLK_CFG_UPDATE, 8), 431d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x060, 432d46adccbSFabien Parent 0x064, 0x068, 8, 2, 15, CLK_CFG_UPDATE, 9), 433f235f6aeSAngeloGioacchino Del Regno MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_HC_SEL, "msdc50_0_hc_sel", 434d46adccbSFabien Parent msdc50_0_hc_parents, 0x060, 0x064, 0x068, 16, 2, 435f235f6aeSAngeloGioacchino Del Regno 23, CLK_CFG_UPDATE, 10, 0), 436f235f6aeSAngeloGioacchino Del Regno MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC2_2_HC_SEL, "msdc2_2_hc_sel", 437d46adccbSFabien Parent msdc50_0_hc_parents, 0x060, 0x064, 0x068, 24, 2, 438f235f6aeSAngeloGioacchino Del Regno 31, CLK_CFG_UPDATE, 11, 0), 439d46adccbSFabien Parent /* CLK_CFG_3 */ 440f235f6aeSAngeloGioacchino Del Regno MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", 441d46adccbSFabien Parent msdc50_0_parents, 0x070, 0x074, 0x078, 0, 3, 7, 442f235f6aeSAngeloGioacchino Del Regno CLK_CFG_UPDATE, 12, 0), 443f235f6aeSAngeloGioacchino Del Regno MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_2_SEL, "msdc50_2_sel", 444d46adccbSFabien Parent msdc50_2_parents, 0x070, 0x074, 0x078, 8, 3, 15, 445f235f6aeSAngeloGioacchino Del Regno CLK_CFG_UPDATE, 13, 0), 446f235f6aeSAngeloGioacchino Del Regno MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", 447d46adccbSFabien Parent msdc30_1_parents, 0x070, 0x074, 0x078, 16, 3, 23, 448f235f6aeSAngeloGioacchino Del Regno CLK_CFG_UPDATE, 14, 0), 449d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents, 450d46adccbSFabien Parent 0x070, 0x074, 0x078, 24, 2, 31, CLK_CFG_UPDATE, 451d46adccbSFabien Parent 15), 452d46adccbSFabien Parent /* CLK_CFG_4 */ 453d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", 454d46adccbSFabien Parent aud_intbus_parents, 0x080, 0x084, 0x088, 0, 2, 7, 455d46adccbSFabien Parent CLK_CFG_UPDATE, 16), 456d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents, 457d46adccbSFabien Parent 0x080, 0x084, 0x088, 8, 1, 15, CLK_CFG_UPDATE, 17), 458d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_2_SEL, "aud_2_sel", aud_2_parents, 459d46adccbSFabien Parent 0x080, 0x084, 0x088, 16, 1, 23, CLK_CFG_UPDATE, 460d46adccbSFabien Parent 18), 461d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel", 462d46adccbSFabien Parent aud_engen1_parents, 0x080, 0x084, 0x088, 24, 2, 31, 463d46adccbSFabien Parent CLK_CFG_UPDATE, 19), 464d46adccbSFabien Parent /* CLK_CFG_5 */ 465d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN2_SEL, "aud_engen2_sel", 466d46adccbSFabien Parent aud_engen2_parents, 0x090, 0x094, 0x098, 0, 2, 7, 467d46adccbSFabien Parent CLK_CFG_UPDATE, 20), 468d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_SPDIF_SEL, "aud_spdif_sel", 469d46adccbSFabien Parent aud_spdif_parents, 0x090, 0x094, 0x098, 8, 1, 15, 470d46adccbSFabien Parent CLK_CFG_UPDATE, 21), 471d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM_SEL, "disp_pwm_sel", 472d46adccbSFabien Parent disp_pwm_parents, 0x090, 0x094, 0x098, 16, 2, 23, 473d46adccbSFabien Parent CLK_CFG_UPDATE, 22), 474d46adccbSFabien Parent /* CLK_CFG_6 */ 475d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DXCC_SEL, "dxcc_sel", dxcc_parents, 476d46adccbSFabien Parent 0x0a0, 0x0a4, 0x0a8, 0, 2, 7, CLK_CFG_UPDATE, 4771775790eSAngeloGioacchino Del Regno 24, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 478d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_SYS_SEL, "ssusb_sys_sel", 479d46adccbSFabien Parent ssusb_sys_parents, 0x0a0, 0x0a4, 0x0a8, 8, 2, 15, 480d46adccbSFabien Parent CLK_CFG_UPDATE, 25), 481d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_SEL, "ssusb_xhci_sel", 482d46adccbSFabien Parent ssusb_sys_parents, 0x0a0, 0x0a4, 0x0a8, 16, 2, 23, 483d46adccbSFabien Parent CLK_CFG_UPDATE, 26), 484d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM_SEL, "spm_sel", spm_parents, 4851775790eSAngeloGioacchino Del Regno 0x0a0, 0x0a4, 0x0a8, 24, 1, 31, CLK_CFG_UPDATE, 4861775790eSAngeloGioacchino Del Regno 27, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 487d46adccbSFabien Parent /* CLK_CFG_7 */ 488d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x0b0, 489d46adccbSFabien Parent 0x0b4, 0x0b8, 0, 3, 7, CLK_CFG_UPDATE, 28), 490d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x0b0, 491d46adccbSFabien Parent 0x0b4, 0x0b8, 8, 2, 15, CLK_CFG_UPDATE, 29), 492d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_SENIF_SEL, "senif_sel", senif_parents, 493d46adccbSFabien Parent 0x0b0, 0x0b4, 0x0b8, 16, 2, 23, CLK_CFG_UPDATE, 494d46adccbSFabien Parent 30), 495d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_FDE_SEL, "aes_fde_sel", 496d46adccbSFabien Parent aes_fde_parents, 0x0b0, 0x0b4, 0x0b8, 24, 3, 31, 497d46adccbSFabien Parent CLK_CFG_UPDATE, 31), 498d46adccbSFabien Parent /* CLK_CFG_8 */ 499d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM_SEL, "camtm_sel", senif_parents, 500d46adccbSFabien Parent 0x0c0, 0x0c4, 0x0c8, 0, 2, 7, CLK_CFG_UPDATE1, 0), 501d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents, 0x0c0, 502d46adccbSFabien Parent 0x0c4, 0x0c8, 8, 3, 15, CLK_CFG_UPDATE1, 1), 503d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi0_parents, 0x0c0, 504d46adccbSFabien Parent 0x0c4, 0x0c8, 16, 3, 23, CLK_CFG_UPDATE1, 2), 505d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP_SEL, "dsp_sel", dsp_parents, 0x0c0, 506d46adccbSFabien Parent 0x0c4, 0x0c8, 24, 3, 31, CLK_CFG_UPDATE1, 3), 507d46adccbSFabien Parent /* CLK_CFG_9 */ 508d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI2X_SEL, "nfi2x_sel", nfi2x_parents, 509d46adccbSFabien Parent 0x0d0, 0x0d4, 0x0d8, 0, 3, 7, CLK_CFG_UPDATE1, 4), 510d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_NFIECC_SEL, "nfiecc_sel", nfiecc_parents, 511d46adccbSFabien Parent 0x0d0, 0x0d4, 0x0d8, 8, 3, 15, CLK_CFG_UPDATE1, 5), 512d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_ECC_SEL, "ecc_sel", ecc_parents, 0x0d0, 513d46adccbSFabien Parent 0x0d4, 0x0d8, 16, 3, 23, CLK_CFG_UPDATE1, 6), 514d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SEL, "eth_sel", eth_parents, 0x0d0, 515d46adccbSFabien Parent 0x0d4, 0x0d8, 24, 3, 31, CLK_CFG_UPDATE1, 7), 516d46adccbSFabien Parent /* CLK_CFG_10 */ 517d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_GCPU_SEL, "gcpu_sel", gcpu_parents, 0x0e0, 518d46adccbSFabien Parent 0x0e4, 0x0e8, 0, 3, 7, CLK_CFG_UPDATE1, 8), 519d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_GCPU_CPM_SEL, "gcpu_cpm_sel", 520d46adccbSFabien Parent gcpu_cpm_parents, 0x0e0, 0x0e4, 0x0e8, 8, 2, 15, 521d46adccbSFabien Parent CLK_CFG_UPDATE1, 9), 522d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_APU_SEL, "apu_sel", apu_parents, 0x0e0, 523d46adccbSFabien Parent 0x0e4, 0x0e8, 16, 3, 23, CLK_CFG_UPDATE1, 10), 524d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_APU_IF_SEL, "apu_if_sel", apu_parents, 525d46adccbSFabien Parent 0x0e0, 0x0e4, 0x0e8, 24, 3, 31, CLK_CFG_UPDATE1, 526d46adccbSFabien Parent 11), 527d46adccbSFabien Parent }; 528d46adccbSFabien Parent 529d46adccbSFabien Parent static const char * const mcu_bus_parents[] = { 530d46adccbSFabien Parent "clk26m", 531d46adccbSFabien Parent "armpll", 532d46adccbSFabien Parent "mainpll", 533d46adccbSFabien Parent "univpll_d2" 534d46adccbSFabien Parent }; 535d46adccbSFabien Parent 536d46adccbSFabien Parent static struct mtk_composite mcu_muxes[] = { 537d46adccbSFabien Parent /* bus_pll_divider_cfg */ 538d46adccbSFabien Parent MUX_GATE_FLAGS(CLK_MCU_BUS_SEL, "mcu_bus_sel", mcu_bus_parents, 0x7C0, 539d46adccbSFabien Parent 9, 2, -1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL), 540d46adccbSFabien Parent }; 541d46adccbSFabien Parent 542d46adccbSFabien Parent #define DIV_ADJ_F(_id, _name, _parent, _reg, _shift, _width, _flags) { \ 543d46adccbSFabien Parent .id = _id, \ 544d46adccbSFabien Parent .name = _name, \ 545d46adccbSFabien Parent .parent_name = _parent, \ 546d46adccbSFabien Parent .div_reg = _reg, \ 547d46adccbSFabien Parent .div_shift = _shift, \ 548d46adccbSFabien Parent .div_width = _width, \ 549d46adccbSFabien Parent .clk_divider_flags = _flags, \ 550d46adccbSFabien Parent } 551d46adccbSFabien Parent 552d46adccbSFabien Parent static const struct mtk_clk_divider top_adj_divs[] = { 553d46adccbSFabien Parent DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV0, "apll12_ck_div0", "apll_i2s0_sel", 554d46adccbSFabien Parent 0x324, 0, 8, CLK_DIVIDER_ROUND_CLOSEST), 555d46adccbSFabien Parent DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV1, "apll12_ck_div1", "apll_i2s1_sel", 556d46adccbSFabien Parent 0x324, 8, 8, CLK_DIVIDER_ROUND_CLOSEST), 557d46adccbSFabien Parent DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV2, "apll12_ck_div2", "apll_i2s2_sel", 558d46adccbSFabien Parent 0x324, 16, 8, CLK_DIVIDER_ROUND_CLOSEST), 559d46adccbSFabien Parent DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV3, "apll12_ck_div3", "apll_i2s3_sel", 560d46adccbSFabien Parent 0x324, 24, 8, CLK_DIVIDER_ROUND_CLOSEST), 5613d6f6d2bSAlexandre Mergnat DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV4, "apll12_ck_div4", "apll_tdmout_sel", 5623d6f6d2bSAlexandre Mergnat 0x328, 0, 8, CLK_DIVIDER_ROUND_CLOSEST), 5633d6f6d2bSAlexandre Mergnat DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV4B, "apll12_ck_div4b", "apll_tdmout_sel", 5643d6f6d2bSAlexandre Mergnat 0x328, 8, 8, CLK_DIVIDER_ROUND_CLOSEST), 5653d6f6d2bSAlexandre Mergnat DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV5, "apll12_ck_div5", "apll_tdmin_sel", 5663d6f6d2bSAlexandre Mergnat 0x328, 16, 8, CLK_DIVIDER_ROUND_CLOSEST), 5673d6f6d2bSAlexandre Mergnat DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV5B, "apll12_ck_div5b", "apll_tdmin_sel", 5683d6f6d2bSAlexandre Mergnat 0x328, 24, 8, CLK_DIVIDER_ROUND_CLOSEST), 569d46adccbSFabien Parent DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV6, "apll12_ck_div6", "apll_spdif_sel", 570d46adccbSFabien Parent 0x32c, 0, 8, CLK_DIVIDER_ROUND_CLOSEST), 571d46adccbSFabien Parent }; 572d46adccbSFabien Parent 573905b7430SAngeloGioacchino Del Regno static const struct mtk_gate_regs top0_cg_regs = { 574905b7430SAngeloGioacchino Del Regno .set_ofs = 0, 575905b7430SAngeloGioacchino Del Regno .clr_ofs = 0, 576905b7430SAngeloGioacchino Del Regno .sta_ofs = 0, 577d46adccbSFabien Parent }; 578d46adccbSFabien Parent 579905b7430SAngeloGioacchino Del Regno static const struct mtk_gate_regs top1_cg_regs = { 580905b7430SAngeloGioacchino Del Regno .set_ofs = 0x104, 581905b7430SAngeloGioacchino Del Regno .clr_ofs = 0x104, 582905b7430SAngeloGioacchino Del Regno .sta_ofs = 0x104, 583905b7430SAngeloGioacchino Del Regno }; 584905b7430SAngeloGioacchino Del Regno 585905b7430SAngeloGioacchino Del Regno static const struct mtk_gate_regs top2_cg_regs = { 586905b7430SAngeloGioacchino Del Regno .set_ofs = 0x320, 587905b7430SAngeloGioacchino Del Regno .clr_ofs = 0x320, 588905b7430SAngeloGioacchino Del Regno .sta_ofs = 0x320, 589905b7430SAngeloGioacchino Del Regno }; 590905b7430SAngeloGioacchino Del Regno 591905b7430SAngeloGioacchino Del Regno #define GATE_TOP0(_id, _name, _parent, _shift) \ 592905b7430SAngeloGioacchino Del Regno GATE_MTK(_id, _name, _parent, &top0_cg_regs, \ 593a1043fbcSMarkus Schneider-Pargmann _shift, &mtk_clk_gate_ops_no_setclr) 594905b7430SAngeloGioacchino Del Regno 595905b7430SAngeloGioacchino Del Regno #define GATE_TOP1(_id, _name, _parent, _shift) \ 596905b7430SAngeloGioacchino Del Regno GATE_MTK(_id, _name, _parent, &top1_cg_regs, \ 597a1043fbcSMarkus Schneider-Pargmann _shift, &mtk_clk_gate_ops_no_setclr_inv) 598905b7430SAngeloGioacchino Del Regno 599905b7430SAngeloGioacchino Del Regno #define GATE_TOP2(_id, _name, _parent, _shift) \ 600905b7430SAngeloGioacchino Del Regno GATE_MTK(_id, _name, _parent, &top2_cg_regs, \ 601a1043fbcSMarkus Schneider-Pargmann _shift, &mtk_clk_gate_ops_no_setclr_inv) 602905b7430SAngeloGioacchino Del Regno 603905b7430SAngeloGioacchino Del Regno static const struct mtk_gate top_clk_gates[] = { 604905b7430SAngeloGioacchino Del Regno GATE_TOP0(CLK_TOP_CONN_32K, "conn_32k", "clk32k", 10), 605905b7430SAngeloGioacchino Del Regno GATE_TOP0(CLK_TOP_CONN_26M, "conn_26m", "clk26m", 11), 606905b7430SAngeloGioacchino Del Regno GATE_TOP0(CLK_TOP_DSP_32K, "dsp_32k", "clk32k", 16), 607905b7430SAngeloGioacchino Del Regno GATE_TOP0(CLK_TOP_DSP_26M, "dsp_26m", "clk26m", 17), 608905b7430SAngeloGioacchino Del Regno GATE_TOP1(CLK_TOP_USB20_48M_EN, "usb20_48m_en", "usb20_192m_d4", 8), 609905b7430SAngeloGioacchino Del Regno GATE_TOP1(CLK_TOP_UNIVPLL_48M_EN, "univpll_48m_en", "usb20_192m_d4", 9), 610905b7430SAngeloGioacchino Del Regno GATE_TOP1(CLK_TOP_LVDSTX_CLKDIG_EN, "lvdstx_dig_en", "lvdstx_dig_cts", 20), 611905b7430SAngeloGioacchino Del Regno GATE_TOP1(CLK_TOP_VPLL_DPIX_EN, "vpll_dpix_en", "vpll_dpix", 21), 612905b7430SAngeloGioacchino Del Regno GATE_TOP1(CLK_TOP_SSUSB_TOP_CK_EN, "ssusb_top_ck_en", NULL, 22), 613905b7430SAngeloGioacchino Del Regno GATE_TOP1(CLK_TOP_SSUSB_PHY_CK_EN, "ssusb_phy_ck_en", NULL, 23), 614905b7430SAngeloGioacchino Del Regno GATE_TOP2(CLK_TOP_AUD_I2S0_M, "aud_i2s0_m_ck", "apll12_ck_div0", 0), 615905b7430SAngeloGioacchino Del Regno GATE_TOP2(CLK_TOP_AUD_I2S1_M, "aud_i2s1_m_ck", "apll12_ck_div1", 1), 616905b7430SAngeloGioacchino Del Regno GATE_TOP2(CLK_TOP_AUD_I2S2_M, "aud_i2s2_m_ck", "apll12_ck_div2", 2), 617905b7430SAngeloGioacchino Del Regno GATE_TOP2(CLK_TOP_AUD_I2S3_M, "aud_i2s3_m_ck", "apll12_ck_div3", 3), 618905b7430SAngeloGioacchino Del Regno GATE_TOP2(CLK_TOP_AUD_TDMOUT_M, "aud_tdmout_m_ck", "apll12_ck_div4", 4), 619905b7430SAngeloGioacchino Del Regno GATE_TOP2(CLK_TOP_AUD_TDMOUT_B, "aud_tdmout_b_ck", "apll12_ck_div4b", 5), 620905b7430SAngeloGioacchino Del Regno GATE_TOP2(CLK_TOP_AUD_TDMIN_M, "aud_tdmin_m_ck", "apll12_ck_div5", 6), 621905b7430SAngeloGioacchino Del Regno GATE_TOP2(CLK_TOP_AUD_TDMIN_B, "aud_tdmin_b_ck", "apll12_ck_div5b", 7), 622905b7430SAngeloGioacchino Del Regno GATE_TOP2(CLK_TOP_AUD_SPDIF_M, "aud_spdif_m_ck", "apll12_ck_div6", 8), 623d46adccbSFabien Parent }; 624d46adccbSFabien Parent 625d46adccbSFabien Parent static const struct mtk_gate_regs ifr2_cg_regs = { 626d46adccbSFabien Parent .set_ofs = 0x80, 627d46adccbSFabien Parent .clr_ofs = 0x84, 628d46adccbSFabien Parent .sta_ofs = 0x90, 629d46adccbSFabien Parent }; 630d46adccbSFabien Parent 631d46adccbSFabien Parent static const struct mtk_gate_regs ifr3_cg_regs = { 632d46adccbSFabien Parent .set_ofs = 0x88, 633d46adccbSFabien Parent .clr_ofs = 0x8c, 634d46adccbSFabien Parent .sta_ofs = 0x94, 635d46adccbSFabien Parent }; 636d46adccbSFabien Parent 637d46adccbSFabien Parent static const struct mtk_gate_regs ifr4_cg_regs = { 638d46adccbSFabien Parent .set_ofs = 0xa4, 639d46adccbSFabien Parent .clr_ofs = 0xa8, 640d46adccbSFabien Parent .sta_ofs = 0xac, 641d46adccbSFabien Parent }; 642d46adccbSFabien Parent 643d46adccbSFabien Parent static const struct mtk_gate_regs ifr5_cg_regs = { 644d46adccbSFabien Parent .set_ofs = 0xc0, 645d46adccbSFabien Parent .clr_ofs = 0xc4, 646d46adccbSFabien Parent .sta_ofs = 0xc8, 647d46adccbSFabien Parent }; 648d46adccbSFabien Parent 649d46adccbSFabien Parent static const struct mtk_gate_regs ifr6_cg_regs = { 650d46adccbSFabien Parent .set_ofs = 0xd0, 651d46adccbSFabien Parent .clr_ofs = 0xd4, 652d46adccbSFabien Parent .sta_ofs = 0xd8, 653d46adccbSFabien Parent }; 654d46adccbSFabien Parent 655905b7430SAngeloGioacchino Del Regno #define GATE_IFRX(_id, _name, _parent, _shift, _regs) \ 656905b7430SAngeloGioacchino Del Regno GATE_MTK(_id, _name, _parent, _regs, _shift, \ 657905b7430SAngeloGioacchino Del Regno &mtk_clk_gate_ops_setclr) 658d46adccbSFabien Parent 659905b7430SAngeloGioacchino Del Regno #define GATE_IFR2(_id, _name, _parent, _shift) \ 660905b7430SAngeloGioacchino Del Regno GATE_IFRX(_id, _name, _parent, _shift, &ifr2_cg_regs) 661d46adccbSFabien Parent 662905b7430SAngeloGioacchino Del Regno #define GATE_IFR3(_id, _name, _parent, _shift) \ 663905b7430SAngeloGioacchino Del Regno GATE_IFRX(_id, _name, _parent, _shift, &ifr3_cg_regs) 664d46adccbSFabien Parent 665905b7430SAngeloGioacchino Del Regno #define GATE_IFR4(_id, _name, _parent, _shift) \ 666905b7430SAngeloGioacchino Del Regno GATE_IFRX(_id, _name, _parent, _shift, &ifr4_cg_regs) 667d46adccbSFabien Parent 668905b7430SAngeloGioacchino Del Regno #define GATE_IFR5(_id, _name, _parent, _shift) \ 669905b7430SAngeloGioacchino Del Regno GATE_IFRX(_id, _name, _parent, _shift, &ifr5_cg_regs) 670905b7430SAngeloGioacchino Del Regno 671905b7430SAngeloGioacchino Del Regno #define GATE_IFR6(_id, _name, _parent, _shift) \ 672905b7430SAngeloGioacchino Del Regno GATE_IFRX(_id, _name, _parent, _shift, &ifr6_cg_regs) 673d46adccbSFabien Parent 674d46adccbSFabien Parent static const struct mtk_gate ifr_clks[] = { 675d46adccbSFabien Parent /* IFR2 */ 676d46adccbSFabien Parent GATE_IFR2(CLK_IFR_PMIC_TMR, "ifr_pmic_tmr", "clk26m", 0), 677d46adccbSFabien Parent GATE_IFR2(CLK_IFR_PMIC_AP, "ifr_pmic_ap", "clk26m", 1), 678d46adccbSFabien Parent GATE_IFR2(CLK_IFR_PMIC_MD, "ifr_pmic_md", "clk26m", 2), 679d46adccbSFabien Parent GATE_IFR2(CLK_IFR_PMIC_CONN, "ifr_pmic_conn", "clk26m", 3), 680d46adccbSFabien Parent GATE_IFR2(CLK_IFR_ICUSB, "ifr_icusb", "axi_sel", 8), 681d46adccbSFabien Parent GATE_IFR2(CLK_IFR_GCE, "ifr_gce", "axi_sel", 9), 682d46adccbSFabien Parent GATE_IFR2(CLK_IFR_THERM, "ifr_therm", "axi_sel", 10), 683d46adccbSFabien Parent GATE_IFR2(CLK_IFR_PWM_HCLK, "ifr_pwm_hclk", "axi_sel", 15), 684d46adccbSFabien Parent GATE_IFR2(CLK_IFR_PWM1, "ifr_pwm1", "pwm_sel", 16), 685d46adccbSFabien Parent GATE_IFR2(CLK_IFR_PWM2, "ifr_pwm2", "pwm_sel", 17), 686d46adccbSFabien Parent GATE_IFR2(CLK_IFR_PWM3, "ifr_pwm3", "pwm_sel", 18), 687d46adccbSFabien Parent GATE_IFR2(CLK_IFR_PWM4, "ifr_pwm4", "pwm_sel", 19), 688d46adccbSFabien Parent GATE_IFR2(CLK_IFR_PWM5, "ifr_pwm5", "pwm_sel", 20), 689d46adccbSFabien Parent GATE_IFR2(CLK_IFR_PWM, "ifr_pwm", "pwm_sel", 21), 690d46adccbSFabien Parent GATE_IFR2(CLK_IFR_UART0, "ifr_uart0", "uart_sel", 22), 691d46adccbSFabien Parent GATE_IFR2(CLK_IFR_UART1, "ifr_uart1", "uart_sel", 23), 692d46adccbSFabien Parent GATE_IFR2(CLK_IFR_UART2, "ifr_uart2", "uart_sel", 24), 693d46adccbSFabien Parent GATE_IFR2(CLK_IFR_DSP_UART, "ifr_dsp_uart", "uart_sel", 26), 694d46adccbSFabien Parent GATE_IFR2(CLK_IFR_GCE_26M, "ifr_gce_26m", "clk26m", 27), 695d46adccbSFabien Parent GATE_IFR2(CLK_IFR_CQ_DMA_FPC, "ifr_cq_dma_fpc", "axi_sel", 28), 696d46adccbSFabien Parent GATE_IFR2(CLK_IFR_BTIF, "ifr_btif", "axi_sel", 31), 697d46adccbSFabien Parent /* IFR3 */ 698d46adccbSFabien Parent GATE_IFR3(CLK_IFR_SPI0, "ifr_spi0", "spi_sel", 1), 699d46adccbSFabien Parent GATE_IFR3(CLK_IFR_MSDC0_HCLK, "ifr_msdc0", "msdc50_0_hc_sel", 2), 700d46adccbSFabien Parent GATE_IFR3(CLK_IFR_MSDC2_HCLK, "ifr_msdc2", "msdc2_2_hc_sel", 3), 701d46adccbSFabien Parent GATE_IFR3(CLK_IFR_MSDC1_HCLK, "ifr_msdc1", "axi_sel", 4), 702d46adccbSFabien Parent GATE_IFR3(CLK_IFR_DVFSRC, "ifr_dvfsrc", "clk26m", 7), 703d46adccbSFabien Parent GATE_IFR3(CLK_IFR_GCPU, "ifr_gcpu", "axi_sel", 8), 704d46adccbSFabien Parent GATE_IFR3(CLK_IFR_TRNG, "ifr_trng", "axi_sel", 9), 705d46adccbSFabien Parent GATE_IFR3(CLK_IFR_AUXADC, "ifr_auxadc", "clk26m", 10), 7063d6f6d2bSAlexandre Mergnat GATE_IFR3(CLK_IFR_CPUM, "ifr_cpum", "clk26m", 11), 707d46adccbSFabien Parent GATE_IFR3(CLK_IFR_AUXADC_MD, "ifr_auxadc_md", "clk26m", 14), 708d46adccbSFabien Parent GATE_IFR3(CLK_IFR_AP_DMA, "ifr_ap_dma", "axi_sel", 18), 709d46adccbSFabien Parent GATE_IFR3(CLK_IFR_DEBUGSYS, "ifr_debugsys", "axi_sel", 24), 710d46adccbSFabien Parent GATE_IFR3(CLK_IFR_AUDIO, "ifr_audio", "axi_sel", 25), 711d46adccbSFabien Parent /* IFR4 */ 712d46adccbSFabien Parent GATE_IFR4(CLK_IFR_PWM_FBCLK6, "ifr_pwm_fbclk6", "pwm_sel", 0), 713d46adccbSFabien Parent GATE_IFR4(CLK_IFR_DISP_PWM, "ifr_disp_pwm", "disp_pwm_sel", 2), 714d46adccbSFabien Parent GATE_IFR4(CLK_IFR_AUD_26M_BK, "ifr_aud_26m_bk", "clk26m", 4), 715d46adccbSFabien Parent GATE_IFR4(CLK_IFR_CQ_DMA, "ifr_cq_dma", "axi_sel", 27), 716d46adccbSFabien Parent /* IFR5 */ 717d46adccbSFabien Parent GATE_IFR5(CLK_IFR_MSDC0_SF, "ifr_msdc0_sf", "msdc50_0_sel", 0), 718d46adccbSFabien Parent GATE_IFR5(CLK_IFR_MSDC1_SF, "ifr_msdc1_sf", "msdc50_0_sel", 1), 719d46adccbSFabien Parent GATE_IFR5(CLK_IFR_MSDC2_SF, "ifr_msdc2_sf", "msdc50_0_sel", 2), 720d46adccbSFabien Parent GATE_IFR5(CLK_IFR_AP_MSDC0, "ifr_ap_msdc0", "msdc50_0_sel", 7), 721d46adccbSFabien Parent GATE_IFR5(CLK_IFR_MD_MSDC0, "ifr_md_msdc0", "msdc50_0_sel", 8), 722d46adccbSFabien Parent GATE_IFR5(CLK_IFR_MSDC0_SRC, "ifr_msdc0_src", "msdc50_0_sel", 9), 723d46adccbSFabien Parent GATE_IFR5(CLK_IFR_MSDC1_SRC, "ifr_msdc1_src", "msdc30_1_sel", 10), 724d46adccbSFabien Parent GATE_IFR5(CLK_IFR_MSDC2_SRC, "ifr_msdc2_src", "msdc50_2_sel", 11), 725d46adccbSFabien Parent GATE_IFR5(CLK_IFR_PWRAP_TMR, "ifr_pwrap_tmr", "clk26m", 12), 726d46adccbSFabien Parent GATE_IFR5(CLK_IFR_PWRAP_SPI, "ifr_pwrap_spi", "clk26m", 13), 727d46adccbSFabien Parent GATE_IFR5(CLK_IFR_PWRAP_SYS, "ifr_pwrap_sys", "clk26m", 14), 7283d6f6d2bSAlexandre Mergnat GATE_MTK_FLAGS(CLK_IFR_MCU_PM_BK, "ifr_mcu_pm_bk", NULL, &ifr5_cg_regs, 7293d6f6d2bSAlexandre Mergnat 17, &mtk_clk_gate_ops_setclr, CLK_IGNORE_UNUSED), 730d46adccbSFabien Parent GATE_IFR5(CLK_IFR_IRRX_26M, "ifr_irrx_26m", "clk26m", 22), 731d46adccbSFabien Parent GATE_IFR5(CLK_IFR_IRRX_32K, "ifr_irrx_32k", "clk32k", 23), 732d46adccbSFabien Parent GATE_IFR5(CLK_IFR_I2C0_AXI, "ifr_i2c0_axi", "i2c_sel", 24), 733d46adccbSFabien Parent GATE_IFR5(CLK_IFR_I2C1_AXI, "ifr_i2c1_axi", "i2c_sel", 25), 734d46adccbSFabien Parent GATE_IFR5(CLK_IFR_I2C2_AXI, "ifr_i2c2_axi", "i2c_sel", 26), 735d46adccbSFabien Parent GATE_IFR5(CLK_IFR_I2C3_AXI, "ifr_i2c3_axi", "i2c_sel", 27), 736d46adccbSFabien Parent GATE_IFR5(CLK_IFR_NIC_AXI, "ifr_nic_axi", "axi_sel", 28), 737d46adccbSFabien Parent GATE_IFR5(CLK_IFR_NIC_SLV_AXI, "ifr_nic_slv_axi", "axi_sel", 29), 738d46adccbSFabien Parent GATE_IFR5(CLK_IFR_APU_AXI, "ifr_apu_axi", "axi_sel", 30), 739d46adccbSFabien Parent /* IFR6 */ 740d46adccbSFabien Parent GATE_IFR6(CLK_IFR_NFIECC, "ifr_nfiecc", "nfiecc_sel", 0), 741d46adccbSFabien Parent GATE_IFR6(CLK_IFR_NFI1X_BK, "ifr_nfi1x_bk", "nfi2x_sel", 1), 742d46adccbSFabien Parent GATE_IFR6(CLK_IFR_NFIECC_BK, "ifr_nfiecc_bk", "nfi2x_sel", 2), 743d46adccbSFabien Parent GATE_IFR6(CLK_IFR_NFI_BK, "ifr_nfi_bk", "axi_sel", 3), 744d46adccbSFabien Parent GATE_IFR6(CLK_IFR_MSDC2_AP_BK, "ifr_msdc2_ap_bk", "axi_sel", 4), 745d46adccbSFabien Parent GATE_IFR6(CLK_IFR_MSDC2_MD_BK, "ifr_msdc2_md_bk", "axi_sel", 5), 746d46adccbSFabien Parent GATE_IFR6(CLK_IFR_MSDC2_BK, "ifr_msdc2_bk", "axi_sel", 6), 747d46adccbSFabien Parent GATE_IFR6(CLK_IFR_SUSB_133_BK, "ifr_susb_133_bk", "axi_sel", 7), 748d46adccbSFabien Parent GATE_IFR6(CLK_IFR_SUSB_66_BK, "ifr_susb_66_bk", "axi_sel", 8), 749d46adccbSFabien Parent GATE_IFR6(CLK_IFR_SSUSB_SYS, "ifr_ssusb_sys", "ssusb_sys_sel", 9), 750d46adccbSFabien Parent GATE_IFR6(CLK_IFR_SSUSB_REF, "ifr_ssusb_ref", "ssusb_sys_sel", 10), 751d46adccbSFabien Parent GATE_IFR6(CLK_IFR_SSUSB_XHCI, "ifr_ssusb_xhci", "ssusb_xhci_sel", 11), 752d46adccbSFabien Parent }; 753d46adccbSFabien Parent 754905b7430SAngeloGioacchino Del Regno static const struct mtk_gate_regs peri_cg_regs = { 755905b7430SAngeloGioacchino Del Regno .set_ofs = 0x20c, 756905b7430SAngeloGioacchino Del Regno .clr_ofs = 0x20c, 757905b7430SAngeloGioacchino Del Regno .sta_ofs = 0x20c, 758d46adccbSFabien Parent }; 759d46adccbSFabien Parent 760905b7430SAngeloGioacchino Del Regno static const struct mtk_gate peri_clks[] = { 761905b7430SAngeloGioacchino Del Regno GATE_MTK(CLK_PERIAXI, "periaxi", "axi_sel", &peri_cg_regs, 31, 762905b7430SAngeloGioacchino Del Regno &mtk_clk_gate_ops_no_setclr), 763905b7430SAngeloGioacchino Del Regno }; 764d46adccbSFabien Parent 765ffe91cb2SAngeloGioacchino Del Regno static const struct mtk_clk_desc topck_desc = { 766ffe91cb2SAngeloGioacchino Del Regno .clks = top_clk_gates, 767ffe91cb2SAngeloGioacchino Del Regno .num_clks = ARRAY_SIZE(top_clk_gates), 768ffe91cb2SAngeloGioacchino Del Regno .fixed_clks = top_fixed_clks, 769ffe91cb2SAngeloGioacchino Del Regno .num_fixed_clks = ARRAY_SIZE(top_fixed_clks), 770ffe91cb2SAngeloGioacchino Del Regno .factor_clks = top_divs, 771ffe91cb2SAngeloGioacchino Del Regno .num_factor_clks = ARRAY_SIZE(top_divs), 772ffe91cb2SAngeloGioacchino Del Regno .mux_clks = top_muxes, 773ffe91cb2SAngeloGioacchino Del Regno .num_mux_clks = ARRAY_SIZE(top_muxes), 774ffe91cb2SAngeloGioacchino Del Regno .composite_clks = top_misc_muxes, 775ffe91cb2SAngeloGioacchino Del Regno .num_composite_clks = ARRAY_SIZE(top_misc_muxes), 776ffe91cb2SAngeloGioacchino Del Regno .divider_clks = top_adj_divs, 777ffe91cb2SAngeloGioacchino Del Regno .num_divider_clks = ARRAY_SIZE(top_adj_divs), 778ffe91cb2SAngeloGioacchino Del Regno .clk_lock = &mt8365_clk_lock, 779d46adccbSFabien Parent }; 780d46adccbSFabien Parent 781ffe91cb2SAngeloGioacchino Del Regno static const struct mtk_clk_desc infra_desc = { 782ffe91cb2SAngeloGioacchino Del Regno .clks = ifr_clks, 783ffe91cb2SAngeloGioacchino Del Regno .num_clks = ARRAY_SIZE(ifr_clks), 784ffe91cb2SAngeloGioacchino Del Regno }; 785d46adccbSFabien Parent 786ffe91cb2SAngeloGioacchino Del Regno static const struct mtk_clk_desc peri_desc = { 787ffe91cb2SAngeloGioacchino Del Regno .clks = peri_clks, 788ffe91cb2SAngeloGioacchino Del Regno .num_clks = ARRAY_SIZE(peri_clks), 789ffe91cb2SAngeloGioacchino Del Regno }; 790d46adccbSFabien Parent 791ffe91cb2SAngeloGioacchino Del Regno static const struct mtk_clk_desc mcu_desc = { 792ffe91cb2SAngeloGioacchino Del Regno .composite_clks = mcu_muxes, 793ffe91cb2SAngeloGioacchino Del Regno .num_composite_clks = ARRAY_SIZE(mcu_muxes), 794ffe91cb2SAngeloGioacchino Del Regno .clk_lock = &mt8365_clk_lock, 795ffe91cb2SAngeloGioacchino Del Regno }; 796d46adccbSFabien Parent 797ffe91cb2SAngeloGioacchino Del Regno static const struct of_device_id of_match_clk_mt8365[] = { 798ffe91cb2SAngeloGioacchino Del Regno { .compatible = "mediatek,mt8365-topckgen", .data = &topck_desc }, 799ffe91cb2SAngeloGioacchino Del Regno { .compatible = "mediatek,mt8365-infracfg", .data = &infra_desc }, 800ffe91cb2SAngeloGioacchino Del Regno { .compatible = "mediatek,mt8365-pericfg", .data = &peri_desc }, 801ffe91cb2SAngeloGioacchino Del Regno { .compatible = "mediatek,mt8365-mcucfg", .data = &mcu_desc }, 802ffe91cb2SAngeloGioacchino Del Regno { /* sentinel */ } 803ffe91cb2SAngeloGioacchino Del Regno }; 80465c9ad77SAngeloGioacchino Del Regno MODULE_DEVICE_TABLE(of, of_match_clk_mt8365); 805d46adccbSFabien Parent 806d46adccbSFabien Parent static struct platform_driver clk_mt8365_drv = { 807d46adccbSFabien Parent .driver = { 808d46adccbSFabien Parent .name = "clk-mt8365", 809d46adccbSFabien Parent .of_match_table = of_match_clk_mt8365, 810d46adccbSFabien Parent }, 811ffe91cb2SAngeloGioacchino Del Regno .probe = mtk_clk_simple_probe, 81261ca6ee7SUwe Kleine-König .remove_new = mtk_clk_simple_remove, 813d46adccbSFabien Parent }; 814ffe91cb2SAngeloGioacchino Del Regno module_platform_driver(clk_mt8365_drv); 815d46adccbSFabien Parent MODULE_LICENSE("GPL"); 816