1db077febSFabien Parent // SPDX-License-Identifier: GPL-2.0 2db077febSFabien Parent /* 3db077febSFabien Parent * Copyright (c) 2019 MediaTek Inc. 4db077febSFabien Parent * Author: James Liao <jamesjj.liao@mediatek.com> 5db077febSFabien Parent * Fabien Parent <fparent@baylibre.com> 6b8390192SAngeloGioacchino Del Regno * Copyright (c) 2023 Collabora Ltd. 7db077febSFabien Parent */ 8db077febSFabien Parent 9db077febSFabien Parent #include <linux/delay.h> 10db077febSFabien Parent #include <linux/of.h> 11db077febSFabien Parent #include <linux/of_address.h> 12db077febSFabien Parent #include <linux/slab.h> 13db077febSFabien Parent #include <linux/mfd/syscon.h> 14b8390192SAngeloGioacchino Del Regno #include <linux/platform_device.h> 15db077febSFabien Parent 16db077febSFabien Parent #include "clk-gate.h" 1739691fb6SChen-Yu Tsai #include "clk-mtk.h" 18db077febSFabien Parent 19db077febSFabien Parent #include <dt-bindings/clock/mt8516-clk.h> 20db077febSFabien Parent 21db077febSFabien Parent static DEFINE_SPINLOCK(mt8516_clk_lock); 22db077febSFabien Parent 23db077febSFabien Parent static const struct mtk_fixed_clk fixed_clks[] __initconst = { 24db077febSFabien Parent FIXED_CLK(CLK_TOP_CLK_NULL, "clk_null", NULL, 0), 25db077febSFabien Parent FIXED_CLK(CLK_TOP_I2S_INFRA_BCK, "i2s_infra_bck", "clk_null", 26000000), 26db077febSFabien Parent FIXED_CLK(CLK_TOP_MEMPLL, "mempll", "clk26m", 800000000), 27db077febSFabien Parent }; 28db077febSFabien Parent 29db077febSFabien Parent static const struct mtk_fixed_factor top_divs[] __initconst = { 30db077febSFabien Parent FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "mempll", 1, 1), 31db077febSFabien Parent FACTOR(CLK_TOP_MAINPLL_D2, "mainpll_d2", "mainpll", 1, 2), 32db077febSFabien Parent FACTOR(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4), 33db077febSFabien Parent FACTOR(CLK_TOP_MAINPLL_D8, "mainpll_d8", "mainpll", 1, 8), 34db077febSFabien Parent FACTOR(CLK_TOP_MAINPLL_D16, "mainpll_d16", "mainpll", 1, 16), 35db077febSFabien Parent FACTOR(CLK_TOP_MAINPLL_D11, "mainpll_d11", "mainpll", 1, 11), 36db077febSFabien Parent FACTOR(CLK_TOP_MAINPLL_D22, "mainpll_d22", "mainpll", 1, 22), 37db077febSFabien Parent FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3), 38db077febSFabien Parent FACTOR(CLK_TOP_MAINPLL_D6, "mainpll_d6", "mainpll", 1, 6), 39db077febSFabien Parent FACTOR(CLK_TOP_MAINPLL_D12, "mainpll_d12", "mainpll", 1, 12), 40db077febSFabien Parent FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5), 41db077febSFabien Parent FACTOR(CLK_TOP_MAINPLL_D10, "mainpll_d10", "mainpll", 1, 10), 42db077febSFabien Parent FACTOR(CLK_TOP_MAINPLL_D20, "mainpll_d20", "mainpll", 1, 20), 43db077febSFabien Parent FACTOR(CLK_TOP_MAINPLL_D40, "mainpll_d40", "mainpll", 1, 40), 44db077febSFabien Parent FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7), 45db077febSFabien Parent FACTOR(CLK_TOP_MAINPLL_D14, "mainpll_d14", "mainpll", 1, 14), 46db077febSFabien Parent FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2), 47db077febSFabien Parent FACTOR(CLK_TOP_UNIVPLL_D4, "univpll_d4", "univpll", 1, 4), 48db077febSFabien Parent FACTOR(CLK_TOP_UNIVPLL_D8, "univpll_d8", "univpll", 1, 8), 49db077febSFabien Parent FACTOR(CLK_TOP_UNIVPLL_D16, "univpll_d16", "univpll", 1, 16), 50db077febSFabien Parent FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3), 51db077febSFabien Parent FACTOR(CLK_TOP_UNIVPLL_D6, "univpll_d6", "univpll", 1, 6), 52db077febSFabien Parent FACTOR(CLK_TOP_UNIVPLL_D12, "univpll_d12", "univpll", 1, 12), 53db077febSFabien Parent FACTOR(CLK_TOP_UNIVPLL_D24, "univpll_d24", "univpll", 1, 24), 54db077febSFabien Parent FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5), 55db077febSFabien Parent FACTOR(CLK_TOP_UNIVPLL_D20, "univpll_d20", "univpll", 1, 20), 56db077febSFabien Parent FACTOR(CLK_TOP_MMPLL380M, "mmpll380m", "mmpll", 1, 1), 57db077febSFabien Parent FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2), 58db077febSFabien Parent FACTOR(CLK_TOP_MMPLL_200M, "mmpll_200m", "mmpll", 1, 3), 59db077febSFabien Parent FACTOR(CLK_TOP_USB_PHY48M, "usb_phy48m_ck", "univpll", 1, 26), 60db077febSFabien Parent FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1), 61db077febSFabien Parent FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1_ck", 1, 2), 62db077febSFabien Parent FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "rg_apll1_d2_en", 1, 2), 63db077febSFabien Parent FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "rg_apll1_d4_en", 1, 2), 64db077febSFabien Parent FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1), 65db077febSFabien Parent FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2_ck", 1, 2), 66db077febSFabien Parent FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "rg_apll2_d2_en", 1, 2), 67db077febSFabien Parent FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "rg_apll2_d4_en", 1, 2), 68db077febSFabien Parent FACTOR(CLK_TOP_CLK26M, "clk26m_ck", "clk26m", 1, 1), 69db077febSFabien Parent FACTOR(CLK_TOP_CLK26M_D2, "clk26m_d2", "clk26m", 1, 2), 70db077febSFabien Parent FACTOR(CLK_TOP_AHB_INFRA_D2, "ahb_infra_d2", "ahb_infra_sel", 1, 2), 71db077febSFabien Parent FACTOR(CLK_TOP_NFI1X, "nfi1x_ck", "nfi2x_pad_sel", 1, 2), 72db077febSFabien Parent FACTOR(CLK_TOP_ETH_D2, "eth_d2_ck", "eth_sel", 1, 2), 73db077febSFabien Parent }; 74db077febSFabien Parent 75db077febSFabien Parent static const char * const uart0_parents[] __initconst = { 76db077febSFabien Parent "clk26m_ck", 77db077febSFabien Parent "univpll_d24" 78db077febSFabien Parent }; 79db077febSFabien Parent 80db077febSFabien Parent static const char * const ahb_infra_parents[] __initconst = { 81db077febSFabien Parent "clk_null", 82db077febSFabien Parent "clk26m_ck", 83db077febSFabien Parent "mainpll_d11", 84db077febSFabien Parent "clk_null", 85db077febSFabien Parent "mainpll_d12", 86db077febSFabien Parent "clk_null", 87db077febSFabien Parent "clk_null", 88db077febSFabien Parent "clk_null", 89db077febSFabien Parent "clk_null", 90db077febSFabien Parent "clk_null", 91db077febSFabien Parent "clk_null", 92db077febSFabien Parent "clk_null", 93db077febSFabien Parent "mainpll_d10" 94db077febSFabien Parent }; 95db077febSFabien Parent 96db077febSFabien Parent static const char * const msdc0_parents[] __initconst = { 97db077febSFabien Parent "clk26m_ck", 98db077febSFabien Parent "univpll_d6", 99db077febSFabien Parent "mainpll_d8", 100db077febSFabien Parent "univpll_d8", 101db077febSFabien Parent "mainpll_d16", 102db077febSFabien Parent "mmpll_200m", 103db077febSFabien Parent "mainpll_d12", 104db077febSFabien Parent "mmpll_d2" 105db077febSFabien Parent }; 106db077febSFabien Parent 107db077febSFabien Parent static const char * const uart1_parents[] __initconst = { 108db077febSFabien Parent "clk26m_ck", 109db077febSFabien Parent "univpll_d24" 110db077febSFabien Parent }; 111db077febSFabien Parent 112db077febSFabien Parent static const char * const msdc1_parents[] __initconst = { 113db077febSFabien Parent "clk26m_ck", 114db077febSFabien Parent "univpll_d6", 115db077febSFabien Parent "mainpll_d8", 116db077febSFabien Parent "univpll_d8", 117db077febSFabien Parent "mainpll_d16", 118db077febSFabien Parent "mmpll_200m", 119db077febSFabien Parent "mainpll_d12", 120db077febSFabien Parent "mmpll_d2" 121db077febSFabien Parent }; 122db077febSFabien Parent 123db077febSFabien Parent static const char * const pmicspi_parents[] __initconst = { 124db077febSFabien Parent "univpll_d20", 125db077febSFabien Parent "usb_phy48m_ck", 126db077febSFabien Parent "univpll_d16", 127db077febSFabien Parent "clk26m_ck" 128db077febSFabien Parent }; 129db077febSFabien Parent 130db077febSFabien Parent static const char * const qaxi_aud26m_parents[] __initconst = { 131db077febSFabien Parent "clk26m_ck", 132db077febSFabien Parent "ahb_infra_sel" 133db077febSFabien Parent }; 134db077febSFabien Parent 135db077febSFabien Parent static const char * const aud_intbus_parents[] __initconst = { 136db077febSFabien Parent "clk_null", 137db077febSFabien Parent "clk26m_ck", 138db077febSFabien Parent "mainpll_d22", 139db077febSFabien Parent "clk_null", 140db077febSFabien Parent "mainpll_d11" 141db077febSFabien Parent }; 142db077febSFabien Parent 143db077febSFabien Parent static const char * const nfi2x_pad_parents[] __initconst = { 144db077febSFabien Parent "clk_null", 145db077febSFabien Parent "clk_null", 146db077febSFabien Parent "clk_null", 147db077febSFabien Parent "clk_null", 148db077febSFabien Parent "clk_null", 149db077febSFabien Parent "clk_null", 150db077febSFabien Parent "clk_null", 151db077febSFabien Parent "clk_null", 152db077febSFabien Parent "clk26m_ck", 153db077febSFabien Parent "clk_null", 154db077febSFabien Parent "clk_null", 155db077febSFabien Parent "clk_null", 156db077febSFabien Parent "clk_null", 157db077febSFabien Parent "clk_null", 158db077febSFabien Parent "clk_null", 159db077febSFabien Parent "clk_null", 160db077febSFabien Parent "clk_null", 161db077febSFabien Parent "mainpll_d12", 162db077febSFabien Parent "mainpll_d8", 163db077febSFabien Parent "clk_null", 164db077febSFabien Parent "mainpll_d6", 165db077febSFabien Parent "clk_null", 166db077febSFabien Parent "clk_null", 167db077febSFabien Parent "clk_null", 168db077febSFabien Parent "clk_null", 169db077febSFabien Parent "clk_null", 170db077febSFabien Parent "clk_null", 171db077febSFabien Parent "clk_null", 172db077febSFabien Parent "clk_null", 173db077febSFabien Parent "clk_null", 174db077febSFabien Parent "clk_null", 175db077febSFabien Parent "clk_null", 176db077febSFabien Parent "mainpll_d4", 177db077febSFabien Parent "clk_null", 178db077febSFabien Parent "clk_null", 179db077febSFabien Parent "clk_null", 180db077febSFabien Parent "clk_null", 181db077febSFabien Parent "clk_null", 182db077febSFabien Parent "clk_null", 183db077febSFabien Parent "clk_null", 184db077febSFabien Parent "clk_null", 185db077febSFabien Parent "clk_null", 186db077febSFabien Parent "clk_null", 187db077febSFabien Parent "clk_null", 188db077febSFabien Parent "clk_null", 189db077febSFabien Parent "clk_null", 190db077febSFabien Parent "clk_null", 191db077febSFabien Parent "clk_null", 192db077febSFabien Parent "clk_null", 193db077febSFabien Parent "clk_null", 194db077febSFabien Parent "clk_null", 195db077febSFabien Parent "clk_null", 196db077febSFabien Parent "clk_null", 197db077febSFabien Parent "clk_null", 198db077febSFabien Parent "clk_null", 199db077febSFabien Parent "clk_null", 200db077febSFabien Parent "clk_null", 201db077febSFabien Parent "clk_null", 202db077febSFabien Parent "clk_null", 203db077febSFabien Parent "clk_null", 204db077febSFabien Parent "clk_null", 205db077febSFabien Parent "clk_null", 206db077febSFabien Parent "clk_null", 207db077febSFabien Parent "clk_null", 208db077febSFabien Parent "clk_null", 209db077febSFabien Parent "clk_null", 210db077febSFabien Parent "clk_null", 211db077febSFabien Parent "clk_null", 212db077febSFabien Parent "clk_null", 213db077febSFabien Parent "clk_null", 214db077febSFabien Parent "clk_null", 215db077febSFabien Parent "clk_null", 216db077febSFabien Parent "clk_null", 217db077febSFabien Parent "clk_null", 218db077febSFabien Parent "clk_null", 219db077febSFabien Parent "clk_null", 220db077febSFabien Parent "clk_null", 221db077febSFabien Parent "clk_null", 222db077febSFabien Parent "clk_null", 223db077febSFabien Parent "clk_null", 224db077febSFabien Parent "clk_null", 225db077febSFabien Parent "mainpll_d10", 226db077febSFabien Parent "mainpll_d7", 227db077febSFabien Parent "clk_null", 228db077febSFabien Parent "mainpll_d5" 229db077febSFabien Parent }; 230db077febSFabien Parent 231db077febSFabien Parent static const char * const nfi1x_pad_parents[] __initconst = { 232db077febSFabien Parent "ahb_infra_sel", 233db077febSFabien Parent "nfi1x_ck" 234db077febSFabien Parent }; 235db077febSFabien Parent 236db077febSFabien Parent static const char * const usb_78m_parents[] __initconst = { 237db077febSFabien Parent "clk_null", 238db077febSFabien Parent "clk26m_ck", 239db077febSFabien Parent "univpll_d16", 240db077febSFabien Parent "clk_null", 241db077febSFabien Parent "mainpll_d20" 242db077febSFabien Parent }; 243db077febSFabien Parent 244db077febSFabien Parent static const char * const spinor_parents[] __initconst = { 245db077febSFabien Parent "clk26m_d2", 246db077febSFabien Parent "clk26m_ck", 247db077febSFabien Parent "mainpll_d40", 248db077febSFabien Parent "univpll_d24", 249db077febSFabien Parent "univpll_d20", 250db077febSFabien Parent "mainpll_d20", 251db077febSFabien Parent "mainpll_d16", 252db077febSFabien Parent "univpll_d12" 253db077febSFabien Parent }; 254db077febSFabien Parent 255db077febSFabien Parent static const char * const msdc2_parents[] __initconst = { 256db077febSFabien Parent "clk26m_ck", 257db077febSFabien Parent "univpll_d6", 258db077febSFabien Parent "mainpll_d8", 259db077febSFabien Parent "univpll_d8", 260db077febSFabien Parent "mainpll_d16", 261db077febSFabien Parent "mmpll_200m", 262db077febSFabien Parent "mainpll_d12", 263db077febSFabien Parent "mmpll_d2" 264db077febSFabien Parent }; 265db077febSFabien Parent 266db077febSFabien Parent static const char * const eth_parents[] __initconst = { 267db077febSFabien Parent "clk26m_ck", 268db077febSFabien Parent "mainpll_d40", 269db077febSFabien Parent "univpll_d24", 270db077febSFabien Parent "univpll_d20", 271db077febSFabien Parent "mainpll_d20" 272db077febSFabien Parent }; 273db077febSFabien Parent 274db077febSFabien Parent static const char * const aud1_parents[] __initconst = { 275db077febSFabien Parent "clk26m_ck", 276db077febSFabien Parent "apll1_ck" 277db077febSFabien Parent }; 278db077febSFabien Parent 279db077febSFabien Parent static const char * const aud2_parents[] __initconst = { 280db077febSFabien Parent "clk26m_ck", 281db077febSFabien Parent "apll2_ck" 282db077febSFabien Parent }; 283db077febSFabien Parent 284db077febSFabien Parent static const char * const aud_engen1_parents[] __initconst = { 285db077febSFabien Parent "clk26m_ck", 286db077febSFabien Parent "rg_apll1_d2_en", 287db077febSFabien Parent "rg_apll1_d4_en", 288db077febSFabien Parent "rg_apll1_d8_en" 289db077febSFabien Parent }; 290db077febSFabien Parent 291db077febSFabien Parent static const char * const aud_engen2_parents[] __initconst = { 292db077febSFabien Parent "clk26m_ck", 293db077febSFabien Parent "rg_apll2_d2_en", 294db077febSFabien Parent "rg_apll2_d4_en", 295db077febSFabien Parent "rg_apll2_d8_en" 296db077febSFabien Parent }; 297db077febSFabien Parent 298db077febSFabien Parent static const char * const i2c_parents[] __initconst = { 299db077febSFabien Parent "clk26m_ck", 300db077febSFabien Parent "univpll_d20", 301db077febSFabien Parent "univpll_d16", 302db077febSFabien Parent "univpll_d12" 303db077febSFabien Parent }; 304db077febSFabien Parent 305db077febSFabien Parent static const char * const aud_i2s0_m_parents[] __initconst = { 306db077febSFabien Parent "rg_aud1", 307db077febSFabien Parent "rg_aud2" 308db077febSFabien Parent }; 309db077febSFabien Parent 310db077febSFabien Parent static const char * const pwm_parents[] __initconst = { 311db077febSFabien Parent "clk26m_ck", 312db077febSFabien Parent "univpll_d12" 313db077febSFabien Parent }; 314db077febSFabien Parent 315db077febSFabien Parent static const char * const spi_parents[] __initconst = { 316db077febSFabien Parent "clk26m_ck", 317db077febSFabien Parent "univpll_d12", 318db077febSFabien Parent "univpll_d8", 319db077febSFabien Parent "univpll_d6" 320db077febSFabien Parent }; 321db077febSFabien Parent 322db077febSFabien Parent static const char * const aud_spdifin_parents[] __initconst = { 323db077febSFabien Parent "clk26m_ck", 324db077febSFabien Parent "univpll_d2" 325db077febSFabien Parent }; 326db077febSFabien Parent 327db077febSFabien Parent static const char * const uart2_parents[] __initconst = { 328db077febSFabien Parent "clk26m_ck", 329db077febSFabien Parent "univpll_d24" 330db077febSFabien Parent }; 331db077febSFabien Parent 332db077febSFabien Parent static const char * const bsi_parents[] __initconst = { 333db077febSFabien Parent "clk26m_ck", 334db077febSFabien Parent "mainpll_d10", 335db077febSFabien Parent "mainpll_d12", 336db077febSFabien Parent "mainpll_d20" 337db077febSFabien Parent }; 338db077febSFabien Parent 339db077febSFabien Parent static const char * const dbg_atclk_parents[] __initconst = { 340db077febSFabien Parent "clk_null", 341db077febSFabien Parent "clk26m_ck", 342db077febSFabien Parent "mainpll_d5", 343db077febSFabien Parent "clk_null", 344db077febSFabien Parent "univpll_d5" 345db077febSFabien Parent }; 346db077febSFabien Parent 347db077febSFabien Parent static const char * const csw_nfiecc_parents[] __initconst = { 348db077febSFabien Parent "clk_null", 349db077febSFabien Parent "mainpll_d7", 350db077febSFabien Parent "mainpll_d6", 351db077febSFabien Parent "clk_null", 352db077febSFabien Parent "mainpll_d5" 353db077febSFabien Parent }; 354db077febSFabien Parent 355db077febSFabien Parent static const char * const nfiecc_parents[] __initconst = { 356db077febSFabien Parent "clk_null", 357db077febSFabien Parent "nfi2x_pad_sel", 358db077febSFabien Parent "mainpll_d4", 359db077febSFabien Parent "clk_null", 360db077febSFabien Parent "csw_nfiecc_sel" 361db077febSFabien Parent }; 362db077febSFabien Parent 363db077febSFabien Parent static struct mtk_composite top_muxes[] __initdata = { 364db077febSFabien Parent /* CLK_MUX_SEL0 */ 365db077febSFabien Parent MUX(CLK_TOP_UART0_SEL, "uart0_sel", uart0_parents, 366db077febSFabien Parent 0x000, 0, 1), 367db077febSFabien Parent MUX(CLK_TOP_AHB_INFRA_SEL, "ahb_infra_sel", ahb_infra_parents, 368db077febSFabien Parent 0x000, 4, 4), 369db077febSFabien Parent MUX(CLK_TOP_MSDC0_SEL, "msdc0_sel", msdc0_parents, 370db077febSFabien Parent 0x000, 11, 3), 371db077febSFabien Parent MUX(CLK_TOP_UART1_SEL, "uart1_sel", uart1_parents, 372db077febSFabien Parent 0x000, 19, 1), 373db077febSFabien Parent MUX(CLK_TOP_MSDC1_SEL, "msdc1_sel", msdc1_parents, 374db077febSFabien Parent 0x000, 20, 3), 375db077febSFabien Parent MUX(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents, 376db077febSFabien Parent 0x000, 24, 2), 377db077febSFabien Parent MUX(CLK_TOP_QAXI_AUD26M_SEL, "qaxi_aud26m_sel", qaxi_aud26m_parents, 378db077febSFabien Parent 0x000, 26, 1), 379db077febSFabien Parent MUX(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents, 380db077febSFabien Parent 0x000, 27, 3), 381db077febSFabien Parent /* CLK_MUX_SEL1 */ 382db077febSFabien Parent MUX(CLK_TOP_NFI2X_PAD_SEL, "nfi2x_pad_sel", nfi2x_pad_parents, 383db077febSFabien Parent 0x004, 0, 7), 384db077febSFabien Parent MUX(CLK_TOP_NFI1X_PAD_SEL, "nfi1x_pad_sel", nfi1x_pad_parents, 385db077febSFabien Parent 0x004, 7, 1), 386db077febSFabien Parent MUX(CLK_TOP_USB_78M_SEL, "usb_78m_sel", usb_78m_parents, 387db077febSFabien Parent 0x004, 20, 3), 388db077febSFabien Parent /* CLK_MUX_SEL8 */ 389db077febSFabien Parent MUX(CLK_TOP_SPINOR_SEL, "spinor_sel", spinor_parents, 390db077febSFabien Parent 0x040, 0, 3), 391db077febSFabien Parent MUX(CLK_TOP_MSDC2_SEL, "msdc2_sel", msdc2_parents, 392db077febSFabien Parent 0x040, 3, 3), 393db077febSFabien Parent MUX(CLK_TOP_ETH_SEL, "eth_sel", eth_parents, 394db077febSFabien Parent 0x040, 6, 3), 395db077febSFabien Parent MUX(CLK_TOP_AUD1_SEL, "aud1_sel", aud1_parents, 396db077febSFabien Parent 0x040, 22, 1), 397db077febSFabien Parent MUX(CLK_TOP_AUD2_SEL, "aud2_sel", aud2_parents, 398db077febSFabien Parent 0x040, 23, 1), 399db077febSFabien Parent MUX(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel", aud_engen1_parents, 400db077febSFabien Parent 0x040, 24, 2), 401db077febSFabien Parent MUX(CLK_TOP_AUD_ENGEN2_SEL, "aud_engen2_sel", aud_engen2_parents, 402db077febSFabien Parent 0x040, 26, 2), 403db077febSFabien Parent MUX(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 404db077febSFabien Parent 0x040, 28, 2), 405db077febSFabien Parent /* CLK_SEL_9 */ 406db077febSFabien Parent MUX(CLK_TOP_AUD_I2S0_M_SEL, "aud_i2s0_m_sel", aud_i2s0_m_parents, 407db077febSFabien Parent 0x044, 12, 1), 408db077febSFabien Parent MUX(CLK_TOP_AUD_I2S1_M_SEL, "aud_i2s1_m_sel", aud_i2s0_m_parents, 409db077febSFabien Parent 0x044, 13, 1), 410db077febSFabien Parent MUX(CLK_TOP_AUD_I2S2_M_SEL, "aud_i2s2_m_sel", aud_i2s0_m_parents, 411db077febSFabien Parent 0x044, 14, 1), 412db077febSFabien Parent MUX(CLK_TOP_AUD_I2S3_M_SEL, "aud_i2s3_m_sel", aud_i2s0_m_parents, 413db077febSFabien Parent 0x044, 15, 1), 414db077febSFabien Parent MUX(CLK_TOP_AUD_I2S4_M_SEL, "aud_i2s4_m_sel", aud_i2s0_m_parents, 415db077febSFabien Parent 0x044, 16, 1), 416db077febSFabien Parent MUX(CLK_TOP_AUD_I2S5_M_SEL, "aud_i2s5_m_sel", aud_i2s0_m_parents, 417db077febSFabien Parent 0x044, 17, 1), 418db077febSFabien Parent MUX(CLK_TOP_AUD_SPDIF_B_SEL, "aud_spdif_b_sel", aud_i2s0_m_parents, 419db077febSFabien Parent 0x044, 18, 1), 420db077febSFabien Parent /* CLK_MUX_SEL13 */ 421db077febSFabien Parent MUX(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 422db077febSFabien Parent 0x07c, 0, 1), 423db077febSFabien Parent MUX(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 424db077febSFabien Parent 0x07c, 1, 2), 425db077febSFabien Parent MUX(CLK_TOP_AUD_SPDIFIN_SEL, "aud_spdifin_sel", aud_spdifin_parents, 426db077febSFabien Parent 0x07c, 3, 1), 427db077febSFabien Parent MUX(CLK_TOP_UART2_SEL, "uart2_sel", uart2_parents, 428db077febSFabien Parent 0x07c, 4, 1), 429db077febSFabien Parent MUX(CLK_TOP_BSI_SEL, "bsi_sel", bsi_parents, 430db077febSFabien Parent 0x07c, 5, 2), 431db077febSFabien Parent MUX(CLK_TOP_DBG_ATCLK_SEL, "dbg_atclk_sel", dbg_atclk_parents, 432db077febSFabien Parent 0x07c, 7, 3), 433db077febSFabien Parent MUX(CLK_TOP_CSW_NFIECC_SEL, "csw_nfiecc_sel", csw_nfiecc_parents, 434db077febSFabien Parent 0x07c, 10, 3), 435db077febSFabien Parent MUX(CLK_TOP_NFIECC_SEL, "nfiecc_sel", nfiecc_parents, 436db077febSFabien Parent 0x07c, 13, 3), 437db077febSFabien Parent }; 438db077febSFabien Parent 439db077febSFabien Parent static const char * const ifr_mux1_parents[] __initconst = { 440db077febSFabien Parent "clk26m_ck", 441db077febSFabien Parent "armpll", 442db077febSFabien Parent "univpll", 443db077febSFabien Parent "mainpll_d2" 444db077febSFabien Parent }; 445db077febSFabien Parent 446db077febSFabien Parent static const char * const ifr_eth_25m_parents[] __initconst = { 447db077febSFabien Parent "eth_d2_ck", 448db077febSFabien Parent "rg_eth" 449db077febSFabien Parent }; 450db077febSFabien Parent 451db077febSFabien Parent static const char * const ifr_i2c0_parents[] __initconst = { 452db077febSFabien Parent "ahb_infra_d2", 453db077febSFabien Parent "rg_i2c" 454db077febSFabien Parent }; 455db077febSFabien Parent 456db077febSFabien Parent static const struct mtk_composite ifr_muxes[] __initconst = { 457db077febSFabien Parent MUX(CLK_IFR_MUX1_SEL, "ifr_mux1_sel", ifr_mux1_parents, 0x000, 458db077febSFabien Parent 2, 2), 459db077febSFabien Parent MUX(CLK_IFR_ETH_25M_SEL, "ifr_eth_25m_sel", ifr_eth_25m_parents, 0x080, 460db077febSFabien Parent 0, 1), 461db077febSFabien Parent MUX(CLK_IFR_I2C0_SEL, "ifr_i2c0_sel", ifr_i2c0_parents, 0x080, 462db077febSFabien Parent 1, 1), 463db077febSFabien Parent MUX(CLK_IFR_I2C1_SEL, "ifr_i2c1_sel", ifr_i2c0_parents, 0x080, 464db077febSFabien Parent 2, 1), 465db077febSFabien Parent MUX(CLK_IFR_I2C2_SEL, "ifr_i2c2_sel", ifr_i2c0_parents, 0x080, 466db077febSFabien Parent 3, 1), 467db077febSFabien Parent }; 468db077febSFabien Parent 469db077febSFabien Parent #define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) { \ 470db077febSFabien Parent .id = _id, \ 471db077febSFabien Parent .name = _name, \ 472db077febSFabien Parent .parent_name = _parent, \ 473db077febSFabien Parent .div_reg = _reg, \ 474db077febSFabien Parent .div_shift = _shift, \ 475db077febSFabien Parent .div_width = _width, \ 476db077febSFabien Parent } 477db077febSFabien Parent 478db077febSFabien Parent static const struct mtk_clk_divider top_adj_divs[] = { 479db077febSFabien Parent DIV_ADJ(CLK_TOP_APLL12_CK_DIV0, "apll12_ck_div0", "aud_i2s0_m_sel", 480db077febSFabien Parent 0x0048, 0, 8), 481db077febSFabien Parent DIV_ADJ(CLK_TOP_APLL12_CK_DIV1, "apll12_ck_div1", "aud_i2s1_m_sel", 482db077febSFabien Parent 0x0048, 8, 8), 483db077febSFabien Parent DIV_ADJ(CLK_TOP_APLL12_CK_DIV2, "apll12_ck_div2", "aud_i2s2_m_sel", 484db077febSFabien Parent 0x0048, 16, 8), 485db077febSFabien Parent DIV_ADJ(CLK_TOP_APLL12_CK_DIV3, "apll12_ck_div3", "aud_i2s3_m_sel", 486db077febSFabien Parent 0x0048, 24, 8), 487db077febSFabien Parent DIV_ADJ(CLK_TOP_APLL12_CK_DIV4, "apll12_ck_div4", "aud_i2s4_m_sel", 488db077febSFabien Parent 0x004c, 0, 8), 489db077febSFabien Parent DIV_ADJ(CLK_TOP_APLL12_CK_DIV4B, "apll12_ck_div4b", "apll12_div4", 490db077febSFabien Parent 0x004c, 8, 8), 491db077febSFabien Parent DIV_ADJ(CLK_TOP_APLL12_CK_DIV5, "apll12_ck_div5", "aud_i2s5_m_sel", 492db077febSFabien Parent 0x004c, 16, 8), 493db077febSFabien Parent DIV_ADJ(CLK_TOP_APLL12_CK_DIV5B, "apll12_ck_div5b", "apll12_div5", 494db077febSFabien Parent 0x004c, 24, 8), 495db077febSFabien Parent DIV_ADJ(CLK_TOP_APLL12_CK_DIV6, "apll12_ck_div6", "aud_spdif_b_sel", 496db077febSFabien Parent 0x0078, 0, 8), 497db077febSFabien Parent }; 498db077febSFabien Parent 499db077febSFabien Parent static const struct mtk_gate_regs top1_cg_regs = { 500db077febSFabien Parent .set_ofs = 0x54, 501db077febSFabien Parent .clr_ofs = 0x84, 502db077febSFabien Parent .sta_ofs = 0x24, 503db077febSFabien Parent }; 504db077febSFabien Parent 505db077febSFabien Parent static const struct mtk_gate_regs top2_cg_regs = { 506db077febSFabien Parent .set_ofs = 0x6c, 507db077febSFabien Parent .clr_ofs = 0x9c, 508db077febSFabien Parent .sta_ofs = 0x3c, 509db077febSFabien Parent }; 510db077febSFabien Parent 511db077febSFabien Parent static const struct mtk_gate_regs top3_cg_regs = { 512db077febSFabien Parent .set_ofs = 0xa0, 513db077febSFabien Parent .clr_ofs = 0xb0, 514db077febSFabien Parent .sta_ofs = 0x70, 515db077febSFabien Parent }; 516db077febSFabien Parent 517db077febSFabien Parent static const struct mtk_gate_regs top4_cg_regs = { 518db077febSFabien Parent .set_ofs = 0xa4, 519db077febSFabien Parent .clr_ofs = 0xb4, 520db077febSFabien Parent .sta_ofs = 0x74, 521db077febSFabien Parent }; 522db077febSFabien Parent 523db077febSFabien Parent static const struct mtk_gate_regs top5_cg_regs = { 524db077febSFabien Parent .set_ofs = 0x44, 525db077febSFabien Parent .clr_ofs = 0x44, 526db077febSFabien Parent .sta_ofs = 0x44, 527db077febSFabien Parent }; 528db077febSFabien Parent 5294c85e20bSAngeloGioacchino Del Regno #define GATE_TOP1(_id, _name, _parent, _shift) \ 5304c85e20bSAngeloGioacchino Del Regno GATE_MTK(_id, _name, _parent, &top1_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 531db077febSFabien Parent 5324c85e20bSAngeloGioacchino Del Regno #define GATE_TOP2(_id, _name, _parent, _shift) \ 5334c85e20bSAngeloGioacchino Del Regno GATE_MTK(_id, _name, _parent, &top2_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 534db077febSFabien Parent 5354c85e20bSAngeloGioacchino Del Regno #define GATE_TOP2_I(_id, _name, _parent, _shift) \ 5364c85e20bSAngeloGioacchino Del Regno GATE_MTK(_id, _name, _parent, &top2_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv) 537db077febSFabien Parent 5384c85e20bSAngeloGioacchino Del Regno #define GATE_TOP3(_id, _name, _parent, _shift) \ 5394c85e20bSAngeloGioacchino Del Regno GATE_MTK(_id, _name, _parent, &top3_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 540db077febSFabien Parent 5414c85e20bSAngeloGioacchino Del Regno #define GATE_TOP4_I(_id, _name, _parent, _shift) \ 5424c85e20bSAngeloGioacchino Del Regno GATE_MTK(_id, _name, _parent, &top4_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv) 543db077febSFabien Parent 5444c85e20bSAngeloGioacchino Del Regno #define GATE_TOP5(_id, _name, _parent, _shift) \ 5454c85e20bSAngeloGioacchino Del Regno GATE_MTK(_id, _name, _parent, &top5_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 546db077febSFabien Parent 547db077febSFabien Parent static const struct mtk_gate top_clks[] __initconst = { 548db077febSFabien Parent /* TOP1 */ 549db077febSFabien Parent GATE_TOP1(CLK_TOP_THEM, "them", "ahb_infra_sel", 1), 550db077febSFabien Parent GATE_TOP1(CLK_TOP_APDMA, "apdma", "ahb_infra_sel", 2), 551db077febSFabien Parent GATE_TOP1(CLK_TOP_I2C0, "i2c0", "ifr_i2c0_sel", 3), 552db077febSFabien Parent GATE_TOP1(CLK_TOP_I2C1, "i2c1", "ifr_i2c1_sel", 4), 553db077febSFabien Parent GATE_TOP1(CLK_TOP_AUXADC1, "auxadc1", "ahb_infra_sel", 5), 554db077febSFabien Parent GATE_TOP1(CLK_TOP_NFI, "nfi", "nfi1x_pad_sel", 6), 555db077febSFabien Parent GATE_TOP1(CLK_TOP_NFIECC, "nfiecc", "rg_nfiecc", 7), 556db077febSFabien Parent GATE_TOP1(CLK_TOP_DEBUGSYS, "debugsys", "rg_dbg_atclk", 8), 557db077febSFabien Parent GATE_TOP1(CLK_TOP_PWM, "pwm", "ahb_infra_sel", 9), 558db077febSFabien Parent GATE_TOP1(CLK_TOP_UART0, "uart0", "uart0_sel", 10), 559db077febSFabien Parent GATE_TOP1(CLK_TOP_UART1, "uart1", "uart1_sel", 11), 560db077febSFabien Parent GATE_TOP1(CLK_TOP_BTIF, "btif", "ahb_infra_sel", 12), 561db077febSFabien Parent GATE_TOP1(CLK_TOP_USB, "usb", "usb_78m", 13), 562db077febSFabien Parent GATE_TOP1(CLK_TOP_FLASHIF_26M, "flashif_26m", "clk26m_ck", 14), 563db077febSFabien Parent GATE_TOP1(CLK_TOP_AUXADC2, "auxadc2", "ahb_infra_sel", 15), 564db077febSFabien Parent GATE_TOP1(CLK_TOP_I2C2, "i2c2", "ifr_i2c2_sel", 16), 565db077febSFabien Parent GATE_TOP1(CLK_TOP_MSDC0, "msdc0", "msdc0_sel", 17), 566db077febSFabien Parent GATE_TOP1(CLK_TOP_MSDC1, "msdc1", "msdc1_sel", 18), 567db077febSFabien Parent GATE_TOP1(CLK_TOP_NFI2X, "nfi2x", "nfi2x_pad_sel", 19), 568db077febSFabien Parent GATE_TOP1(CLK_TOP_PMICWRAP_AP, "pwrap_ap", "clk26m_ck", 20), 569db077febSFabien Parent GATE_TOP1(CLK_TOP_SEJ, "sej", "ahb_infra_sel", 21), 570db077febSFabien Parent GATE_TOP1(CLK_TOP_MEMSLP_DLYER, "memslp_dlyer", "clk26m_ck", 22), 571db077febSFabien Parent GATE_TOP1(CLK_TOP_SPI, "spi", "spi_sel", 23), 572db077febSFabien Parent GATE_TOP1(CLK_TOP_APXGPT, "apxgpt", "clk26m_ck", 24), 573db077febSFabien Parent GATE_TOP1(CLK_TOP_AUDIO, "audio", "clk26m_ck", 25), 574db077febSFabien Parent GATE_TOP1(CLK_TOP_PMICWRAP_MD, "pwrap_md", "clk26m_ck", 27), 575db077febSFabien Parent GATE_TOP1(CLK_TOP_PMICWRAP_CONN, "pwrap_conn", "clk26m_ck", 28), 576db077febSFabien Parent GATE_TOP1(CLK_TOP_PMICWRAP_26M, "pwrap_26m", "clk26m_ck", 29), 577db077febSFabien Parent GATE_TOP1(CLK_TOP_AUX_ADC, "aux_adc", "clk26m_ck", 30), 578db077febSFabien Parent GATE_TOP1(CLK_TOP_AUX_TP, "aux_tp", "clk26m_ck", 31), 579db077febSFabien Parent /* TOP2 */ 580db077febSFabien Parent GATE_TOP2(CLK_TOP_MSDC2, "msdc2", "ahb_infra_sel", 0), 581db077febSFabien Parent GATE_TOP2(CLK_TOP_RBIST, "rbist", "univpll_d12", 1), 582db077febSFabien Parent GATE_TOP2(CLK_TOP_NFI_BUS, "nfi_bus", "ahb_infra_sel", 2), 583db077febSFabien Parent GATE_TOP2(CLK_TOP_GCE, "gce", "ahb_infra_sel", 4), 584db077febSFabien Parent GATE_TOP2(CLK_TOP_TRNG, "trng", "ahb_infra_sel", 5), 585db077febSFabien Parent GATE_TOP2(CLK_TOP_SEJ_13M, "sej_13m", "clk26m_ck", 6), 586db077febSFabien Parent GATE_TOP2(CLK_TOP_AES, "aes", "ahb_infra_sel", 7), 587db077febSFabien Parent GATE_TOP2(CLK_TOP_PWM_B, "pwm_b", "rg_pwm_infra", 8), 588db077febSFabien Parent GATE_TOP2(CLK_TOP_PWM1_FB, "pwm1_fb", "rg_pwm_infra", 9), 589db077febSFabien Parent GATE_TOP2(CLK_TOP_PWM2_FB, "pwm2_fb", "rg_pwm_infra", 10), 590db077febSFabien Parent GATE_TOP2(CLK_TOP_PWM3_FB, "pwm3_fb", "rg_pwm_infra", 11), 591db077febSFabien Parent GATE_TOP2(CLK_TOP_PWM4_FB, "pwm4_fb", "rg_pwm_infra", 12), 592db077febSFabien Parent GATE_TOP2(CLK_TOP_PWM5_FB, "pwm5_fb", "rg_pwm_infra", 13), 593db077febSFabien Parent GATE_TOP2(CLK_TOP_USB_1P, "usb_1p", "usb_78m", 14), 594db077febSFabien Parent GATE_TOP2(CLK_TOP_FLASHIF_FREERUN, "flashif_freerun", "ahb_infra_sel", 595db077febSFabien Parent 15), 596db077febSFabien Parent GATE_TOP2(CLK_TOP_66M_ETH, "eth_66m", "ahb_infra_d2", 19), 597db077febSFabien Parent GATE_TOP2(CLK_TOP_133M_ETH, "eth_133m", "ahb_infra_sel", 20), 598db077febSFabien Parent GATE_TOP2(CLK_TOP_FETH_25M, "feth_25m", "ifr_eth_25m_sel", 21), 599db077febSFabien Parent GATE_TOP2(CLK_TOP_FETH_50M, "feth_50m", "rg_eth", 22), 600db077febSFabien Parent GATE_TOP2(CLK_TOP_FLASHIF_AXI, "flashif_axi", "ahb_infra_sel", 23), 601db077febSFabien Parent GATE_TOP2(CLK_TOP_USBIF, "usbif", "ahb_infra_sel", 24), 602db077febSFabien Parent GATE_TOP2(CLK_TOP_UART2, "uart2", "rg_uart2", 25), 603db077febSFabien Parent GATE_TOP2(CLK_TOP_BSI, "bsi", "ahb_infra_sel", 26), 604db077febSFabien Parent GATE_TOP2_I(CLK_TOP_MSDC0_INFRA, "msdc0_infra", "msdc0", 28), 605db077febSFabien Parent GATE_TOP2_I(CLK_TOP_MSDC1_INFRA, "msdc1_infra", "msdc1", 29), 606db077febSFabien Parent GATE_TOP2_I(CLK_TOP_MSDC2_INFRA, "msdc2_infra", "rg_msdc2", 30), 607db077febSFabien Parent GATE_TOP2(CLK_TOP_USB_78M, "usb_78m", "usb_78m_sel", 31), 608db077febSFabien Parent /* TOP3 */ 609db077febSFabien Parent GATE_TOP3(CLK_TOP_RG_SPINOR, "rg_spinor", "spinor_sel", 0), 610db077febSFabien Parent GATE_TOP3(CLK_TOP_RG_MSDC2, "rg_msdc2", "msdc2_sel", 1), 611db077febSFabien Parent GATE_TOP3(CLK_TOP_RG_ETH, "rg_eth", "eth_sel", 2), 612db077febSFabien Parent GATE_TOP3(CLK_TOP_RG_AUD1, "rg_aud1", "aud1_sel", 8), 613db077febSFabien Parent GATE_TOP3(CLK_TOP_RG_AUD2, "rg_aud2", "aud2_sel", 9), 614db077febSFabien Parent GATE_TOP3(CLK_TOP_RG_AUD_ENGEN1, "rg_aud_engen1", "aud_engen1_sel", 10), 615db077febSFabien Parent GATE_TOP3(CLK_TOP_RG_AUD_ENGEN2, "rg_aud_engen2", "aud_engen2_sel", 11), 616db077febSFabien Parent GATE_TOP3(CLK_TOP_RG_I2C, "rg_i2c", "i2c_sel", 12), 617db077febSFabien Parent GATE_TOP3(CLK_TOP_RG_PWM_INFRA, "rg_pwm_infra", "pwm_sel", 13), 618db077febSFabien Parent GATE_TOP3(CLK_TOP_RG_AUD_SPDIF_IN, "rg_aud_spdif_in", "aud_spdifin_sel", 619db077febSFabien Parent 14), 620db077febSFabien Parent GATE_TOP3(CLK_TOP_RG_UART2, "rg_uart2", "uart2_sel", 15), 621db077febSFabien Parent GATE_TOP3(CLK_TOP_RG_BSI, "rg_bsi", "bsi_sel", 16), 622db077febSFabien Parent GATE_TOP3(CLK_TOP_RG_DBG_ATCLK, "rg_dbg_atclk", "dbg_atclk_sel", 17), 623db077febSFabien Parent GATE_TOP3(CLK_TOP_RG_NFIECC, "rg_nfiecc", "nfiecc_sel", 18), 624db077febSFabien Parent /* TOP4 */ 625db077febSFabien Parent GATE_TOP4_I(CLK_TOP_RG_APLL1_D2_EN, "rg_apll1_d2_en", "apll1_d2", 8), 626db077febSFabien Parent GATE_TOP4_I(CLK_TOP_RG_APLL1_D4_EN, "rg_apll1_d4_en", "apll1_d4", 9), 627db077febSFabien Parent GATE_TOP4_I(CLK_TOP_RG_APLL1_D8_EN, "rg_apll1_d8_en", "apll1_d8", 10), 628db077febSFabien Parent GATE_TOP4_I(CLK_TOP_RG_APLL2_D2_EN, "rg_apll2_d2_en", "apll2_d2", 11), 629db077febSFabien Parent GATE_TOP4_I(CLK_TOP_RG_APLL2_D4_EN, "rg_apll2_d4_en", "apll2_d4", 12), 630db077febSFabien Parent GATE_TOP4_I(CLK_TOP_RG_APLL2_D8_EN, "rg_apll2_d8_en", "apll2_d8", 13), 631db077febSFabien Parent /* TOP5 */ 632db077febSFabien Parent GATE_TOP5(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll12_ck_div0", 0), 633db077febSFabien Parent GATE_TOP5(CLK_TOP_APLL12_DIV1, "apll12_div1", "apll12_ck_div1", 1), 634db077febSFabien Parent GATE_TOP5(CLK_TOP_APLL12_DIV2, "apll12_div2", "apll12_ck_div2", 2), 635db077febSFabien Parent GATE_TOP5(CLK_TOP_APLL12_DIV3, "apll12_div3", "apll12_ck_div3", 3), 636db077febSFabien Parent GATE_TOP5(CLK_TOP_APLL12_DIV4, "apll12_div4", "apll12_ck_div4", 4), 637db077febSFabien Parent GATE_TOP5(CLK_TOP_APLL12_DIV4B, "apll12_div4b", "apll12_ck_div4b", 5), 638db077febSFabien Parent GATE_TOP5(CLK_TOP_APLL12_DIV5, "apll12_div5", "apll12_ck_div5", 6), 639db077febSFabien Parent GATE_TOP5(CLK_TOP_APLL12_DIV5B, "apll12_div5b", "apll12_ck_div5b", 7), 640db077febSFabien Parent GATE_TOP5(CLK_TOP_APLL12_DIV6, "apll12_div6", "apll12_ck_div6", 8), 641db077febSFabien Parent }; 642db077febSFabien Parent 643b8390192SAngeloGioacchino Del Regno static const struct mtk_clk_desc topck_desc = { 644b8390192SAngeloGioacchino Del Regno .clks = top_clks, 645b8390192SAngeloGioacchino Del Regno .num_clks = ARRAY_SIZE(top_clks), 646b8390192SAngeloGioacchino Del Regno .fixed_clks = fixed_clks, 647b8390192SAngeloGioacchino Del Regno .num_fixed_clks = ARRAY_SIZE(fixed_clks), 648b8390192SAngeloGioacchino Del Regno .factor_clks = top_divs, 649b8390192SAngeloGioacchino Del Regno .num_factor_clks = ARRAY_SIZE(top_divs), 650b8390192SAngeloGioacchino Del Regno .composite_clks = top_muxes, 651b8390192SAngeloGioacchino Del Regno .num_composite_clks = ARRAY_SIZE(top_muxes), 652b8390192SAngeloGioacchino Del Regno .divider_clks = top_adj_divs, 653b8390192SAngeloGioacchino Del Regno .num_divider_clks = ARRAY_SIZE(top_adj_divs), 654b8390192SAngeloGioacchino Del Regno .clk_lock = &mt8516_clk_lock, 655b8390192SAngeloGioacchino Del Regno }; 656db077febSFabien Parent 657b8390192SAngeloGioacchino Del Regno static const struct mtk_clk_desc infra_desc = { 658b8390192SAngeloGioacchino Del Regno .composite_clks = ifr_muxes, 659b8390192SAngeloGioacchino Del Regno .num_composite_clks = ARRAY_SIZE(ifr_muxes), 660b8390192SAngeloGioacchino Del Regno .clk_lock = &mt8516_clk_lock, 661b8390192SAngeloGioacchino Del Regno }; 662db077febSFabien Parent 663b8390192SAngeloGioacchino Del Regno static const struct of_device_id of_match_clk_mt8516[] = { 664b8390192SAngeloGioacchino Del Regno { .compatible = "mediatek,mt8516-topckgen", .data = &topck_desc }, 665b8390192SAngeloGioacchino Del Regno { .compatible = "mediatek,mt8516-infracfg", .data = &infra_desc }, 666b8390192SAngeloGioacchino Del Regno { /* sentinel */ } 667b8390192SAngeloGioacchino Del Regno }; 66865c9ad77SAngeloGioacchino Del Regno MODULE_DEVICE_TABLE(of, of_match_clk_mt8516); 669db077febSFabien Parent 670b8390192SAngeloGioacchino Del Regno static struct platform_driver clk_mt8516_drv = { 671b8390192SAngeloGioacchino Del Regno .probe = mtk_clk_simple_probe, 672*61ca6ee7SUwe Kleine-König .remove_new = mtk_clk_simple_remove, 673b8390192SAngeloGioacchino Del Regno .driver = { 674b8390192SAngeloGioacchino Del Regno .name = "clk-mt8516", 675b8390192SAngeloGioacchino Del Regno .of_match_table = of_match_clk_mt8516, 676b8390192SAngeloGioacchino Del Regno }, 677b8390192SAngeloGioacchino Del Regno }; 678b8390192SAngeloGioacchino Del Regno module_platform_driver(clk_mt8516_drv); 679db077febSFabien Parent 680b8390192SAngeloGioacchino Del Regno MODULE_DESCRIPTION("MediaTek MT8516 clocks driver"); 681b8390192SAngeloGioacchino Del Regno MODULE_LICENSE("GPL"); 682