1*125ab5d5SJiaxin Yu /* SPDX-License-Identifier: GPL-2.0 */ 2*125ab5d5SJiaxin Yu /* 3*125ab5d5SJiaxin Yu * mt8192-afe-clk.h -- Mediatek 8192 afe clock ctrl definition 4*125ab5d5SJiaxin Yu * 5*125ab5d5SJiaxin Yu * Copyright (c) 2020 MediaTek Inc. 6*125ab5d5SJiaxin Yu * Author: Shane Chien <shane.chien@mediatek.com> 7*125ab5d5SJiaxin Yu */ 8*125ab5d5SJiaxin Yu 9*125ab5d5SJiaxin Yu #ifndef _MT8192_AFE_CLOCK_CTRL_H_ 10*125ab5d5SJiaxin Yu #define _MT8192_AFE_CLOCK_CTRL_H_ 11*125ab5d5SJiaxin Yu 12*125ab5d5SJiaxin Yu #define AP_PLL_CON3 0x0014 13*125ab5d5SJiaxin Yu #define APLL1_CON0 0x0318 14*125ab5d5SJiaxin Yu #define APLL1_CON1 0x031c 15*125ab5d5SJiaxin Yu #define APLL1_CON2 0x0320 16*125ab5d5SJiaxin Yu #define APLL1_CON4 0x0328 17*125ab5d5SJiaxin Yu #define APLL1_TUNER_CON0 0x0040 18*125ab5d5SJiaxin Yu 19*125ab5d5SJiaxin Yu #define APLL2_CON0 0x032c 20*125ab5d5SJiaxin Yu #define APLL2_CON1 0x0330 21*125ab5d5SJiaxin Yu #define APLL2_CON2 0x0334 22*125ab5d5SJiaxin Yu #define APLL2_CON4 0x033c 23*125ab5d5SJiaxin Yu #define APLL2_TUNER_CON0 0x0044 24*125ab5d5SJiaxin Yu 25*125ab5d5SJiaxin Yu #define CLK_CFG_7 0x0080 26*125ab5d5SJiaxin Yu #define CLK_CFG_8 0x0090 27*125ab5d5SJiaxin Yu #define CLK_CFG_11 0x00c0 28*125ab5d5SJiaxin Yu #define CLK_CFG_12 0x00d0 29*125ab5d5SJiaxin Yu #define CLK_CFG_13 0x00e0 30*125ab5d5SJiaxin Yu #define CLK_CFG_15 0x0100 31*125ab5d5SJiaxin Yu 32*125ab5d5SJiaxin Yu #define CLK_AUDDIV_0 0x0320 33*125ab5d5SJiaxin Yu #define CLK_AUDDIV_2 0x0328 34*125ab5d5SJiaxin Yu #define CLK_AUDDIV_3 0x0334 35*125ab5d5SJiaxin Yu #define CLK_AUDDIV_4 0x0338 36*125ab5d5SJiaxin Yu #define CKSYS_AUD_TOP_CFG 0x032c 37*125ab5d5SJiaxin Yu #define CKSYS_AUD_TOP_MON 0x0330 38*125ab5d5SJiaxin Yu 39*125ab5d5SJiaxin Yu #define PERI_BUS_DCM_CTRL 0x0074 40*125ab5d5SJiaxin Yu #define MODULE_SW_CG_1_STA 0x0094 41*125ab5d5SJiaxin Yu #define MODULE_SW_CG_2_STA 0x00ac 42*125ab5d5SJiaxin Yu 43*125ab5d5SJiaxin Yu /* CLK_AUDDIV_0 */ 44*125ab5d5SJiaxin Yu #define APLL12_DIV0_PDN_SFT 0 45*125ab5d5SJiaxin Yu #define APLL12_DIV0_PDN_MASK 0x1 46*125ab5d5SJiaxin Yu #define APLL12_DIV0_PDN_MASK_SFT (0x1 << 0) 47*125ab5d5SJiaxin Yu #define APLL12_DIV1_PDN_SFT 1 48*125ab5d5SJiaxin Yu #define APLL12_DIV1_PDN_MASK 0x1 49*125ab5d5SJiaxin Yu #define APLL12_DIV1_PDN_MASK_SFT (0x1 << 1) 50*125ab5d5SJiaxin Yu #define APLL12_DIV2_PDN_SFT 2 51*125ab5d5SJiaxin Yu #define APLL12_DIV2_PDN_MASK 0x1 52*125ab5d5SJiaxin Yu #define APLL12_DIV2_PDN_MASK_SFT (0x1 << 2) 53*125ab5d5SJiaxin Yu #define APLL12_DIV3_PDN_SFT 3 54*125ab5d5SJiaxin Yu #define APLL12_DIV3_PDN_MASK 0x1 55*125ab5d5SJiaxin Yu #define APLL12_DIV3_PDN_MASK_SFT (0x1 << 3) 56*125ab5d5SJiaxin Yu #define APLL12_DIV4_PDN_SFT 4 57*125ab5d5SJiaxin Yu #define APLL12_DIV4_PDN_MASK 0x1 58*125ab5d5SJiaxin Yu #define APLL12_DIV4_PDN_MASK_SFT (0x1 << 4) 59*125ab5d5SJiaxin Yu #define APLL12_DIVB_PDN_SFT 5 60*125ab5d5SJiaxin Yu #define APLL12_DIVB_PDN_MASK 0x1 61*125ab5d5SJiaxin Yu #define APLL12_DIVB_PDN_MASK_SFT (0x1 << 5) 62*125ab5d5SJiaxin Yu #define APLL12_DIV5_PDN_SFT 6 63*125ab5d5SJiaxin Yu #define APLL12_DIV5_PDN_MASK 0x1 64*125ab5d5SJiaxin Yu #define APLL12_DIV5_PDN_MASK_SFT (0x1 << 6) 65*125ab5d5SJiaxin Yu #define APLL12_DIV6_PDN_SFT 7 66*125ab5d5SJiaxin Yu #define APLL12_DIV6_PDN_MASK 0x1 67*125ab5d5SJiaxin Yu #define APLL12_DIV6_PDN_MASK_SFT (0x1 << 7) 68*125ab5d5SJiaxin Yu #define APLL12_DIV7_PDN_SFT 8 69*125ab5d5SJiaxin Yu #define APLL12_DIV7_PDN_MASK 0x1 70*125ab5d5SJiaxin Yu #define APLL12_DIV7_PDN_MASK_SFT (0x1 << 8) 71*125ab5d5SJiaxin Yu #define APLL12_DIV8_PDN_SFT 9 72*125ab5d5SJiaxin Yu #define APLL12_DIV8_PDN_MASK 0x1 73*125ab5d5SJiaxin Yu #define APLL12_DIV8_PDN_MASK_SFT (0x1 << 9) 74*125ab5d5SJiaxin Yu #define APLL12_DIV9_PDN_SFT 10 75*125ab5d5SJiaxin Yu #define APLL12_DIV9_PDN_MASK 0x1 76*125ab5d5SJiaxin Yu #define APLL12_DIV9_PDN_MASK_SFT (0x1 << 10) 77*125ab5d5SJiaxin Yu #define APLL_I2S0_MCK_SEL_SFT 16 78*125ab5d5SJiaxin Yu #define APLL_I2S0_MCK_SEL_MASK 0x1 79*125ab5d5SJiaxin Yu #define APLL_I2S0_MCK_SEL_MASK_SFT (0x1 << 16) 80*125ab5d5SJiaxin Yu #define APLL_I2S1_MCK_SEL_SFT 17 81*125ab5d5SJiaxin Yu #define APLL_I2S1_MCK_SEL_MASK 0x1 82*125ab5d5SJiaxin Yu #define APLL_I2S1_MCK_SEL_MASK_SFT (0x1 << 17) 83*125ab5d5SJiaxin Yu #define APLL_I2S2_MCK_SEL_SFT 18 84*125ab5d5SJiaxin Yu #define APLL_I2S2_MCK_SEL_MASK 0x1 85*125ab5d5SJiaxin Yu #define APLL_I2S2_MCK_SEL_MASK_SFT (0x1 << 18) 86*125ab5d5SJiaxin Yu #define APLL_I2S3_MCK_SEL_SFT 19 87*125ab5d5SJiaxin Yu #define APLL_I2S3_MCK_SEL_MASK 0x1 88*125ab5d5SJiaxin Yu #define APLL_I2S3_MCK_SEL_MASK_SFT (0x1 << 19) 89*125ab5d5SJiaxin Yu #define APLL_I2S4_MCK_SEL_SFT 20 90*125ab5d5SJiaxin Yu #define APLL_I2S4_MCK_SEL_MASK 0x1 91*125ab5d5SJiaxin Yu #define APLL_I2S4_MCK_SEL_MASK_SFT (0x1 << 20) 92*125ab5d5SJiaxin Yu #define APLL_I2S5_MCK_SEL_SFT 21 93*125ab5d5SJiaxin Yu #define APLL_I2S5_MCK_SEL_MASK 0x1 94*125ab5d5SJiaxin Yu #define APLL_I2S5_MCK_SEL_MASK_SFT (0x1 << 21) 95*125ab5d5SJiaxin Yu #define APLL_I2S6_MCK_SEL_SFT 22 96*125ab5d5SJiaxin Yu #define APLL_I2S6_MCK_SEL_MASK 0x1 97*125ab5d5SJiaxin Yu #define APLL_I2S6_MCK_SEL_MASK_SFT (0x1 << 22) 98*125ab5d5SJiaxin Yu #define APLL_I2S7_MCK_SEL_SFT 23 99*125ab5d5SJiaxin Yu #define APLL_I2S7_MCK_SEL_MASK 0x1 100*125ab5d5SJiaxin Yu #define APLL_I2S7_MCK_SEL_MASK_SFT (0x1 << 23) 101*125ab5d5SJiaxin Yu #define APLL_I2S8_MCK_SEL_SFT 24 102*125ab5d5SJiaxin Yu #define APLL_I2S8_MCK_SEL_MASK 0x1 103*125ab5d5SJiaxin Yu #define APLL_I2S8_MCK_SEL_MASK_SFT (0x1 << 24) 104*125ab5d5SJiaxin Yu #define APLL_I2S9_MCK_SEL_SFT 25 105*125ab5d5SJiaxin Yu #define APLL_I2S9_MCK_SEL_MASK 0x1 106*125ab5d5SJiaxin Yu #define APLL_I2S9_MCK_SEL_MASK_SFT (0x1 << 25) 107*125ab5d5SJiaxin Yu 108*125ab5d5SJiaxin Yu /* CLK_AUDDIV_2 */ 109*125ab5d5SJiaxin Yu #define APLL12_CK_DIV0_SFT 0 110*125ab5d5SJiaxin Yu #define APLL12_CK_DIV0_MASK 0xff 111*125ab5d5SJiaxin Yu #define APLL12_CK_DIV0_MASK_SFT (0xff << 0) 112*125ab5d5SJiaxin Yu #define APLL12_CK_DIV1_SFT 8 113*125ab5d5SJiaxin Yu #define APLL12_CK_DIV1_MASK 0xff 114*125ab5d5SJiaxin Yu #define APLL12_CK_DIV1_MASK_SFT (0xff << 8) 115*125ab5d5SJiaxin Yu #define APLL12_CK_DIV2_SFT 16 116*125ab5d5SJiaxin Yu #define APLL12_CK_DIV2_MASK 0xff 117*125ab5d5SJiaxin Yu #define APLL12_CK_DIV2_MASK_SFT (0xff << 16) 118*125ab5d5SJiaxin Yu #define APLL12_CK_DIV3_SFT 24 119*125ab5d5SJiaxin Yu #define APLL12_CK_DIV3_MASK 0xff 120*125ab5d5SJiaxin Yu #define APLL12_CK_DIV3_MASK_SFT (0xff << 24) 121*125ab5d5SJiaxin Yu 122*125ab5d5SJiaxin Yu /* CLK_AUDDIV_3 */ 123*125ab5d5SJiaxin Yu #define APLL12_CK_DIV4_SFT 0 124*125ab5d5SJiaxin Yu #define APLL12_CK_DIV4_MASK 0xff 125*125ab5d5SJiaxin Yu #define APLL12_CK_DIV4_MASK_SFT (0xff << 0) 126*125ab5d5SJiaxin Yu #define APLL12_CK_DIVB_SFT 8 127*125ab5d5SJiaxin Yu #define APLL12_CK_DIVB_MASK 0xff 128*125ab5d5SJiaxin Yu #define APLL12_CK_DIVB_MASK_SFT (0xff << 8) 129*125ab5d5SJiaxin Yu #define APLL12_CK_DIV5_SFT 16 130*125ab5d5SJiaxin Yu #define APLL12_CK_DIV5_MASK 0xff 131*125ab5d5SJiaxin Yu #define APLL12_CK_DIV5_MASK_SFT (0xff << 16) 132*125ab5d5SJiaxin Yu #define APLL12_CK_DIV6_SFT 24 133*125ab5d5SJiaxin Yu #define APLL12_CK_DIV6_MASK 0xff 134*125ab5d5SJiaxin Yu #define APLL12_CK_DIV6_MASK_SFT (0xff << 24) 135*125ab5d5SJiaxin Yu 136*125ab5d5SJiaxin Yu /* CLK_AUDDIV_4 */ 137*125ab5d5SJiaxin Yu #define APLL12_CK_DIV7_SFT 0 138*125ab5d5SJiaxin Yu #define APLL12_CK_DIV7_MASK 0xff 139*125ab5d5SJiaxin Yu #define APLL12_CK_DIV7_MASK_SFT (0xff << 0) 140*125ab5d5SJiaxin Yu #define APLL12_CK_DIV8_SFT 8 141*125ab5d5SJiaxin Yu #define APLL12_CK_DIV8_MASK 0xff 142*125ab5d5SJiaxin Yu #define APLL12_CK_DIV8_MASK_SFT (0xff << 0) 143*125ab5d5SJiaxin Yu #define APLL12_CK_DIV9_SFT 16 144*125ab5d5SJiaxin Yu #define APLL12_CK_DIV9_MASK 0xff 145*125ab5d5SJiaxin Yu #define APLL12_CK_DIV9_MASK_SFT (0xff << 0) 146*125ab5d5SJiaxin Yu 147*125ab5d5SJiaxin Yu /* AUD_TOP_CFG */ 148*125ab5d5SJiaxin Yu #define AUD_TOP_CFG_SFT 0 149*125ab5d5SJiaxin Yu #define AUD_TOP_CFG_MASK 0xffffffff 150*125ab5d5SJiaxin Yu #define AUD_TOP_CFG_MASK_SFT (0xffffffff << 0) 151*125ab5d5SJiaxin Yu 152*125ab5d5SJiaxin Yu /* AUD_TOP_MON */ 153*125ab5d5SJiaxin Yu #define AUD_TOP_MON_SFT 0 154*125ab5d5SJiaxin Yu #define AUD_TOP_MON_MASK 0xffffffff 155*125ab5d5SJiaxin Yu #define AUD_TOP_MON_MASK_SFT (0xffffffff << 0) 156*125ab5d5SJiaxin Yu 157*125ab5d5SJiaxin Yu /* CLK_AUDDIV_3 */ 158*125ab5d5SJiaxin Yu #define APLL12_CK_DIV5_MSB_SFT 0 159*125ab5d5SJiaxin Yu #define APLL12_CK_DIV5_MSB_MASK 0xf 160*125ab5d5SJiaxin Yu #define APLL12_CK_DIV5_MSB_MASK_SFT (0xf << 0) 161*125ab5d5SJiaxin Yu #define RESERVED0_SFT 4 162*125ab5d5SJiaxin Yu #define RESERVED0_MASK 0xfffffff 163*125ab5d5SJiaxin Yu #define RESERVED0_MASK_SFT (0xfffffff << 4) 164*125ab5d5SJiaxin Yu 165*125ab5d5SJiaxin Yu /* APLL */ 166*125ab5d5SJiaxin Yu #define APLL1_W_NAME "APLL1" 167*125ab5d5SJiaxin Yu #define APLL2_W_NAME "APLL2" 168*125ab5d5SJiaxin Yu enum { 169*125ab5d5SJiaxin Yu MT8192_APLL1 = 0, 170*125ab5d5SJiaxin Yu MT8192_APLL2, 171*125ab5d5SJiaxin Yu }; 172*125ab5d5SJiaxin Yu 173*125ab5d5SJiaxin Yu enum { 174*125ab5d5SJiaxin Yu CLK_AFE = 0, 175*125ab5d5SJiaxin Yu CLK_TML, 176*125ab5d5SJiaxin Yu CLK_APLL22M, 177*125ab5d5SJiaxin Yu CLK_APLL24M, 178*125ab5d5SJiaxin Yu CLK_APLL1_TUNER, 179*125ab5d5SJiaxin Yu CLK_APLL2_TUNER, 180*125ab5d5SJiaxin Yu CLK_NLE, 181*125ab5d5SJiaxin Yu CLK_INFRA_SYS_AUDIO, 182*125ab5d5SJiaxin Yu CLK_INFRA_AUDIO_26M, 183*125ab5d5SJiaxin Yu CLK_MUX_AUDIO, 184*125ab5d5SJiaxin Yu CLK_MUX_AUDIOINTBUS, 185*125ab5d5SJiaxin Yu CLK_TOP_MAINPLL_D4_D4, 186*125ab5d5SJiaxin Yu /* apll related mux */ 187*125ab5d5SJiaxin Yu CLK_TOP_MUX_AUD_1, 188*125ab5d5SJiaxin Yu CLK_TOP_APLL1_CK, 189*125ab5d5SJiaxin Yu CLK_TOP_MUX_AUD_2, 190*125ab5d5SJiaxin Yu CLK_TOP_APLL2_CK, 191*125ab5d5SJiaxin Yu CLK_TOP_MUX_AUD_ENG1, 192*125ab5d5SJiaxin Yu CLK_TOP_APLL1_D4, 193*125ab5d5SJiaxin Yu CLK_TOP_MUX_AUD_ENG2, 194*125ab5d5SJiaxin Yu CLK_TOP_APLL2_D4, 195*125ab5d5SJiaxin Yu CLK_TOP_MUX_AUDIO_H, 196*125ab5d5SJiaxin Yu CLK_TOP_I2S0_M_SEL, 197*125ab5d5SJiaxin Yu CLK_TOP_I2S1_M_SEL, 198*125ab5d5SJiaxin Yu CLK_TOP_I2S2_M_SEL, 199*125ab5d5SJiaxin Yu CLK_TOP_I2S3_M_SEL, 200*125ab5d5SJiaxin Yu CLK_TOP_I2S4_M_SEL, 201*125ab5d5SJiaxin Yu CLK_TOP_I2S5_M_SEL, 202*125ab5d5SJiaxin Yu CLK_TOP_I2S6_M_SEL, 203*125ab5d5SJiaxin Yu CLK_TOP_I2S7_M_SEL, 204*125ab5d5SJiaxin Yu CLK_TOP_I2S8_M_SEL, 205*125ab5d5SJiaxin Yu CLK_TOP_I2S9_M_SEL, 206*125ab5d5SJiaxin Yu CLK_TOP_APLL12_DIV0, 207*125ab5d5SJiaxin Yu CLK_TOP_APLL12_DIV1, 208*125ab5d5SJiaxin Yu CLK_TOP_APLL12_DIV2, 209*125ab5d5SJiaxin Yu CLK_TOP_APLL12_DIV3, 210*125ab5d5SJiaxin Yu CLK_TOP_APLL12_DIV4, 211*125ab5d5SJiaxin Yu CLK_TOP_APLL12_DIVB, 212*125ab5d5SJiaxin Yu CLK_TOP_APLL12_DIV5, 213*125ab5d5SJiaxin Yu CLK_TOP_APLL12_DIV6, 214*125ab5d5SJiaxin Yu CLK_TOP_APLL12_DIV7, 215*125ab5d5SJiaxin Yu CLK_TOP_APLL12_DIV8, 216*125ab5d5SJiaxin Yu CLK_TOP_APLL12_DIV9, 217*125ab5d5SJiaxin Yu CLK_CLK26M, 218*125ab5d5SJiaxin Yu CLK_NUM 219*125ab5d5SJiaxin Yu }; 220*125ab5d5SJiaxin Yu 221*125ab5d5SJiaxin Yu struct mtk_base_afe; 222*125ab5d5SJiaxin Yu 223*125ab5d5SJiaxin Yu int mt8192_init_clock(struct mtk_base_afe *afe); 224*125ab5d5SJiaxin Yu int mt8192_afe_enable_clock(struct mtk_base_afe *afe); 225*125ab5d5SJiaxin Yu void mt8192_afe_disable_clock(struct mtk_base_afe *afe); 226*125ab5d5SJiaxin Yu 227*125ab5d5SJiaxin Yu int mt8192_apll1_enable(struct mtk_base_afe *afe); 228*125ab5d5SJiaxin Yu void mt8192_apll1_disable(struct mtk_base_afe *afe); 229*125ab5d5SJiaxin Yu 230*125ab5d5SJiaxin Yu int mt8192_apll2_enable(struct mtk_base_afe *afe); 231*125ab5d5SJiaxin Yu void mt8192_apll2_disable(struct mtk_base_afe *afe); 232*125ab5d5SJiaxin Yu 233*125ab5d5SJiaxin Yu int mt8192_get_apll_rate(struct mtk_base_afe *afe, int apll); 234*125ab5d5SJiaxin Yu int mt8192_get_apll_by_rate(struct mtk_base_afe *afe, int rate); 235*125ab5d5SJiaxin Yu int mt8192_get_apll_by_name(struct mtk_base_afe *afe, const char *name); 236*125ab5d5SJiaxin Yu 237*125ab5d5SJiaxin Yu /* these will be replaced by using CCF */ 238*125ab5d5SJiaxin Yu int mt8192_mck_enable(struct mtk_base_afe *afe, int mck_id, int rate); 239*125ab5d5SJiaxin Yu void mt8192_mck_disable(struct mtk_base_afe *afe, int mck_id); 240*125ab5d5SJiaxin Yu 241*125ab5d5SJiaxin Yu int mt8192_set_audio_int_bus_parent(struct mtk_base_afe *afe, 242*125ab5d5SJiaxin Yu int clk_id); 243*125ab5d5SJiaxin Yu 244*125ab5d5SJiaxin Yu #endif 245