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/openbmc/linux/Documentation/devicetree/bindings/timestamp/
H A Dnvidia,tegra194-hte.yaml19 GPIO lines from the AON (always on) GPIO controller.
24 - nvidia,tegra194-gte-aon
26 - nvidia,tegra234-gte-aon
49 property and the value depends on the HTE instance in the chip. The AON
57 The phandle to AON gpio controller instance. This is required to handle
80 - nvidia,tegra194-gte-aon
81 - nvidia,tegra234-gte-aon
114 - nvidia,tegra234-gte-aon
124 compatible = "nvidia,tegra194-gte-aon";
/openbmc/linux/drivers/clk/sprd/
H A Dsc9860-clk.c500 static SPRD_COMP_CLK(aon_apb, "aon-apb", aon_apb_parents, 0x230,
602 static SPRD_MUX_CLK(aon_i2c, "aon-i2c", cm3_i2c_parents, 0x280,
826 static SPRD_SC_GATE_CLK(avs_lit_eb, "avs-lit-eb", "aon-apb", 0x0,
828 static SPRD_SC_GATE_CLK(avs_big_eb, "avs-big-eb", "aon-apb", 0x0,
830 static SPRD_SC_GATE_CLK(ap_intc5_eb, "ap-intc5-eb", "aon-apb", 0x0,
832 static SPRD_SC_GATE_CLK(gpio_eb, "gpio-eb", "aon-apb", 0x0,
834 static SPRD_SC_GATE_CLK(pwm0_eb, "pwm0-eb", "aon-apb", 0x0,
836 static SPRD_SC_GATE_CLK(pwm1_eb, "pwm1-eb", "aon-apb", 0x0,
838 static SPRD_SC_GATE_CLK(pwm2_eb, "pwm2-eb", "aon-apb", 0x0,
840 static SPRD_SC_GATE_CLK(pwm3_eb, "pwm3-eb", "aon-apb", 0x0,
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mips/brcm/
H A Dsoc.txt21 = Always-On control block (AON CTRL)
28 "brcm,bcm7425-aon-ctrl"
29 "brcm,bcm7429-aon-ctrl"
30 "brcm,bcm7435-aon-ctrl" and
31 "brcm,brcmstb-aon-ctrl"
32 - reg : the register start and length for the AON CTRL block
37 compatible = "brcm,bcm7425-aon-ctrl", "brcm,brcmstb-aon-ctrl";
/openbmc/linux/drivers/clk/ti/
H A Dclk-33xx.c151 "l3-aon-clkctrl:0000:19",
152 "l3-aon-clkctrl:0000:30",
157 "l3-aon-clkctrl:0000:20",
167 "l3-aon-clkctrl:0000:22",
192 { AM3_L3_AON_DEBUGSS_CLKCTRL, am3_debugss_bit_data, CLKF_SW_SUP, "l3-aon-clkctrl:0000:24" },
244 DT_CLK(NULL, "dbg_clka_ck", "l3-aon-clkctrl:0000:30"),
245 DT_CLK(NULL, "dbg_sysclk_ck", "l3-aon-clkctrl:0000:19"),
250 DT_CLK(NULL, "stm_clk_div_ck", "l3-aon-clkctrl:0000:27"),
251 DT_CLK(NULL, "stm_pmd_clock_mux_ck", "l3-aon-clkctrl:0000:22"),
252 DT_CLK(NULL, "trace_clk_div_ck", "l3-aon-clkctrl:0000:24"),
[all …]
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dbrcm,kona-ccu.txt60 "brcm,bcm11351-aon-ccu"
75 aon hub_timer peri 0 BCM281XX_AON_CCU_HUB_TIMER
76 aon pmu_bsc peri 1 BCM281XX_AON_CCU_PMU_BSC
77 aon pmu_bsc_var peri 2 BCM281XX_AON_CCU_PMU_BSC_VAR
106 "brcm,bcm21664-aon-ccu"
120 aon hub_timer peri 0 BCM21664_AON_CCU_HUB_TIMER
H A Dsprd,sc9860-clk.txt9 - "sprd,sc9860-aon-prediv"
11 - "sprd,sc9860-aon-gate"
/openbmc/linux/Documentation/devicetree/bindings/gpio/
H A Dnvidia,tegra186-gpio.yaml14 Tegra186 contains two GPIO controllers; a main controller and an "AON"
83 - nvidia,tegra186-gpio-aon
85 - nvidia,tegra194-gpio-aon
87 - nvidia,tegra234-gpio-aon
166 - nvidia,tegra186-gpio-aon
167 - nvidia,tegra194-gpio-aon
168 - nvidia,tegra234-gpio-aon
205 compatible = "nvidia,tegra186-gpio-aon";
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dnvidia,tegra234-pinmux-aon.yaml4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra234-pinmux-aon.yaml#
7 title: NVIDIA Tegra234 AON Pinmux Controller
17 const: nvidia,tegra234-pinmux-aon
65 compatible = "nvidia,tegra234-pinmux-aon";
H A Dstarfive,jh7110-aon-pinctrl.yaml4 $id: http://devicetree.org/schemas/pinctrl/starfive,jh7110-aon-pinctrl.yaml#
7 title: StarFive JH7110 AON Pin Controller
22 const: starfive,jh7110-aon-pinctrl
103 compatible = "starfive,jh7110-aon-pinctrl";
/openbmc/linux/drivers/clk/bcm/
H A Dclk-iproc-pll.c187 val = readl(pll->control_base + ctrl->aon.offset); in __pll_disable()
188 val |= bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift; in __pll_disable()
189 iproc_pll_write(pll, pll->control_base, ctrl->aon.offset, val); in __pll_disable()
194 val = readl(pll->pwr_base + ctrl->aon.offset); in __pll_disable()
195 val |= 1 << ctrl->aon.iso_shift; in __pll_disable()
196 iproc_pll_write(pll, pll->pwr_base, ctrl->aon.offset, val); in __pll_disable()
199 val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); in __pll_disable()
200 iproc_pll_write(pll, pll->pwr_base, ctrl->aon.offset, val); in __pll_disable()
210 val = readl(pll->control_base + ctrl->aon.offset); in __pll_enable()
211 val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); in __pll_enable()
[all …]
H A Dclk-bcm281xx.c31 /* AON CCU */
61 BCM281XX_CCU_COMMON(aon, AON),
64 KONA_CLK(aon, hub_timer, peri),
66 KONA_CLK(aon, pmu_bsc, peri),
68 KONA_CLK(aon, pmu_bsc_var, peri),
H A Dclk-sr.c37 .aon = AON_VAL(0x0, 5, 1, 0),
97 .aon = AON_VAL(0x0, 1, 13, 12),
156 .aon = AON_VAL(0x0, 1, 19, 18),
191 .aon = AON_VAL(0x0, 1, 25, 24),
245 .aon = AON_VAL(0x0, 1, 1, 0),
283 .aon = AON_VAL(0x0, 2, 19, 18),
328 .aon = AON_VAL(0x0, 2, 22, 21),
367 .aon = AON_VAL(0x0, 2, 25, 24),
H A Dclk-bcm21664.c30 /* AON CCU */
43 BCM21664_CCU_COMMON(aon, AON),
50 KONA_CLK(aon, hub_timer, peri),
/openbmc/qemu/hw/riscv/
H A Dsifive_e.c12 * 4) Registers emulated as RAM: AON, GPIO, QSPI, PWM
188 object_initialize_child(obj, "riscv.sifive.e.aon", &s->aon, in type_init()
230 /* AON */ in sifive_e_soc_realize()
232 if (!sysbus_realize(SYS_BUS_DEVICE(&s->aon), errp)) { in sifive_e_soc_realize()
236 /* Map AON registers */ in sifive_e_soc_realize()
237 sysbus_mmio_map(SYS_BUS_DEVICE(&s->aon), 0, memmap[SIFIVE_E_DEV_AON].base); in sifive_e_soc_realize()
257 sysbus_connect_irq(SYS_BUS_DEVICE(&s->aon), 0, in sifive_e_soc_realize()
/openbmc/linux/Documentation/devicetree/bindings/soc/starfive/
H A Dstarfive,jh7110-syscon.yaml25 - starfive,jh7110-aon-syscon
59 const: starfive,jh7110-aon-syscon
88 compatible = "starfive,jh7110-aon-syscon", "syscon";
/openbmc/qemu/tests/qtest/
H A Dsifive-e-aon-watchdog-test.c429 qtest_add_func("/sifive-e-aon-watchdog-test/wdogcount", in main()
431 qtest_add_func("/sifive-e-aon-watchdog-test/wdogcfg", in main()
433 qtest_add_func("/sifive-e-aon-watchdog-test/wdogcmp0", in main()
435 qtest_add_func("/sifive-e-aon-watchdog-test/wdogkey", in main()
437 qtest_add_func("/sifive-e-aon-watchdog-test/wdogfeed", in main()
439 qtest_add_func("/sifive-e-aon-watchdog-test/scaled_wdogs", in main()
441 qtest_add_func("/sifive-e-aon-watchdog-test/watchdog", in main()
443 qtest_add_func("/sifive-e-aon-watchdog-test/scaled_watchdog", in main()
445 qtest_add_func("/sifive-e-aon-watchdog-test/periodic_int", in main()
447 qtest_add_func("/sifive-e-aon-watchdog-test/enable_disable", in main()
/openbmc/linux/drivers/pinctrl/starfive/
H A Dpinctrl-starfive-jh7110-aon.c3 * Pinctrl / GPIO driver for StarFive JH7110 SoC aon controller
159 .compatible = "starfive,jh7110-aon-pinctrl",
169 .name = "starfive-jh7110-aon-pinctrl",
176 MODULE_DESCRIPTION("Pinctrl driver for the StarFive JH7110 SoC aon controller");
/openbmc/linux/Documentation/devicetree/bindings/arm/bcm/
H A Dbrcm,brcmstb.txt128 = Always-On control block (AON CTRL)
134 - compatible : should contain "brcm,brcmstb-aon-ctrl"
135 - reg : the register start and length for the AON CTRL block
139 aon-ctrl@410000 {
140 compatible = "brcm,brcmstb-aon-ctrl";
/openbmc/u-boot/doc/device-tree-bindings/gpio/
H A Dnvidia,tegra186-gpio.txt3 Tegra186 contains two GPIO controllers; a main controller and an "AON"
70 - "nvidia,tegra186-gpio-aon".
93 - "nvidia,tegra186-gpio-aon": 1 entry.
150 compatible = "nvidia,tegra186-gpio-aon";
/openbmc/linux/include/dt-bindings/clock/
H A Dbcm21664.h17 #define BCM21664_DT_AON_CCU_COMPAT "brcm,bcm21664-aon-ccu"
26 /* aon CCU clock ids */
H A Dbcm281xx.h22 #define BCM281XX_DT_AON_CCU_COMPAT "brcm,bcm11351-aon-ccu"
32 /* aon CCU clock ids */
/openbmc/qemu/include/hw/misc/
H A Dsifive_e_aon.h2 * SiFive HiFive1 AON (Always On Domain) interface.
25 #define TYPE_SIFIVE_E_AON "riscv.sifive.e.aon"
/openbmc/linux/Documentation/devicetree/bindings/arm/omap/
H A Dprcm.txt22 "ti,omap5-cm-core-aon"
26 "ti,dra7-cm-core-aon"
/openbmc/linux/Documentation/devicetree/bindings/mtd/
H A Dqcom,nandc.yaml32 - const: aon
157 clock-names = "core", "aon";
200 clock-names = "core", "aon";
/openbmc/linux/Documentation/devicetree/bindings/ufs/
H A Dsprd,ums9620-ufs.yaml47 sprd,aon-apb-syscon:
78 sprd,aon-apb-syscon = <&aon_apb_regs>;

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