1af583852SDipen Patel# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2af583852SDipen Patel%YAML 1.2 3af583852SDipen Patel--- 45dad4eccSDipen Patel$id: http://devicetree.org/schemas/timestamp/nvidia,tegra194-hte.yaml# 5af583852SDipen Patel$schema: http://devicetree.org/meta-schemas/core.yaml# 6af583852SDipen Patel 7d0672fa4SDipen Pateltitle: Tegra on chip generic hardware timestamping engine (HTE) provider 8af583852SDipen Patel 9af583852SDipen Patelmaintainers: 10af583852SDipen Patel - Dipen Patel <dipenp@nvidia.com> 11af583852SDipen Patel 12af583852SDipen Pateldescription: 13af583852SDipen Patel Tegra SoC has two instances of generic hardware timestamping engines (GTE) 14af583852SDipen Patel known as GTE GPIO and GTE IRQ, which can monitor subset of GPIO and on chip 15af583852SDipen Patel IRQ lines for the state change respectively, upon detection it will record 16af583852SDipen Patel timestamp (taken from system counter) in its internal hardware FIFO. It has 17af583852SDipen Patel a bitmap array arranged in 32bit slices where each bit represent signal/line 18af583852SDipen Patel to enable or disable for the hardware timestamping. The GTE GPIO monitors 19af583852SDipen Patel GPIO lines from the AON (always on) GPIO controller. 20af583852SDipen Patel 21af583852SDipen Patelproperties: 22af583852SDipen Patel compatible: 23af583852SDipen Patel enum: 24af583852SDipen Patel - nvidia,tegra194-gte-aon 25af583852SDipen Patel - nvidia,tegra194-gte-lic 26d0672fa4SDipen Patel - nvidia,tegra234-gte-aon 27d0672fa4SDipen Patel - nvidia,tegra234-gte-lic 28af583852SDipen Patel 29af583852SDipen Patel reg: 30af583852SDipen Patel maxItems: 1 31af583852SDipen Patel 32af583852SDipen Patel interrupts: 33af583852SDipen Patel maxItems: 1 34af583852SDipen Patel 35af583852SDipen Patel nvidia,int-threshold: 36af583852SDipen Patel $ref: /schemas/types.yaml#/definitions/uint32 37af583852SDipen Patel description: 38af583852SDipen Patel HTE device generates its interrupt based on this u32 FIFO threshold 39af583852SDipen Patel value. The recommended value is 1. 40af583852SDipen Patel minimum: 1 41af583852SDipen Patel maximum: 256 42af583852SDipen Patel 43af583852SDipen Patel nvidia,slices: 44af583852SDipen Patel $ref: /schemas/types.yaml#/definitions/uint32 45*1815e37bSDipen Patel deprecated: true 46af583852SDipen Patel description: 47af583852SDipen Patel HTE lines are arranged in 32 bit slice where each bit represents different 48af583852SDipen Patel line/signal that it can enable/configure for the timestamp. It is u32 49*1815e37bSDipen Patel property and the value depends on the HTE instance in the chip. The AON 50*1815e37bSDipen Patel GTE instances for both Tegra194 and Tegra234 has 3 slices. The Tegra194 51*1815e37bSDipen Patel LIC instance has 11 slices and Tegra234 LIC has 17 slices. 52d0672fa4SDipen Patel enum: [3, 11, 17] 53d0672fa4SDipen Patel 54d0672fa4SDipen Patel nvidia,gpio-controller: 55d0672fa4SDipen Patel $ref: /schemas/types.yaml#/definitions/phandle 56d0672fa4SDipen Patel description: 57d0672fa4SDipen Patel The phandle to AON gpio controller instance. This is required to handle 58d0672fa4SDipen Patel namespace conversion between GPIO and GTE. 59af583852SDipen Patel 60af583852SDipen Patel '#timestamp-cells': 61af583852SDipen Patel description: 62af583852SDipen Patel This represents number of line id arguments as specified by the 63af583852SDipen Patel consumers. For the GTE IRQ, this is IRQ number as mentioned in the 64af583852SDipen Patel SoC technical reference manual. For the GTE GPIO, its value is same as 65af583852SDipen Patel mentioned in the nvidia GPIO device tree binding document. 66af583852SDipen Patel const: 1 67af583852SDipen Patel 68af583852SDipen Patelrequired: 69af583852SDipen Patel - compatible 70af583852SDipen Patel - reg 71af583852SDipen Patel - interrupts 72af583852SDipen Patel - "#timestamp-cells" 73af583852SDipen Patel 74d0672fa4SDipen PatelallOf: 75d0672fa4SDipen Patel - if: 76d0672fa4SDipen Patel properties: 77d0672fa4SDipen Patel compatible: 78d0672fa4SDipen Patel contains: 79d0672fa4SDipen Patel enum: 80d0672fa4SDipen Patel - nvidia,tegra194-gte-aon 81d0672fa4SDipen Patel - nvidia,tegra234-gte-aon 82d0672fa4SDipen Patel then: 83d0672fa4SDipen Patel properties: 84d0672fa4SDipen Patel nvidia,slices: 85d0672fa4SDipen Patel const: 3 86d0672fa4SDipen Patel 87d0672fa4SDipen Patel - if: 88d0672fa4SDipen Patel properties: 89d0672fa4SDipen Patel compatible: 90d0672fa4SDipen Patel contains: 91d0672fa4SDipen Patel enum: 92d0672fa4SDipen Patel - nvidia,tegra194-gte-lic 93d0672fa4SDipen Patel then: 94d0672fa4SDipen Patel properties: 95d0672fa4SDipen Patel nvidia,slices: 96d0672fa4SDipen Patel const: 11 97d0672fa4SDipen Patel 98d0672fa4SDipen Patel - if: 99d0672fa4SDipen Patel properties: 100d0672fa4SDipen Patel compatible: 101d0672fa4SDipen Patel contains: 102d0672fa4SDipen Patel enum: 103d0672fa4SDipen Patel - nvidia,tegra234-gte-lic 104d0672fa4SDipen Patel then: 105d0672fa4SDipen Patel properties: 106d0672fa4SDipen Patel nvidia,slices: 107d0672fa4SDipen Patel const: 17 108d0672fa4SDipen Patel 109d0672fa4SDipen Patel - if: 110d0672fa4SDipen Patel properties: 111d0672fa4SDipen Patel compatible: 112d0672fa4SDipen Patel contains: 113d0672fa4SDipen Patel enum: 114d0672fa4SDipen Patel - nvidia,tegra234-gte-aon 115d0672fa4SDipen Patel then: 116d0672fa4SDipen Patel required: 117d0672fa4SDipen Patel - nvidia,gpio-controller 118d0672fa4SDipen Patel 119af583852SDipen PateladditionalProperties: false 120af583852SDipen Patel 121af583852SDipen Patelexamples: 122af583852SDipen Patel - | 123af583852SDipen Patel tegra_hte_aon: timestamp@c1e0000 { 124af583852SDipen Patel compatible = "nvidia,tegra194-gte-aon"; 125af583852SDipen Patel reg = <0xc1e0000 0x10000>; 126af583852SDipen Patel interrupts = <0 13 0x4>; 127af583852SDipen Patel nvidia,int-threshold = <1>; 128af583852SDipen Patel #timestamp-cells = <1>; 129af583852SDipen Patel }; 130af583852SDipen Patel 131af583852SDipen Patel - | 132af583852SDipen Patel tegra_hte_lic: timestamp@3aa0000 { 133af583852SDipen Patel compatible = "nvidia,tegra194-gte-lic"; 134af583852SDipen Patel reg = <0x3aa0000 0x10000>; 135af583852SDipen Patel interrupts = <0 11 0x4>; 136af583852SDipen Patel nvidia,int-threshold = <1>; 137af583852SDipen Patel #timestamp-cells = <1>; 138af583852SDipen Patel }; 139af583852SDipen Patel 140af583852SDipen Patel... 141