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/openbmc/u-boot/arch/arm/dts/
H A Drk3399-sdram-ddr3-1866.dtsi8 0x1
9 0xa
10 0x3
11 0x2
12 0x1
13 0x0
14 0xf
15 0xf
17 0x80181219
18 0x17050a03
[all …]
H A Drk3399-sdram-ddr3-1333.dtsi8 0x1
9 0xa
10 0x3
11 0x2
12 0x1
13 0x0
14 0xf
15 0xf
17 0x80120e12
18 0x11030802
[all …]
H A Drk3399-sdram-ddr3-1600.dtsi8 0x1
9 0xa
10 0x3
11 0x2
12 0x1
13 0x0
14 0xf
15 0xf
17 0x80151015
18 0x14040902
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/top/
H A Dgk104.c35 for (i = 0; i < 64; i++) { in gk104_top_parse()
39 type = ~0; in gk104_top_parse()
40 inst = 0; in gk104_top_parse()
43 data = nvkm_rd32(device, 0x022700 + (i * 0x04)); in gk104_top_parse()
45 switch (data & 0x00000003) { in gk104_top_parse()
46 case 0x00000000: /* NOT_VALID */ in gk104_top_parse()
48 case 0x00000001: /* DATA */ in gk104_top_parse()
49 inst = (data & 0x3c000000) >> 26; in gk104_top_parse()
50 info->addr = (data & 0x00fff000); in gk104_top_parse()
51 if (data & 0x00000004) in gk104_top_parse()
[all …]
/openbmc/linux/arch/arm/mach-pxa/
H A Dpxa-regs.h14 #define UNCACHED_PHYS_0 0xfe000000
15 #define UNCACHED_PHYS_0_SIZE 0x00100000
20 * 0x40000000 - 0x41ffffff <--> 0xf2000000 - 0xf3ffffff
21 * 0x44000000 - 0x45ffffff <--> 0xf4000000 - 0xf5ffffff
22 * 0x48000000 - 0x49ffffff <--> 0xf6000000 - 0xf7ffffff
23 * 0x4c000000 - 0x4dffffff <--> 0xf8000000 - 0xf9ffffff
24 * 0x50000000 - 0x51ffffff <--> 0xfa000000 - 0xfbffffff
25 * 0x54000000 - 0x55ffffff <--> 0xfc000000 - 0xfdffffff
26 * 0x58000000 - 0x59ffffff <--> 0xfe000000 - 0xffffffff
31 #define io_v2p(x) (0x3c000000 + ((x) & 0x01ffffff) + (((x) & 0x0e000000) << 1))
[all …]
/openbmc/linux/arch/mips/lantiq/falcon/
H A Dprom.c25 #define PART_MASK 0x0FFFF000
27 #define REV_MASK 0xF0000000
29 #define SREV_MASK 0x03C00000
31 #define TYPE_MASK 0x3C000000
34 #define BOOT_REG_BASE (KSEG1 | 0x1F200000)
35 #define BOOT_RVEC (BOOT_REG_BASE | 0x00)
36 #define BOOT_NVEC (BOOT_REG_BASE | 0x04)
37 #define BOOT_EVEC (BOOT_REG_BASE | 0x08)
61 sprintf(i->rev_type, "%c%d%d", (i->srev & 0x4) ? ('B') : ('A'), in ltq_soc_detect()
62 i->rev & 0x7, (i->srev & 0x3) + 1); in ltq_soc_detect()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/soc/ti/
H A Dk3-ringacc.yaml84 reg = <0x0 0x3c000000 0x0 0x400000>,
85 <0x0 0x38000000 0x0 0x400000>,
86 <0x0 0x31120000 0x0 0x100>,
87 <0x0 0x33000000 0x0 0x40000>,
88 <0x0 0x31080000 0x0 0x40000>;
91 ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */
/openbmc/linux/arch/arm/boot/dts/broadcom/
H A Dbcm958522er.dts48 reg = <0x60000000 0x80000000>;
78 nand@0 {
80 reg = <0>;
91 partition@0 {
93 reg = <0x00000000 0x00200000>;
98 reg = <0x00200000 0x00400000>;
102 reg = <0x00600000 0x00a00000>;
106 reg = <0x01000000 0x03000000>;
110 reg = <0x04000000 0x3c000000>;
129 pinctrl-0 = <&nand_sel>;
[all …]
H A Dbcm958525er.dts48 reg = <0x60000000 0x80000000>;
78 nand@0 {
80 reg = <0>;
91 partition@0 {
93 reg = <0x00000000 0x00200000>;
98 reg = <0x00200000 0x00400000>;
102 reg = <0x00600000 0x00a00000>;
106 reg = <0x01000000 0x03000000>;
110 reg = <0x04000000 0x3c000000>;
129 pinctrl-0 = <&nand_sel>;
[all …]
H A Dbcm958525xmc.dts48 reg = <0x60000000 0x40000000>;
78 reg = <0x4c>;
83 reg = <0x52>;
89 reg = <0x68>;
94 nand@0 {
96 reg = <0>;
107 partition@0 {
109 reg = <0x00000000 0x00200000>;
114 reg = <0x00200000 0x00400000>;
118 reg = <0x00600000 0x00a00000>;
[all …]
H A Dbcm958622hr.dts48 reg = <0x60000000 0x80000000>;
82 nand@0 {
84 reg = <0>;
95 partition@0 {
97 reg = <0x00000000 0x00200000>;
102 reg = <0x00200000 0x00400000>;
106 reg = <0x00600000 0x00a00000>;
110 reg = <0x01000000 0x03000000>;
114 reg = <0x04000000 0x3c000000>;
133 pinctrl-0 = <&nand_sel>;
[all …]
H A Dbcm988312hr.dts48 reg = <0x60000000 0x80000000>;
82 nand@0 {
84 reg = <0>;
95 partition@0 {
97 reg = <0x00000000 0x00200000>;
102 reg = <0x00200000 0x00400000>;
106 reg = <0x00600000 0x00a00000>;
110 reg = <0x01000000 0x03000000>;
114 reg = <0x04000000 0x3c000000>;
133 pinctrl-0 = <&nand_sel>;
[all …]
H A Dbcm958625hr.dts48 reg = <0x60000000 0x20000000>;
93 nand@0 {
95 reg = <0>;
106 partition@0 {
108 reg = <0x00000000 0x00200000>;
113 reg = <0x00200000 0x00400000>;
117 reg = <0x00600000 0x00a00000>;
121 reg = <0x01000000 0x03000000>;
125 reg = <0x04000000 0x3c000000>;
144 pinctrl-0 = <&nand_sel>;
[all …]
H A Dbcm958623hr.dts48 reg = <0x60000000 0x80000000>;
82 nand@0 {
84 reg = <0>;
95 partition@0 {
97 reg = <0x00000000 0x00200000>;
102 reg = <0x00200000 0x00400000>;
106 reg = <0x00600000 0x00a00000>;
110 reg = <0x01000000 0x03000000>;
114 reg = <0x04000000 0x3c000000>;
133 pinctrl-0 = <&nand_sel>;
[all …]
H A Dbcm958625k.dts47 reg = <0x60000000 0x80000000>;
72 nand@0 {
74 reg = <0>;
85 partition@0 {
87 reg = <0x00000000 0x00200000>;
92 reg = <0x00200000 0x00400000>;
96 reg = <0x00600000 0x00a00000>;
100 reg = <0x01000000 0x03000000>;
104 reg = <0x04000000 0x3c000000>;
127 pinctrl-0 = <&nand_sel>, <&gpiobs>, <&pwmc>;
[all …]
/openbmc/u-boot/board/freescale/ls2080ardb/
H A DREADME57 0x00_0000_0000 .. 0x00_000F_FFFF Boot Rom
58 0x00_0100_0000 .. 0x00_0FFF_FFFF CCSR
59 0x00_1800_0000 .. 0x00_181F_FFFF OCRAM
60 0x00_2000_0000 .. 0x00_2FFF_FFFF QSPI region #1
61 0x00_3000_0000 .. 0x00_3FFF_FFFF IFC region #1
62 0x00_8000_0000 .. 0x00_FFFF_FFFF DDR region #1
63 0x05_1000_0000 .. 0x05_FFFF_FFFF IFC region #2
64 0x80_8000_0000 .. 0xFF_FFFF_FFFF DDR region #2
72 0x30000000 - 0x37ffffff : 128MB : NOR flash
73 0x3C000000 - 0x40000000 : 64MB : CPLD
[all …]
/openbmc/u-boot/include/configs/
H A Dls2080a_common.h20 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
29 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
30 #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
31 #define CONFIG_ENV_SECT_SIZE 0x40000
44 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
45 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
47 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
57 #define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL
59 * DDR controller use 0 as the base address for binding.
62 #define CONFIG_SYS_DP_DDR_BASE_PHY 0
[all …]
H A Dls1088a_common.h29 #define LS1088ARDB_PB_BOARD 0x4A
34 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
39 #define CONFIG_SYS_FSL_QSPI_BASE 0x20000000
42 #define CONFIG_SYS_FSL_QSPI_BASE 0x20000000
43 #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
52 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
53 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
55 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
75 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
86 * During booting, IFC is mapped at the region of 0x30000000.
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_1_default.h26 #define mmSDMA0_UCODE_ADDR_DEFAULT 0x00000000
27 #define mmSDMA0_UCODE_DATA_DEFAULT 0x00000000
28 #define mmSDMA0_VM_CNTL_DEFAULT 0x00000000
29 #define mmSDMA0_VM_CTX_LO_DEFAULT 0x00000000
30 #define mmSDMA0_VM_CTX_HI_DEFAULT 0x00000000
31 #define mmSDMA0_ACTIVE_FCN_ID_DEFAULT 0x00000000
32 #define mmSDMA0_VM_CTX_CNTL_DEFAULT 0x00000000
33 #define mmSDMA0_VIRT_RESET_REQ_DEFAULT 0x00000000
34 #define mmSDMA0_CONTEXT_REG_TYPE0_DEFAULT 0xfffdf79f
35 #define mmSDMA0_CONTEXT_REG_TYPE1_DEFAULT 0x003fbcff
[all …]
H A Dsdma0_4_0_default.h26 #define mmSDMA0_UCODE_ADDR_DEFAULT 0x00000000
27 #define mmSDMA0_UCODE_DATA_DEFAULT 0x00000000
28 #define mmSDMA0_VM_CNTL_DEFAULT 0x00000000
29 #define mmSDMA0_VM_CTX_LO_DEFAULT 0x00000000
30 #define mmSDMA0_VM_CTX_HI_DEFAULT 0x00000000
31 #define mmSDMA0_ACTIVE_FCN_ID_DEFAULT 0x00000000
32 #define mmSDMA0_VM_CTX_CNTL_DEFAULT 0x00000000
33 #define mmSDMA0_VIRT_RESET_REQ_DEFAULT 0x00000000
34 #define mmSDMA0_VF_ENABLE_DEFAULT 0x00000000
35 #define mmSDMA0_CONTEXT_REG_TYPE0_DEFAULT 0xfffdf79f
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/sdma1/
H A Dsdma1_4_0_default.h26 #define mmSDMA1_UCODE_ADDR_DEFAULT 0x00000000
27 #define mmSDMA1_UCODE_DATA_DEFAULT 0x00000000
28 #define mmSDMA1_VM_CNTL_DEFAULT 0x00000000
29 #define mmSDMA1_VM_CTX_LO_DEFAULT 0x00000000
30 #define mmSDMA1_VM_CTX_HI_DEFAULT 0x00000000
31 #define mmSDMA1_ACTIVE_FCN_ID_DEFAULT 0x00000000
32 #define mmSDMA1_VM_CTX_CNTL_DEFAULT 0x00000000
33 #define mmSDMA1_VIRT_RESET_REQ_DEFAULT 0x00000000
34 #define mmSDMA1_VF_ENABLE_DEFAULT 0x00000000
35 #define mmSDMA1_CONTEXT_REG_TYPE0_DEFAULT 0xfffdf79f
[all …]
/openbmc/u-boot/board/freescale/ls2080aqds/
H A DREADME59 0x00_0000_0000 .. 0x00_000F_FFFF Boot Rom
60 0x00_0100_0000 .. 0x00_0FFF_FFFF CCSR
61 0x00_1800_0000 .. 0x00_181F_FFFF OCRAM
62 0x00_3000_0000 .. 0x00_3FFF_FFFF IFC region #1
63 0x00_8000_0000 .. 0x00_FFFF_FFFF DDR region #1
64 0x05_1000_0000 .. 0x05_FFFF_FFFF IFC region #2
65 0x80_8000_0000 .. 0xFF_FFFF_FFFF DDR region #2
73 0x30000000 - 0x37ffffff : 128MB : NOR flash
74 0x38000000 - 0x3BFFFFFF : 64MB : Promjet
75 0x3C000000 - 0x40000000 : 64MB : FPGA etc
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtw89/
H A Drtw8851b_rfk_table.c8 RTW89_DECL_RFK_WM(0xc210, 0x003fc000, 0x80),
9 RTW89_DECL_RFK_WM(0xc224, 0x003fc000, 0x80),
10 RTW89_DECL_RFK_WM(0xc0f8, 0x30000000, 0x3),
11 RTW89_DECL_RFK_WM(0x12b8, BIT(30), 0x1),
12 RTW89_DECL_RFK_WM(0x030c, 0x1f000000, 0x1f),
13 RTW89_DECL_RFK_WM(0x032c, 0xc0000000, 0x0),
14 RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x0),
15 RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x1),
16 RTW89_DECL_RFK_WM(0x032c, BIT(16), 0x0),
17 RTW89_DECL_RFK_WM(0x032c, BIT(20), 0x1),
[all …]
/openbmc/u-boot/include/
H A Dmpc83xx.h23 #define EXC_OFF_SYS_RESET 0x0100
31 #define CONFIG_DEFAULT_IMMR 0xFF400000
34 #define IMMRBAR 0x0000
35 #define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base addr. mask */
42 #define LBLAWBAR0 0x0020
43 #define LBLAWAR0 0x0024
44 #define LBLAWBAR1 0x0028
45 #define LBLAWAR1 0x002C
46 #define LBLAWBAR2 0x0030
47 #define LBLAWAR2 0x0034
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-imx8m/
H A Dddr.h13 #define DDRC_DDR_SS_GPR0 0x3d000000
14 #define DDRC_IPS_BASE_ADDR_0 0x3f400000
15 #define IP2APB_DDRPHY_IPS_BASE_ADDR(X) (0x3c000000 + (X * 0x2000000))
16 #define DDRPHY_MEM(X) (0x3c000000 + (X * 0x2000000) + 0x50000)
342 u32 reg[0xf0000];
354 TRAIN_SUCCESS = 0x7,
355 TRAIN_STREAM_START = 0x8,
356 TRAIN_FAIL = 0xff,
359 #define DDRC_MSTR(X) (DDRC_IPS_BASE_ADDR(X) + 0x00)
360 #define DDRC_STAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x04)
[all …]

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