1812f77b7SFeifei Xu /* 2812f77b7SFeifei Xu * Copyright (C) 2017 Advanced Micro Devices, Inc. 3812f77b7SFeifei Xu * 4812f77b7SFeifei Xu * Permission is hereby granted, free of charge, to any person obtaining a 5812f77b7SFeifei Xu * copy of this software and associated documentation files (the "Software"), 6812f77b7SFeifei Xu * to deal in the Software without restriction, including without limitation 7812f77b7SFeifei Xu * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8812f77b7SFeifei Xu * and/or sell copies of the Software, and to permit persons to whom the 9812f77b7SFeifei Xu * Software is furnished to do so, subject to the following conditions: 10812f77b7SFeifei Xu * 11812f77b7SFeifei Xu * The above copyright notice and this permission notice shall be included 12812f77b7SFeifei Xu * in all copies or substantial portions of the Software. 13812f77b7SFeifei Xu * 14812f77b7SFeifei Xu * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15812f77b7SFeifei Xu * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16812f77b7SFeifei Xu * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17812f77b7SFeifei Xu * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18812f77b7SFeifei Xu * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19812f77b7SFeifei Xu * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20812f77b7SFeifei Xu */ 21812f77b7SFeifei Xu #ifndef _sdma1_4_0_DEFAULT_HEADER 22812f77b7SFeifei Xu #define _sdma1_4_0_DEFAULT_HEADER 23812f77b7SFeifei Xu 24812f77b7SFeifei Xu 25812f77b7SFeifei Xu // addressBlock: sdma1_sdma1dec 26812f77b7SFeifei Xu #define mmSDMA1_UCODE_ADDR_DEFAULT 0x00000000 27812f77b7SFeifei Xu #define mmSDMA1_UCODE_DATA_DEFAULT 0x00000000 28812f77b7SFeifei Xu #define mmSDMA1_VM_CNTL_DEFAULT 0x00000000 29812f77b7SFeifei Xu #define mmSDMA1_VM_CTX_LO_DEFAULT 0x00000000 30812f77b7SFeifei Xu #define mmSDMA1_VM_CTX_HI_DEFAULT 0x00000000 31812f77b7SFeifei Xu #define mmSDMA1_ACTIVE_FCN_ID_DEFAULT 0x00000000 32812f77b7SFeifei Xu #define mmSDMA1_VM_CTX_CNTL_DEFAULT 0x00000000 33812f77b7SFeifei Xu #define mmSDMA1_VIRT_RESET_REQ_DEFAULT 0x00000000 34812f77b7SFeifei Xu #define mmSDMA1_VF_ENABLE_DEFAULT 0x00000000 35812f77b7SFeifei Xu #define mmSDMA1_CONTEXT_REG_TYPE0_DEFAULT 0xfffdf79f 36812f77b7SFeifei Xu #define mmSDMA1_CONTEXT_REG_TYPE1_DEFAULT 0x003fbcff 37812f77b7SFeifei Xu #define mmSDMA1_CONTEXT_REG_TYPE2_DEFAULT 0x000003ff 38812f77b7SFeifei Xu #define mmSDMA1_CONTEXT_REG_TYPE3_DEFAULT 0x00000000 39812f77b7SFeifei Xu #define mmSDMA1_PUB_REG_TYPE0_DEFAULT 0x3c000000 40812f77b7SFeifei Xu #define mmSDMA1_PUB_REG_TYPE1_DEFAULT 0x30003882 41812f77b7SFeifei Xu #define mmSDMA1_PUB_REG_TYPE2_DEFAULT 0x0fc6e880 42812f77b7SFeifei Xu #define mmSDMA1_PUB_REG_TYPE3_DEFAULT 0x00000000 43812f77b7SFeifei Xu #define mmSDMA1_MMHUB_CNTL_DEFAULT 0x00000000 44812f77b7SFeifei Xu #define mmSDMA1_CONTEXT_GROUP_BOUNDARY_DEFAULT 0x00000000 45812f77b7SFeifei Xu #define mmSDMA1_POWER_CNTL_DEFAULT 0x0003c000 46812f77b7SFeifei Xu #define mmSDMA1_CLK_CTRL_DEFAULT 0xff000100 47812f77b7SFeifei Xu #define mmSDMA1_CNTL_DEFAULT 0x00000002 48812f77b7SFeifei Xu #define mmSDMA1_CHICKEN_BITS_DEFAULT 0x00831f07 49812f77b7SFeifei Xu #define mmSDMA1_GB_ADDR_CONFIG_DEFAULT 0x00100012 50812f77b7SFeifei Xu #define mmSDMA1_GB_ADDR_CONFIG_READ_DEFAULT 0x00100012 51812f77b7SFeifei Xu #define mmSDMA1_RB_RPTR_FETCH_HI_DEFAULT 0x00000000 52812f77b7SFeifei Xu #define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_DEFAULT 0x00000000 53812f77b7SFeifei Xu #define mmSDMA1_RB_RPTR_FETCH_DEFAULT 0x00000000 54812f77b7SFeifei Xu #define mmSDMA1_IB_OFFSET_FETCH_DEFAULT 0x00000000 55812f77b7SFeifei Xu #define mmSDMA1_PROGRAM_DEFAULT 0x00000000 56812f77b7SFeifei Xu #define mmSDMA1_STATUS_REG_DEFAULT 0x46dee557 57812f77b7SFeifei Xu #define mmSDMA1_STATUS1_REG_DEFAULT 0x000003ff 58812f77b7SFeifei Xu #define mmSDMA1_RD_BURST_CNTL_DEFAULT 0x00000003 59812f77b7SFeifei Xu #define mmSDMA1_HBM_PAGE_CONFIG_DEFAULT 0x00000000 60812f77b7SFeifei Xu #define mmSDMA1_UCODE_CHECKSUM_DEFAULT 0x00000000 61812f77b7SFeifei Xu #define mmSDMA1_F32_CNTL_DEFAULT 0x00000001 62812f77b7SFeifei Xu #define mmSDMA1_FREEZE_DEFAULT 0x00000000 63812f77b7SFeifei Xu #define mmSDMA1_PHASE0_QUANTUM_DEFAULT 0x00010002 64812f77b7SFeifei Xu #define mmSDMA1_PHASE1_QUANTUM_DEFAULT 0x00010002 65812f77b7SFeifei Xu #define mmSDMA1_EDC_CONFIG_DEFAULT 0x00000002 66812f77b7SFeifei Xu #define mmSDMA1_BA_THRESHOLD_DEFAULT 0x03ff03ff 67812f77b7SFeifei Xu #define mmSDMA1_ID_DEFAULT 0x00000001 68812f77b7SFeifei Xu #define mmSDMA1_VERSION_DEFAULT 0x00000400 69812f77b7SFeifei Xu #define mmSDMA1_EDC_COUNTER_DEFAULT 0x00000000 70812f77b7SFeifei Xu #define mmSDMA1_EDC_COUNTER_CLEAR_DEFAULT 0x00000000 71812f77b7SFeifei Xu #define mmSDMA1_STATUS2_REG_DEFAULT 0x00000001 72812f77b7SFeifei Xu #define mmSDMA1_ATOMIC_CNTL_DEFAULT 0x00000200 73812f77b7SFeifei Xu #define mmSDMA1_ATOMIC_PREOP_LO_DEFAULT 0x00000000 74812f77b7SFeifei Xu #define mmSDMA1_ATOMIC_PREOP_HI_DEFAULT 0x00000000 75812f77b7SFeifei Xu #define mmSDMA1_UTCL1_CNTL_DEFAULT 0xd0003019 76812f77b7SFeifei Xu #define mmSDMA1_UTCL1_WATERMK_DEFAULT 0xfffbe1fe 77812f77b7SFeifei Xu #define mmSDMA1_UTCL1_RD_STATUS_DEFAULT 0x201001ff 78812f77b7SFeifei Xu #define mmSDMA1_UTCL1_WR_STATUS_DEFAULT 0x503001ff 79812f77b7SFeifei Xu #define mmSDMA1_UTCL1_INV0_DEFAULT 0x00000600 80812f77b7SFeifei Xu #define mmSDMA1_UTCL1_INV1_DEFAULT 0x00000000 81812f77b7SFeifei Xu #define mmSDMA1_UTCL1_INV2_DEFAULT 0x00000000 82812f77b7SFeifei Xu #define mmSDMA1_UTCL1_RD_XNACK0_DEFAULT 0x00000000 83812f77b7SFeifei Xu #define mmSDMA1_UTCL1_RD_XNACK1_DEFAULT 0x00000000 84812f77b7SFeifei Xu #define mmSDMA1_UTCL1_WR_XNACK0_DEFAULT 0x00000000 85812f77b7SFeifei Xu #define mmSDMA1_UTCL1_WR_XNACK1_DEFAULT 0x00000000 86812f77b7SFeifei Xu #define mmSDMA1_UTCL1_TIMEOUT_DEFAULT 0x00010001 87812f77b7SFeifei Xu #define mmSDMA1_UTCL1_PAGE_DEFAULT 0x000003e0 88812f77b7SFeifei Xu #define mmSDMA1_POWER_CNTL_IDLE_DEFAULT 0x06060200 89812f77b7SFeifei Xu #define mmSDMA1_RELAX_ORDERING_LUT_DEFAULT 0xc0000006 90812f77b7SFeifei Xu #define mmSDMA1_CHICKEN_BITS_2_DEFAULT 0x00000005 91812f77b7SFeifei Xu #define mmSDMA1_STATUS3_REG_DEFAULT 0x00100000 92812f77b7SFeifei Xu #define mmSDMA1_PHYSICAL_ADDR_LO_DEFAULT 0x00000000 93812f77b7SFeifei Xu #define mmSDMA1_PHYSICAL_ADDR_HI_DEFAULT 0x00000000 94812f77b7SFeifei Xu #define mmSDMA1_PHASE2_QUANTUM_DEFAULT 0x00010002 95812f77b7SFeifei Xu #define mmSDMA1_ERROR_LOG_DEFAULT 0x0000000f 96812f77b7SFeifei Xu #define mmSDMA1_PUB_DUMMY_REG0_DEFAULT 0x00000000 97812f77b7SFeifei Xu #define mmSDMA1_PUB_DUMMY_REG1_DEFAULT 0x00000000 98812f77b7SFeifei Xu #define mmSDMA1_PUB_DUMMY_REG2_DEFAULT 0x00000000 99812f77b7SFeifei Xu #define mmSDMA1_PUB_DUMMY_REG3_DEFAULT 0x00000000 100812f77b7SFeifei Xu #define mmSDMA1_F32_COUNTER_DEFAULT 0x00000000 101812f77b7SFeifei Xu #define mmSDMA1_UNBREAKABLE_DEFAULT 0x00000000 102812f77b7SFeifei Xu #define mmSDMA1_PERFMON_CNTL_DEFAULT 0x000ff7fd 103812f77b7SFeifei Xu #define mmSDMA1_PERFCOUNTER0_RESULT_DEFAULT 0x00000000 104812f77b7SFeifei Xu #define mmSDMA1_PERFCOUNTER1_RESULT_DEFAULT 0x00000000 105812f77b7SFeifei Xu #define mmSDMA1_PERFCOUNTER_TAG_DELAY_RANGE_DEFAULT 0x00640000 106812f77b7SFeifei Xu #define mmSDMA1_CRD_CNTL_DEFAULT 0x000085c0 107812f77b7SFeifei Xu #define mmSDMA1_MMHUB_TRUSTLVL_DEFAULT 0x00000000 108812f77b7SFeifei Xu #define mmSDMA1_GPU_IOV_VIOLATION_LOG_DEFAULT 0x00000000 109812f77b7SFeifei Xu #define mmSDMA1_ULV_CNTL_DEFAULT 0x00000000 110812f77b7SFeifei Xu #define mmSDMA1_EA_DBIT_ADDR_DATA_DEFAULT 0x00000000 111812f77b7SFeifei Xu #define mmSDMA1_EA_DBIT_ADDR_INDEX_DEFAULT 0x00000000 112812f77b7SFeifei Xu #define mmSDMA1_GFX_RB_CNTL_DEFAULT 0x00040000 113812f77b7SFeifei Xu #define mmSDMA1_GFX_RB_BASE_DEFAULT 0x00000000 114812f77b7SFeifei Xu #define mmSDMA1_GFX_RB_BASE_HI_DEFAULT 0x00000000 115812f77b7SFeifei Xu #define mmSDMA1_GFX_RB_RPTR_DEFAULT 0x00000000 116812f77b7SFeifei Xu #define mmSDMA1_GFX_RB_RPTR_HI_DEFAULT 0x00000000 117812f77b7SFeifei Xu #define mmSDMA1_GFX_RB_WPTR_DEFAULT 0x00000000 118812f77b7SFeifei Xu #define mmSDMA1_GFX_RB_WPTR_HI_DEFAULT 0x00000000 119812f77b7SFeifei Xu #define mmSDMA1_GFX_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000 120812f77b7SFeifei Xu #define mmSDMA1_GFX_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 121812f77b7SFeifei Xu #define mmSDMA1_GFX_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 122812f77b7SFeifei Xu #define mmSDMA1_GFX_IB_CNTL_DEFAULT 0x00000100 123812f77b7SFeifei Xu #define mmSDMA1_GFX_IB_RPTR_DEFAULT 0x00000000 124812f77b7SFeifei Xu #define mmSDMA1_GFX_IB_OFFSET_DEFAULT 0x00000000 125812f77b7SFeifei Xu #define mmSDMA1_GFX_IB_BASE_LO_DEFAULT 0x00000000 126812f77b7SFeifei Xu #define mmSDMA1_GFX_IB_BASE_HI_DEFAULT 0x00000000 127812f77b7SFeifei Xu #define mmSDMA1_GFX_IB_SIZE_DEFAULT 0x00000000 128812f77b7SFeifei Xu #define mmSDMA1_GFX_SKIP_CNTL_DEFAULT 0x00000000 129812f77b7SFeifei Xu #define mmSDMA1_GFX_CONTEXT_STATUS_DEFAULT 0x00000005 130812f77b7SFeifei Xu #define mmSDMA1_GFX_DOORBELL_DEFAULT 0x00000000 131812f77b7SFeifei Xu #define mmSDMA1_GFX_CONTEXT_CNTL_DEFAULT 0x00000000 132812f77b7SFeifei Xu #define mmSDMA1_GFX_STATUS_DEFAULT 0x00000000 133812f77b7SFeifei Xu #define mmSDMA1_GFX_DOORBELL_LOG_DEFAULT 0x00000000 134812f77b7SFeifei Xu #define mmSDMA1_GFX_WATERMARK_DEFAULT 0x00000000 135812f77b7SFeifei Xu #define mmSDMA1_GFX_DOORBELL_OFFSET_DEFAULT 0x00000000 136812f77b7SFeifei Xu #define mmSDMA1_GFX_CSA_ADDR_LO_DEFAULT 0x00000000 137812f77b7SFeifei Xu #define mmSDMA1_GFX_CSA_ADDR_HI_DEFAULT 0x00000000 138812f77b7SFeifei Xu #define mmSDMA1_GFX_IB_SUB_REMAIN_DEFAULT 0x00000000 139812f77b7SFeifei Xu #define mmSDMA1_GFX_PREEMPT_DEFAULT 0x00000000 140812f77b7SFeifei Xu #define mmSDMA1_GFX_DUMMY_REG_DEFAULT 0x0000000f 141812f77b7SFeifei Xu #define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 142812f77b7SFeifei Xu #define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 143812f77b7SFeifei Xu #define mmSDMA1_GFX_RB_AQL_CNTL_DEFAULT 0x00004000 144812f77b7SFeifei Xu #define mmSDMA1_GFX_MINOR_PTR_UPDATE_DEFAULT 0x00000000 145812f77b7SFeifei Xu #define mmSDMA1_GFX_MIDCMD_DATA0_DEFAULT 0x00000000 146812f77b7SFeifei Xu #define mmSDMA1_GFX_MIDCMD_DATA1_DEFAULT 0x00000000 147812f77b7SFeifei Xu #define mmSDMA1_GFX_MIDCMD_DATA2_DEFAULT 0x00000000 148812f77b7SFeifei Xu #define mmSDMA1_GFX_MIDCMD_DATA3_DEFAULT 0x00000000 149812f77b7SFeifei Xu #define mmSDMA1_GFX_MIDCMD_DATA4_DEFAULT 0x00000000 150812f77b7SFeifei Xu #define mmSDMA1_GFX_MIDCMD_DATA5_DEFAULT 0x00000000 151812f77b7SFeifei Xu #define mmSDMA1_GFX_MIDCMD_DATA6_DEFAULT 0x00000000 152812f77b7SFeifei Xu #define mmSDMA1_GFX_MIDCMD_DATA7_DEFAULT 0x00000000 153812f77b7SFeifei Xu #define mmSDMA1_GFX_MIDCMD_DATA8_DEFAULT 0x00000000 154812f77b7SFeifei Xu #define mmSDMA1_GFX_MIDCMD_CNTL_DEFAULT 0x00000000 155812f77b7SFeifei Xu #define mmSDMA1_PAGE_RB_CNTL_DEFAULT 0x00040000 156812f77b7SFeifei Xu #define mmSDMA1_PAGE_RB_BASE_DEFAULT 0x00000000 157812f77b7SFeifei Xu #define mmSDMA1_PAGE_RB_BASE_HI_DEFAULT 0x00000000 158812f77b7SFeifei Xu #define mmSDMA1_PAGE_RB_RPTR_DEFAULT 0x00000000 159812f77b7SFeifei Xu #define mmSDMA1_PAGE_RB_RPTR_HI_DEFAULT 0x00000000 160812f77b7SFeifei Xu #define mmSDMA1_PAGE_RB_WPTR_DEFAULT 0x00000000 161812f77b7SFeifei Xu #define mmSDMA1_PAGE_RB_WPTR_HI_DEFAULT 0x00000000 162812f77b7SFeifei Xu #define mmSDMA1_PAGE_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000 163812f77b7SFeifei Xu #define mmSDMA1_PAGE_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 164812f77b7SFeifei Xu #define mmSDMA1_PAGE_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 165812f77b7SFeifei Xu #define mmSDMA1_PAGE_IB_CNTL_DEFAULT 0x00000100 166812f77b7SFeifei Xu #define mmSDMA1_PAGE_IB_RPTR_DEFAULT 0x00000000 167812f77b7SFeifei Xu #define mmSDMA1_PAGE_IB_OFFSET_DEFAULT 0x00000000 168812f77b7SFeifei Xu #define mmSDMA1_PAGE_IB_BASE_LO_DEFAULT 0x00000000 169812f77b7SFeifei Xu #define mmSDMA1_PAGE_IB_BASE_HI_DEFAULT 0x00000000 170812f77b7SFeifei Xu #define mmSDMA1_PAGE_IB_SIZE_DEFAULT 0x00000000 171812f77b7SFeifei Xu #define mmSDMA1_PAGE_SKIP_CNTL_DEFAULT 0x00000000 172812f77b7SFeifei Xu #define mmSDMA1_PAGE_CONTEXT_STATUS_DEFAULT 0x00000004 173812f77b7SFeifei Xu #define mmSDMA1_PAGE_DOORBELL_DEFAULT 0x00000000 174812f77b7SFeifei Xu #define mmSDMA1_PAGE_STATUS_DEFAULT 0x00000000 175812f77b7SFeifei Xu #define mmSDMA1_PAGE_DOORBELL_LOG_DEFAULT 0x00000000 176812f77b7SFeifei Xu #define mmSDMA1_PAGE_WATERMARK_DEFAULT 0x00000000 177812f77b7SFeifei Xu #define mmSDMA1_PAGE_DOORBELL_OFFSET_DEFAULT 0x00000000 178812f77b7SFeifei Xu #define mmSDMA1_PAGE_CSA_ADDR_LO_DEFAULT 0x00000000 179812f77b7SFeifei Xu #define mmSDMA1_PAGE_CSA_ADDR_HI_DEFAULT 0x00000000 180812f77b7SFeifei Xu #define mmSDMA1_PAGE_IB_SUB_REMAIN_DEFAULT 0x00000000 181812f77b7SFeifei Xu #define mmSDMA1_PAGE_PREEMPT_DEFAULT 0x00000000 182812f77b7SFeifei Xu #define mmSDMA1_PAGE_DUMMY_REG_DEFAULT 0x0000000f 183812f77b7SFeifei Xu #define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 184812f77b7SFeifei Xu #define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 185812f77b7SFeifei Xu #define mmSDMA1_PAGE_RB_AQL_CNTL_DEFAULT 0x00004000 186812f77b7SFeifei Xu #define mmSDMA1_PAGE_MINOR_PTR_UPDATE_DEFAULT 0x00000000 187812f77b7SFeifei Xu #define mmSDMA1_PAGE_MIDCMD_DATA0_DEFAULT 0x00000000 188812f77b7SFeifei Xu #define mmSDMA1_PAGE_MIDCMD_DATA1_DEFAULT 0x00000000 189812f77b7SFeifei Xu #define mmSDMA1_PAGE_MIDCMD_DATA2_DEFAULT 0x00000000 190812f77b7SFeifei Xu #define mmSDMA1_PAGE_MIDCMD_DATA3_DEFAULT 0x00000000 191812f77b7SFeifei Xu #define mmSDMA1_PAGE_MIDCMD_DATA4_DEFAULT 0x00000000 192812f77b7SFeifei Xu #define mmSDMA1_PAGE_MIDCMD_DATA5_DEFAULT 0x00000000 193812f77b7SFeifei Xu #define mmSDMA1_PAGE_MIDCMD_DATA6_DEFAULT 0x00000000 194812f77b7SFeifei Xu #define mmSDMA1_PAGE_MIDCMD_DATA7_DEFAULT 0x00000000 195812f77b7SFeifei Xu #define mmSDMA1_PAGE_MIDCMD_DATA8_DEFAULT 0x00000000 196812f77b7SFeifei Xu #define mmSDMA1_PAGE_MIDCMD_CNTL_DEFAULT 0x00000000 197812f77b7SFeifei Xu #define mmSDMA1_RLC0_RB_CNTL_DEFAULT 0x00040000 198812f77b7SFeifei Xu #define mmSDMA1_RLC0_RB_BASE_DEFAULT 0x00000000 199812f77b7SFeifei Xu #define mmSDMA1_RLC0_RB_BASE_HI_DEFAULT 0x00000000 200812f77b7SFeifei Xu #define mmSDMA1_RLC0_RB_RPTR_DEFAULT 0x00000000 201812f77b7SFeifei Xu #define mmSDMA1_RLC0_RB_RPTR_HI_DEFAULT 0x00000000 202812f77b7SFeifei Xu #define mmSDMA1_RLC0_RB_WPTR_DEFAULT 0x00000000 203812f77b7SFeifei Xu #define mmSDMA1_RLC0_RB_WPTR_HI_DEFAULT 0x00000000 204812f77b7SFeifei Xu #define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000 205812f77b7SFeifei Xu #define mmSDMA1_RLC0_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 206812f77b7SFeifei Xu #define mmSDMA1_RLC0_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 207812f77b7SFeifei Xu #define mmSDMA1_RLC0_IB_CNTL_DEFAULT 0x00000100 208812f77b7SFeifei Xu #define mmSDMA1_RLC0_IB_RPTR_DEFAULT 0x00000000 209812f77b7SFeifei Xu #define mmSDMA1_RLC0_IB_OFFSET_DEFAULT 0x00000000 210812f77b7SFeifei Xu #define mmSDMA1_RLC0_IB_BASE_LO_DEFAULT 0x00000000 211812f77b7SFeifei Xu #define mmSDMA1_RLC0_IB_BASE_HI_DEFAULT 0x00000000 212812f77b7SFeifei Xu #define mmSDMA1_RLC0_IB_SIZE_DEFAULT 0x00000000 213812f77b7SFeifei Xu #define mmSDMA1_RLC0_SKIP_CNTL_DEFAULT 0x00000000 214812f77b7SFeifei Xu #define mmSDMA1_RLC0_CONTEXT_STATUS_DEFAULT 0x00000004 215812f77b7SFeifei Xu #define mmSDMA1_RLC0_DOORBELL_DEFAULT 0x00000000 216812f77b7SFeifei Xu #define mmSDMA1_RLC0_STATUS_DEFAULT 0x00000000 217812f77b7SFeifei Xu #define mmSDMA1_RLC0_DOORBELL_LOG_DEFAULT 0x00000000 218812f77b7SFeifei Xu #define mmSDMA1_RLC0_WATERMARK_DEFAULT 0x00000000 219812f77b7SFeifei Xu #define mmSDMA1_RLC0_DOORBELL_OFFSET_DEFAULT 0x00000000 220812f77b7SFeifei Xu #define mmSDMA1_RLC0_CSA_ADDR_LO_DEFAULT 0x00000000 221812f77b7SFeifei Xu #define mmSDMA1_RLC0_CSA_ADDR_HI_DEFAULT 0x00000000 222812f77b7SFeifei Xu #define mmSDMA1_RLC0_IB_SUB_REMAIN_DEFAULT 0x00000000 223812f77b7SFeifei Xu #define mmSDMA1_RLC0_PREEMPT_DEFAULT 0x00000000 224812f77b7SFeifei Xu #define mmSDMA1_RLC0_DUMMY_REG_DEFAULT 0x0000000f 225812f77b7SFeifei Xu #define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 226812f77b7SFeifei Xu #define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 227812f77b7SFeifei Xu #define mmSDMA1_RLC0_RB_AQL_CNTL_DEFAULT 0x00004000 228812f77b7SFeifei Xu #define mmSDMA1_RLC0_MINOR_PTR_UPDATE_DEFAULT 0x00000000 229812f77b7SFeifei Xu #define mmSDMA1_RLC0_MIDCMD_DATA0_DEFAULT 0x00000000 230812f77b7SFeifei Xu #define mmSDMA1_RLC0_MIDCMD_DATA1_DEFAULT 0x00000000 231812f77b7SFeifei Xu #define mmSDMA1_RLC0_MIDCMD_DATA2_DEFAULT 0x00000000 232812f77b7SFeifei Xu #define mmSDMA1_RLC0_MIDCMD_DATA3_DEFAULT 0x00000000 233812f77b7SFeifei Xu #define mmSDMA1_RLC0_MIDCMD_DATA4_DEFAULT 0x00000000 234812f77b7SFeifei Xu #define mmSDMA1_RLC0_MIDCMD_DATA5_DEFAULT 0x00000000 235812f77b7SFeifei Xu #define mmSDMA1_RLC0_MIDCMD_DATA6_DEFAULT 0x00000000 236812f77b7SFeifei Xu #define mmSDMA1_RLC0_MIDCMD_DATA7_DEFAULT 0x00000000 237812f77b7SFeifei Xu #define mmSDMA1_RLC0_MIDCMD_DATA8_DEFAULT 0x00000000 238812f77b7SFeifei Xu #define mmSDMA1_RLC0_MIDCMD_CNTL_DEFAULT 0x00000000 239812f77b7SFeifei Xu #define mmSDMA1_RLC1_RB_CNTL_DEFAULT 0x00040000 240812f77b7SFeifei Xu #define mmSDMA1_RLC1_RB_BASE_DEFAULT 0x00000000 241812f77b7SFeifei Xu #define mmSDMA1_RLC1_RB_BASE_HI_DEFAULT 0x00000000 242812f77b7SFeifei Xu #define mmSDMA1_RLC1_RB_RPTR_DEFAULT 0x00000000 243812f77b7SFeifei Xu #define mmSDMA1_RLC1_RB_RPTR_HI_DEFAULT 0x00000000 244812f77b7SFeifei Xu #define mmSDMA1_RLC1_RB_WPTR_DEFAULT 0x00000000 245812f77b7SFeifei Xu #define mmSDMA1_RLC1_RB_WPTR_HI_DEFAULT 0x00000000 246812f77b7SFeifei Xu #define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000 247812f77b7SFeifei Xu #define mmSDMA1_RLC1_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 248812f77b7SFeifei Xu #define mmSDMA1_RLC1_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 249812f77b7SFeifei Xu #define mmSDMA1_RLC1_IB_CNTL_DEFAULT 0x00000100 250812f77b7SFeifei Xu #define mmSDMA1_RLC1_IB_RPTR_DEFAULT 0x00000000 251812f77b7SFeifei Xu #define mmSDMA1_RLC1_IB_OFFSET_DEFAULT 0x00000000 252812f77b7SFeifei Xu #define mmSDMA1_RLC1_IB_BASE_LO_DEFAULT 0x00000000 253812f77b7SFeifei Xu #define mmSDMA1_RLC1_IB_BASE_HI_DEFAULT 0x00000000 254812f77b7SFeifei Xu #define mmSDMA1_RLC1_IB_SIZE_DEFAULT 0x00000000 255812f77b7SFeifei Xu #define mmSDMA1_RLC1_SKIP_CNTL_DEFAULT 0x00000000 256812f77b7SFeifei Xu #define mmSDMA1_RLC1_CONTEXT_STATUS_DEFAULT 0x00000004 257812f77b7SFeifei Xu #define mmSDMA1_RLC1_DOORBELL_DEFAULT 0x00000000 258812f77b7SFeifei Xu #define mmSDMA1_RLC1_STATUS_DEFAULT 0x00000000 259812f77b7SFeifei Xu #define mmSDMA1_RLC1_DOORBELL_LOG_DEFAULT 0x00000000 260812f77b7SFeifei Xu #define mmSDMA1_RLC1_WATERMARK_DEFAULT 0x00000000 261812f77b7SFeifei Xu #define mmSDMA1_RLC1_DOORBELL_OFFSET_DEFAULT 0x00000000 262812f77b7SFeifei Xu #define mmSDMA1_RLC1_CSA_ADDR_LO_DEFAULT 0x00000000 263812f77b7SFeifei Xu #define mmSDMA1_RLC1_CSA_ADDR_HI_DEFAULT 0x00000000 264812f77b7SFeifei Xu #define mmSDMA1_RLC1_IB_SUB_REMAIN_DEFAULT 0x00000000 265812f77b7SFeifei Xu #define mmSDMA1_RLC1_PREEMPT_DEFAULT 0x00000000 266812f77b7SFeifei Xu #define mmSDMA1_RLC1_DUMMY_REG_DEFAULT 0x0000000f 267812f77b7SFeifei Xu #define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 268812f77b7SFeifei Xu #define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 269812f77b7SFeifei Xu #define mmSDMA1_RLC1_RB_AQL_CNTL_DEFAULT 0x00004000 270812f77b7SFeifei Xu #define mmSDMA1_RLC1_MINOR_PTR_UPDATE_DEFAULT 0x00000000 271812f77b7SFeifei Xu #define mmSDMA1_RLC1_MIDCMD_DATA0_DEFAULT 0x00000000 272812f77b7SFeifei Xu #define mmSDMA1_RLC1_MIDCMD_DATA1_DEFAULT 0x00000000 273812f77b7SFeifei Xu #define mmSDMA1_RLC1_MIDCMD_DATA2_DEFAULT 0x00000000 274812f77b7SFeifei Xu #define mmSDMA1_RLC1_MIDCMD_DATA3_DEFAULT 0x00000000 275812f77b7SFeifei Xu #define mmSDMA1_RLC1_MIDCMD_DATA4_DEFAULT 0x00000000 276812f77b7SFeifei Xu #define mmSDMA1_RLC1_MIDCMD_DATA5_DEFAULT 0x00000000 277812f77b7SFeifei Xu #define mmSDMA1_RLC1_MIDCMD_DATA6_DEFAULT 0x00000000 278812f77b7SFeifei Xu #define mmSDMA1_RLC1_MIDCMD_DATA7_DEFAULT 0x00000000 279812f77b7SFeifei Xu #define mmSDMA1_RLC1_MIDCMD_DATA8_DEFAULT 0x00000000 280812f77b7SFeifei Xu #define mmSDMA1_RLC1_MIDCMD_CNTL_DEFAULT 0x00000000 281812f77b7SFeifei Xu 282812f77b7SFeifei Xu #endif 283