102cf8837SFeifei Xu /* 202cf8837SFeifei Xu * Copyright (C) 2017 Advanced Micro Devices, Inc. 302cf8837SFeifei Xu * 402cf8837SFeifei Xu * Permission is hereby granted, free of charge, to any person obtaining a 502cf8837SFeifei Xu * copy of this software and associated documentation files (the "Software"), 602cf8837SFeifei Xu * to deal in the Software without restriction, including without limitation 702cf8837SFeifei Xu * the rights to use, copy, modify, merge, publish, distribute, sublicense, 802cf8837SFeifei Xu * and/or sell copies of the Software, and to permit persons to whom the 902cf8837SFeifei Xu * Software is furnished to do so, subject to the following conditions: 1002cf8837SFeifei Xu * 1102cf8837SFeifei Xu * The above copyright notice and this permission notice shall be included 1202cf8837SFeifei Xu * in all copies or substantial portions of the Software. 1302cf8837SFeifei Xu * 1402cf8837SFeifei Xu * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 1502cf8837SFeifei Xu * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1602cf8837SFeifei Xu * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1702cf8837SFeifei Xu * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 1802cf8837SFeifei Xu * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 1902cf8837SFeifei Xu * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 2002cf8837SFeifei Xu */ 2102cf8837SFeifei Xu #ifndef _sdma0_4_1_DEFAULT_HEADER 2202cf8837SFeifei Xu #define _sdma0_4_1_DEFAULT_HEADER 2302cf8837SFeifei Xu 2402cf8837SFeifei Xu 2502cf8837SFeifei Xu // addressBlock: sdma0_sdma0dec 2602cf8837SFeifei Xu #define mmSDMA0_UCODE_ADDR_DEFAULT 0x00000000 2702cf8837SFeifei Xu #define mmSDMA0_UCODE_DATA_DEFAULT 0x00000000 2802cf8837SFeifei Xu #define mmSDMA0_VM_CNTL_DEFAULT 0x00000000 2902cf8837SFeifei Xu #define mmSDMA0_VM_CTX_LO_DEFAULT 0x00000000 3002cf8837SFeifei Xu #define mmSDMA0_VM_CTX_HI_DEFAULT 0x00000000 3102cf8837SFeifei Xu #define mmSDMA0_ACTIVE_FCN_ID_DEFAULT 0x00000000 3202cf8837SFeifei Xu #define mmSDMA0_VM_CTX_CNTL_DEFAULT 0x00000000 3302cf8837SFeifei Xu #define mmSDMA0_VIRT_RESET_REQ_DEFAULT 0x00000000 3402cf8837SFeifei Xu #define mmSDMA0_CONTEXT_REG_TYPE0_DEFAULT 0xfffdf79f 3502cf8837SFeifei Xu #define mmSDMA0_CONTEXT_REG_TYPE1_DEFAULT 0x003fbcff 3602cf8837SFeifei Xu #define mmSDMA0_CONTEXT_REG_TYPE2_DEFAULT 0x000003ff 3702cf8837SFeifei Xu #define mmSDMA0_CONTEXT_REG_TYPE3_DEFAULT 0x00000000 3802cf8837SFeifei Xu #define mmSDMA0_PUB_REG_TYPE0_DEFAULT 0x3c000000 3902cf8837SFeifei Xu #define mmSDMA0_PUB_REG_TYPE1_DEFAULT 0x30003882 4002cf8837SFeifei Xu #define mmSDMA0_PUB_REG_TYPE2_DEFAULT 0x0fc66880 4102cf8837SFeifei Xu #define mmSDMA0_PUB_REG_TYPE3_DEFAULT 0x00000000 4202cf8837SFeifei Xu #define mmSDMA0_MMHUB_CNTL_DEFAULT 0x00000000 4302cf8837SFeifei Xu #define mmSDMA0_CONTEXT_GROUP_BOUNDARY_DEFAULT 0x00000000 4402cf8837SFeifei Xu #define mmSDMA0_POWER_CNTL_DEFAULT 0x4003c050 4502cf8837SFeifei Xu #define mmSDMA0_CLK_CTRL_DEFAULT 0xff000100 4602cf8837SFeifei Xu #define mmSDMA0_CNTL_DEFAULT 0x00000002 4702cf8837SFeifei Xu #define mmSDMA0_CHICKEN_BITS_DEFAULT 0x00831f07 4802cf8837SFeifei Xu #define mmSDMA0_GB_ADDR_CONFIG_DEFAULT 0x00100012 4902cf8837SFeifei Xu #define mmSDMA0_GB_ADDR_CONFIG_READ_DEFAULT 0x00100012 5002cf8837SFeifei Xu #define mmSDMA0_RB_RPTR_FETCH_HI_DEFAULT 0x00000000 5102cf8837SFeifei Xu #define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_DEFAULT 0x00000000 5202cf8837SFeifei Xu #define mmSDMA0_RB_RPTR_FETCH_DEFAULT 0x00000000 5302cf8837SFeifei Xu #define mmSDMA0_IB_OFFSET_FETCH_DEFAULT 0x00000000 5402cf8837SFeifei Xu #define mmSDMA0_PROGRAM_DEFAULT 0x00000000 5502cf8837SFeifei Xu #define mmSDMA0_STATUS_REG_DEFAULT 0x46dee557 5602cf8837SFeifei Xu #define mmSDMA0_STATUS1_REG_DEFAULT 0x000003ff 5702cf8837SFeifei Xu #define mmSDMA0_RD_BURST_CNTL_DEFAULT 0x00000003 5802cf8837SFeifei Xu #define mmSDMA0_HBM_PAGE_CONFIG_DEFAULT 0x00000000 5902cf8837SFeifei Xu #define mmSDMA0_UCODE_CHECKSUM_DEFAULT 0x00000000 6002cf8837SFeifei Xu #define mmSDMA0_F32_CNTL_DEFAULT 0x00000001 6102cf8837SFeifei Xu #define mmSDMA0_FREEZE_DEFAULT 0x00000000 6202cf8837SFeifei Xu #define mmSDMA0_PHASE0_QUANTUM_DEFAULT 0x00010002 6302cf8837SFeifei Xu #define mmSDMA0_PHASE1_QUANTUM_DEFAULT 0x00010002 6402cf8837SFeifei Xu #define mmSDMA_POWER_GATING_DEFAULT 0x00000000 6502cf8837SFeifei Xu #define mmSDMA_PGFSM_CONFIG_DEFAULT 0x00000000 6602cf8837SFeifei Xu #define mmSDMA_PGFSM_WRITE_DEFAULT 0x00000000 6702cf8837SFeifei Xu #define mmSDMA_PGFSM_READ_DEFAULT 0x00000000 6802cf8837SFeifei Xu #define mmSDMA0_EDC_CONFIG_DEFAULT 0x00000002 6902cf8837SFeifei Xu #define mmSDMA0_BA_THRESHOLD_DEFAULT 0x03ff03ff 7002cf8837SFeifei Xu #define mmSDMA0_ID_DEFAULT 0x00000001 7102cf8837SFeifei Xu #define mmSDMA0_VERSION_DEFAULT 0x00000401 7202cf8837SFeifei Xu #define mmSDMA0_EDC_COUNTER_DEFAULT 0x00000000 7302cf8837SFeifei Xu #define mmSDMA0_EDC_COUNTER_CLEAR_DEFAULT 0x00000000 7402cf8837SFeifei Xu #define mmSDMA0_STATUS2_REG_DEFAULT 0x00000000 7502cf8837SFeifei Xu #define mmSDMA0_ATOMIC_CNTL_DEFAULT 0x00000200 7602cf8837SFeifei Xu #define mmSDMA0_ATOMIC_PREOP_LO_DEFAULT 0x00000000 7702cf8837SFeifei Xu #define mmSDMA0_ATOMIC_PREOP_HI_DEFAULT 0x00000000 7802cf8837SFeifei Xu #define mmSDMA0_UTCL1_CNTL_DEFAULT 0xd0003019 7902cf8837SFeifei Xu #define mmSDMA0_UTCL1_WATERMK_DEFAULT 0xfffbe1fe 8002cf8837SFeifei Xu #define mmSDMA0_UTCL1_RD_STATUS_DEFAULT 0x201001ff 8102cf8837SFeifei Xu #define mmSDMA0_UTCL1_WR_STATUS_DEFAULT 0x503001ff 8202cf8837SFeifei Xu #define mmSDMA0_UTCL1_INV0_DEFAULT 0x00000600 8302cf8837SFeifei Xu #define mmSDMA0_UTCL1_INV1_DEFAULT 0x00000000 8402cf8837SFeifei Xu #define mmSDMA0_UTCL1_INV2_DEFAULT 0x00000000 8502cf8837SFeifei Xu #define mmSDMA0_UTCL1_RD_XNACK0_DEFAULT 0x00000000 8602cf8837SFeifei Xu #define mmSDMA0_UTCL1_RD_XNACK1_DEFAULT 0x00000000 8702cf8837SFeifei Xu #define mmSDMA0_UTCL1_WR_XNACK0_DEFAULT 0x00000000 8802cf8837SFeifei Xu #define mmSDMA0_UTCL1_WR_XNACK1_DEFAULT 0x00000000 8902cf8837SFeifei Xu #define mmSDMA0_UTCL1_TIMEOUT_DEFAULT 0x00010001 9002cf8837SFeifei Xu #define mmSDMA0_UTCL1_PAGE_DEFAULT 0x000003e0 9102cf8837SFeifei Xu #define mmSDMA0_POWER_CNTL_IDLE_DEFAULT 0x06060200 9202cf8837SFeifei Xu #define mmSDMA0_RELAX_ORDERING_LUT_DEFAULT 0xc0000006 9302cf8837SFeifei Xu #define mmSDMA0_CHICKEN_BITS_2_DEFAULT 0x00000005 9402cf8837SFeifei Xu #define mmSDMA0_STATUS3_REG_DEFAULT 0x00100000 9502cf8837SFeifei Xu #define mmSDMA0_PHYSICAL_ADDR_LO_DEFAULT 0x00000000 9602cf8837SFeifei Xu #define mmSDMA0_PHYSICAL_ADDR_HI_DEFAULT 0x00000000 9702cf8837SFeifei Xu #define mmSDMA0_ERROR_LOG_DEFAULT 0x0000000f 9802cf8837SFeifei Xu #define mmSDMA0_PUB_DUMMY_REG0_DEFAULT 0x00000000 9902cf8837SFeifei Xu #define mmSDMA0_PUB_DUMMY_REG1_DEFAULT 0x00000000 10002cf8837SFeifei Xu #define mmSDMA0_PUB_DUMMY_REG2_DEFAULT 0x00000000 10102cf8837SFeifei Xu #define mmSDMA0_PUB_DUMMY_REG3_DEFAULT 0x00000000 10202cf8837SFeifei Xu #define mmSDMA0_F32_COUNTER_DEFAULT 0x00000000 10302cf8837SFeifei Xu #define mmSDMA0_UNBREAKABLE_DEFAULT 0x00000000 10402cf8837SFeifei Xu #define mmSDMA0_PERFMON_CNTL_DEFAULT 0x000ff7fd 10502cf8837SFeifei Xu #define mmSDMA0_PERFCOUNTER0_RESULT_DEFAULT 0x00000000 10602cf8837SFeifei Xu #define mmSDMA0_PERFCOUNTER1_RESULT_DEFAULT 0x00000000 10702cf8837SFeifei Xu #define mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE_DEFAULT 0x00640000 10802cf8837SFeifei Xu #define mmSDMA0_CRD_CNTL_DEFAULT 0x000085c0 10902cf8837SFeifei Xu #define mmSDMA0_MMHUB_TRUSTLVL_DEFAULT 0x00000000 11002cf8837SFeifei Xu #define mmSDMA0_GPU_IOV_VIOLATION_LOG_DEFAULT 0x00000000 11102cf8837SFeifei Xu #define mmSDMA0_ULV_CNTL_DEFAULT 0x00000000 11202cf8837SFeifei Xu #define mmSDMA0_EA_DBIT_ADDR_DATA_DEFAULT 0x00000000 11302cf8837SFeifei Xu #define mmSDMA0_EA_DBIT_ADDR_INDEX_DEFAULT 0x00000000 11402cf8837SFeifei Xu #define mmSDMA0_GFX_RB_CNTL_DEFAULT 0x00040000 11502cf8837SFeifei Xu #define mmSDMA0_GFX_RB_BASE_DEFAULT 0x00000000 11602cf8837SFeifei Xu #define mmSDMA0_GFX_RB_BASE_HI_DEFAULT 0x00000000 11702cf8837SFeifei Xu #define mmSDMA0_GFX_RB_RPTR_DEFAULT 0x00000000 11802cf8837SFeifei Xu #define mmSDMA0_GFX_RB_RPTR_HI_DEFAULT 0x00000000 11902cf8837SFeifei Xu #define mmSDMA0_GFX_RB_WPTR_DEFAULT 0x00000000 12002cf8837SFeifei Xu #define mmSDMA0_GFX_RB_WPTR_HI_DEFAULT 0x00000000 12102cf8837SFeifei Xu #define mmSDMA0_GFX_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000 12202cf8837SFeifei Xu #define mmSDMA0_GFX_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 12302cf8837SFeifei Xu #define mmSDMA0_GFX_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 12402cf8837SFeifei Xu #define mmSDMA0_GFX_IB_CNTL_DEFAULT 0x00000100 12502cf8837SFeifei Xu #define mmSDMA0_GFX_IB_RPTR_DEFAULT 0x00000000 12602cf8837SFeifei Xu #define mmSDMA0_GFX_IB_OFFSET_DEFAULT 0x00000000 12702cf8837SFeifei Xu #define mmSDMA0_GFX_IB_BASE_LO_DEFAULT 0x00000000 12802cf8837SFeifei Xu #define mmSDMA0_GFX_IB_BASE_HI_DEFAULT 0x00000000 12902cf8837SFeifei Xu #define mmSDMA0_GFX_IB_SIZE_DEFAULT 0x00000000 13002cf8837SFeifei Xu #define mmSDMA0_GFX_SKIP_CNTL_DEFAULT 0x00000000 13102cf8837SFeifei Xu #define mmSDMA0_GFX_CONTEXT_STATUS_DEFAULT 0x00000005 13202cf8837SFeifei Xu #define mmSDMA0_GFX_DOORBELL_DEFAULT 0x00000000 13302cf8837SFeifei Xu #define mmSDMA0_GFX_CONTEXT_CNTL_DEFAULT 0x00000000 13402cf8837SFeifei Xu #define mmSDMA0_GFX_STATUS_DEFAULT 0x00000000 13502cf8837SFeifei Xu #define mmSDMA0_GFX_DOORBELL_LOG_DEFAULT 0x00000000 13602cf8837SFeifei Xu #define mmSDMA0_GFX_WATERMARK_DEFAULT 0x00000000 13702cf8837SFeifei Xu #define mmSDMA0_GFX_DOORBELL_OFFSET_DEFAULT 0x00000000 13802cf8837SFeifei Xu #define mmSDMA0_GFX_CSA_ADDR_LO_DEFAULT 0x00000000 13902cf8837SFeifei Xu #define mmSDMA0_GFX_CSA_ADDR_HI_DEFAULT 0x00000000 14002cf8837SFeifei Xu #define mmSDMA0_GFX_IB_SUB_REMAIN_DEFAULT 0x00000000 14102cf8837SFeifei Xu #define mmSDMA0_GFX_PREEMPT_DEFAULT 0x00000000 14202cf8837SFeifei Xu #define mmSDMA0_GFX_DUMMY_REG_DEFAULT 0x0000000f 14302cf8837SFeifei Xu #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 14402cf8837SFeifei Xu #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 14502cf8837SFeifei Xu #define mmSDMA0_GFX_RB_AQL_CNTL_DEFAULT 0x00004000 14602cf8837SFeifei Xu #define mmSDMA0_GFX_MINOR_PTR_UPDATE_DEFAULT 0x00000000 14702cf8837SFeifei Xu #define mmSDMA0_GFX_MIDCMD_DATA0_DEFAULT 0x00000000 14802cf8837SFeifei Xu #define mmSDMA0_GFX_MIDCMD_DATA1_DEFAULT 0x00000000 14902cf8837SFeifei Xu #define mmSDMA0_GFX_MIDCMD_DATA2_DEFAULT 0x00000000 15002cf8837SFeifei Xu #define mmSDMA0_GFX_MIDCMD_DATA3_DEFAULT 0x00000000 15102cf8837SFeifei Xu #define mmSDMA0_GFX_MIDCMD_DATA4_DEFAULT 0x00000000 15202cf8837SFeifei Xu #define mmSDMA0_GFX_MIDCMD_DATA5_DEFAULT 0x00000000 15302cf8837SFeifei Xu #define mmSDMA0_GFX_MIDCMD_DATA6_DEFAULT 0x00000000 15402cf8837SFeifei Xu #define mmSDMA0_GFX_MIDCMD_DATA7_DEFAULT 0x00000000 15502cf8837SFeifei Xu #define mmSDMA0_GFX_MIDCMD_DATA8_DEFAULT 0x00000000 15602cf8837SFeifei Xu #define mmSDMA0_GFX_MIDCMD_CNTL_DEFAULT 0x00000000 15702cf8837SFeifei Xu #define mmSDMA0_RLC0_RB_CNTL_DEFAULT 0x00040000 15802cf8837SFeifei Xu #define mmSDMA0_RLC0_RB_BASE_DEFAULT 0x00000000 15902cf8837SFeifei Xu #define mmSDMA0_RLC0_RB_BASE_HI_DEFAULT 0x00000000 16002cf8837SFeifei Xu #define mmSDMA0_RLC0_RB_RPTR_DEFAULT 0x00000000 16102cf8837SFeifei Xu #define mmSDMA0_RLC0_RB_RPTR_HI_DEFAULT 0x00000000 16202cf8837SFeifei Xu #define mmSDMA0_RLC0_RB_WPTR_DEFAULT 0x00000000 16302cf8837SFeifei Xu #define mmSDMA0_RLC0_RB_WPTR_HI_DEFAULT 0x00000000 16402cf8837SFeifei Xu #define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000 16502cf8837SFeifei Xu #define mmSDMA0_RLC0_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 16602cf8837SFeifei Xu #define mmSDMA0_RLC0_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 16702cf8837SFeifei Xu #define mmSDMA0_RLC0_IB_CNTL_DEFAULT 0x00000100 16802cf8837SFeifei Xu #define mmSDMA0_RLC0_IB_RPTR_DEFAULT 0x00000000 16902cf8837SFeifei Xu #define mmSDMA0_RLC0_IB_OFFSET_DEFAULT 0x00000000 17002cf8837SFeifei Xu #define mmSDMA0_RLC0_IB_BASE_LO_DEFAULT 0x00000000 17102cf8837SFeifei Xu #define mmSDMA0_RLC0_IB_BASE_HI_DEFAULT 0x00000000 17202cf8837SFeifei Xu #define mmSDMA0_RLC0_IB_SIZE_DEFAULT 0x00000000 17302cf8837SFeifei Xu #define mmSDMA0_RLC0_SKIP_CNTL_DEFAULT 0x00000000 17402cf8837SFeifei Xu #define mmSDMA0_RLC0_CONTEXT_STATUS_DEFAULT 0x00000004 17502cf8837SFeifei Xu #define mmSDMA0_RLC0_DOORBELL_DEFAULT 0x00000000 17602cf8837SFeifei Xu #define mmSDMA0_RLC0_STATUS_DEFAULT 0x00000000 17702cf8837SFeifei Xu #define mmSDMA0_RLC0_DOORBELL_LOG_DEFAULT 0x00000000 17802cf8837SFeifei Xu #define mmSDMA0_RLC0_WATERMARK_DEFAULT 0x00000000 17902cf8837SFeifei Xu #define mmSDMA0_RLC0_DOORBELL_OFFSET_DEFAULT 0x00000000 18002cf8837SFeifei Xu #define mmSDMA0_RLC0_CSA_ADDR_LO_DEFAULT 0x00000000 18102cf8837SFeifei Xu #define mmSDMA0_RLC0_CSA_ADDR_HI_DEFAULT 0x00000000 18202cf8837SFeifei Xu #define mmSDMA0_RLC0_IB_SUB_REMAIN_DEFAULT 0x00000000 18302cf8837SFeifei Xu #define mmSDMA0_RLC0_PREEMPT_DEFAULT 0x00000000 18402cf8837SFeifei Xu #define mmSDMA0_RLC0_DUMMY_REG_DEFAULT 0x0000000f 18502cf8837SFeifei Xu #define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 18602cf8837SFeifei Xu #define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 18702cf8837SFeifei Xu #define mmSDMA0_RLC0_RB_AQL_CNTL_DEFAULT 0x00004000 18802cf8837SFeifei Xu #define mmSDMA0_RLC0_MINOR_PTR_UPDATE_DEFAULT 0x00000000 18902cf8837SFeifei Xu #define mmSDMA0_RLC0_MIDCMD_DATA0_DEFAULT 0x00000000 19002cf8837SFeifei Xu #define mmSDMA0_RLC0_MIDCMD_DATA1_DEFAULT 0x00000000 19102cf8837SFeifei Xu #define mmSDMA0_RLC0_MIDCMD_DATA2_DEFAULT 0x00000000 19202cf8837SFeifei Xu #define mmSDMA0_RLC0_MIDCMD_DATA3_DEFAULT 0x00000000 19302cf8837SFeifei Xu #define mmSDMA0_RLC0_MIDCMD_DATA4_DEFAULT 0x00000000 19402cf8837SFeifei Xu #define mmSDMA0_RLC0_MIDCMD_DATA5_DEFAULT 0x00000000 19502cf8837SFeifei Xu #define mmSDMA0_RLC0_MIDCMD_DATA6_DEFAULT 0x00000000 19602cf8837SFeifei Xu #define mmSDMA0_RLC0_MIDCMD_DATA7_DEFAULT 0x00000000 19702cf8837SFeifei Xu #define mmSDMA0_RLC0_MIDCMD_DATA8_DEFAULT 0x00000000 19802cf8837SFeifei Xu #define mmSDMA0_RLC0_MIDCMD_CNTL_DEFAULT 0x00000000 19902cf8837SFeifei Xu #define mmSDMA0_RLC1_RB_CNTL_DEFAULT 0x00040000 20002cf8837SFeifei Xu #define mmSDMA0_RLC1_RB_BASE_DEFAULT 0x00000000 20102cf8837SFeifei Xu #define mmSDMA0_RLC1_RB_BASE_HI_DEFAULT 0x00000000 20202cf8837SFeifei Xu #define mmSDMA0_RLC1_RB_RPTR_DEFAULT 0x00000000 20302cf8837SFeifei Xu #define mmSDMA0_RLC1_RB_RPTR_HI_DEFAULT 0x00000000 20402cf8837SFeifei Xu #define mmSDMA0_RLC1_RB_WPTR_DEFAULT 0x00000000 20502cf8837SFeifei Xu #define mmSDMA0_RLC1_RB_WPTR_HI_DEFAULT 0x00000000 20602cf8837SFeifei Xu #define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000 20702cf8837SFeifei Xu #define mmSDMA0_RLC1_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 20802cf8837SFeifei Xu #define mmSDMA0_RLC1_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 20902cf8837SFeifei Xu #define mmSDMA0_RLC1_IB_CNTL_DEFAULT 0x00000100 21002cf8837SFeifei Xu #define mmSDMA0_RLC1_IB_RPTR_DEFAULT 0x00000000 21102cf8837SFeifei Xu #define mmSDMA0_RLC1_IB_OFFSET_DEFAULT 0x00000000 21202cf8837SFeifei Xu #define mmSDMA0_RLC1_IB_BASE_LO_DEFAULT 0x00000000 21302cf8837SFeifei Xu #define mmSDMA0_RLC1_IB_BASE_HI_DEFAULT 0x00000000 21402cf8837SFeifei Xu #define mmSDMA0_RLC1_IB_SIZE_DEFAULT 0x00000000 21502cf8837SFeifei Xu #define mmSDMA0_RLC1_SKIP_CNTL_DEFAULT 0x00000000 21602cf8837SFeifei Xu #define mmSDMA0_RLC1_CONTEXT_STATUS_DEFAULT 0x00000004 21702cf8837SFeifei Xu #define mmSDMA0_RLC1_DOORBELL_DEFAULT 0x00000000 21802cf8837SFeifei Xu #define mmSDMA0_RLC1_STATUS_DEFAULT 0x00000000 21902cf8837SFeifei Xu #define mmSDMA0_RLC1_DOORBELL_LOG_DEFAULT 0x00000000 22002cf8837SFeifei Xu #define mmSDMA0_RLC1_WATERMARK_DEFAULT 0x00000000 22102cf8837SFeifei Xu #define mmSDMA0_RLC1_DOORBELL_OFFSET_DEFAULT 0x00000000 22202cf8837SFeifei Xu #define mmSDMA0_RLC1_CSA_ADDR_LO_DEFAULT 0x00000000 22302cf8837SFeifei Xu #define mmSDMA0_RLC1_CSA_ADDR_HI_DEFAULT 0x00000000 22402cf8837SFeifei Xu #define mmSDMA0_RLC1_IB_SUB_REMAIN_DEFAULT 0x00000000 22502cf8837SFeifei Xu #define mmSDMA0_RLC1_PREEMPT_DEFAULT 0x00000000 22602cf8837SFeifei Xu #define mmSDMA0_RLC1_DUMMY_REG_DEFAULT 0x0000000f 22702cf8837SFeifei Xu #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 22802cf8837SFeifei Xu #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 22902cf8837SFeifei Xu #define mmSDMA0_RLC1_RB_AQL_CNTL_DEFAULT 0x00004000 23002cf8837SFeifei Xu #define mmSDMA0_RLC1_MINOR_PTR_UPDATE_DEFAULT 0x00000000 23102cf8837SFeifei Xu #define mmSDMA0_RLC1_MIDCMD_DATA0_DEFAULT 0x00000000 23202cf8837SFeifei Xu #define mmSDMA0_RLC1_MIDCMD_DATA1_DEFAULT 0x00000000 23302cf8837SFeifei Xu #define mmSDMA0_RLC1_MIDCMD_DATA2_DEFAULT 0x00000000 23402cf8837SFeifei Xu #define mmSDMA0_RLC1_MIDCMD_DATA3_DEFAULT 0x00000000 23502cf8837SFeifei Xu #define mmSDMA0_RLC1_MIDCMD_DATA4_DEFAULT 0x00000000 23602cf8837SFeifei Xu #define mmSDMA0_RLC1_MIDCMD_DATA5_DEFAULT 0x00000000 23702cf8837SFeifei Xu #define mmSDMA0_RLC1_MIDCMD_DATA6_DEFAULT 0x00000000 23802cf8837SFeifei Xu #define mmSDMA0_RLC1_MIDCMD_DATA7_DEFAULT 0x00000000 23902cf8837SFeifei Xu #define mmSDMA0_RLC1_MIDCMD_DATA8_DEFAULT 0x00000000 24002cf8837SFeifei Xu #define mmSDMA0_RLC1_MIDCMD_CNTL_DEFAULT 0x00000000 24102cf8837SFeifei Xu 24202cf8837SFeifei Xu #endif 243