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/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/bar/
H A Dg84.c34 nvkm_wr32(device, 0x070000, 0x00000001); in g84_bar_flush()
36 if (!(nvkm_rd32(device, 0x070000) & 0x00000002)) in g84_bar_flush()
62 return nv50_bar_new_(&g84_bar_func, device, type, inst, 0x200, pbar); in g84_bar_new()
/openbmc/linux/Documentation/devicetree/bindings/serio/
H A Darm,pl050.yaml61 reg = <0x070000 0x1000>;
/openbmc/u-boot/drivers/spi/
H A Dich.h24 uint32_t bfpr; /* 0x00 */
29 uint32_t fdata[16]; /* 0x10 */
30 uint32_t frap; /* 0x50 */
33 uint32_t pr[5]; /* 0x74 */
35 uint8_t ssfs; /* 0x90 */
37 uint16_t preop; /* 0x94 */
39 uint8_t opmenu[8]; /* 0x98 */
42 uint32_t fdoc; /* 0xb0 */
45 uint32_t afc; /* 0xc0 */
49 uint32_t fpb; /* 0xd0 */
[all …]
/openbmc/u-boot/drivers/phy/marvell/
H A Dcomphy_a3700.h19 #define POLL_32B_REG 0
24 #define COMPHY_SEL_ADDR MVEBU_REG(0x0183FC)
26 #define COMPHY_PHY_CFG1_ADDR(lane) MVEBU_REG(0x018300 + (1 - lane) * 0x28)
35 #define rf_gen_rx_select (0x0F << rf_gen_rx_sel_shift)
37 #define rf_gen_tx_select (0x0F << rf_gen_tx_sel_shift)
40 #define COMPHY_PHY_STAT1_ADDR(lane) MVEBU_REG(0x018318 + (1 - lane) * 0x28)
41 #define rb_rx_init_done BIT(0)
48 #define PCIE_BASE MVEBU_REG(0x070000)
49 #define PCIETOP_BASE MVEBU_REG(0x080000)
50 #define PCIE_RAMBASE MVEBU_REG(0x08C000)
[all …]
/openbmc/u-boot/arch/mips/dts/
H A Dmscc,luton.dtsi15 #size-cells = <0>;
17 cpu@0 {
20 reg = <0>;
30 #clock-cells = <0>;
35 #clock-cells = <0>;
43 ranges = <0 0x60000000 0x10200000>;
46 pinctrl-0 = <&uart_pins>;
50 reg = <0x10100000 0x20>;
60 reg = <0x70068 0x68>;
63 gpio-ranges = <&gpio 0 0 32>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/arm/
H A Drtsm_ve-motherboard.dtsi13 #clock-cells = <0>;
20 #clock-cells = <0>;
27 #clock-cells = <0>;
49 #clock-cells = <0>;
55 arm,vexpress-sysreg,func = <5 0>;
60 arm,vexpress-sysreg,func = <7 0>;
65 arm,vexpress-sysreg,func = <8 0>;
70 arm,vexpress-sysreg,func = <9 0>;
75 arm,vexpress-sysreg,func = <11 0>;
83 ranges = <0 0x8000000 0 0x8000000 0x18000000>;
[all …]
H A Djuno-motherboard.dtsi13 #clock-cells = <0>;
20 #clock-cells = <0>;
27 #clock-cells = <0>;
34 #clock-cells = <0>;
55 gpios = <&iofpga_gpio0 0 0x4>;
62 gpios = <&iofpga_gpio0 1 0x4>;
69 gpios = <&iofpga_gpio0 2 0x4>;
76 gpios = <&iofpga_gpio0 3 0x4>;
83 gpios = <&iofpga_gpio0 4 0x4>;
90 gpios = <&iofpga_gpio0 5 0x4>;
[all …]
/openbmc/linux/sound/pci/mixart/
H A Dmixart_core.h15 MSG_CONNECTOR_GET_AUDIO_INFO = 0x050008,
16 MSG_CONNECTOR_GET_OUT_AUDIO_LEVEL = 0x050009,
17 MSG_CONNECTOR_SET_OUT_AUDIO_LEVEL = 0x05000A,
19 MSG_CONSOLE_MANAGER = 0x070000,
20 MSG_CONSOLE_GET_CLOCK_UID = 0x070003,
22 MSG_PHYSICALIO_SET_LEVEL = 0x0F0008,
24 MSG_STREAM_ADD_INPUT_GROUP = 0x130000,
25 MSG_STREAM_ADD_OUTPUT_GROUP = 0x130001,
26 MSG_STREAM_DELETE_GROUP = 0x130004,
27 MSG_STREAM_START_STREAM_GRP_PACKET = 0x130006,
[all …]
/openbmc/linux/include/linux/
H A Dsm501-regs.h11 #define SM501_SYS_CONFIG (0x000000)
14 #define SM501_SYSTEM_CONTROL (0x000000)
16 #define SM501_SYSCTRL_PANEL_TRISTATE (1<<0)
21 #define SM501_SYSCTRL_PCI_SLAVE_BURST_1 (0<<4)
35 #define SM501_MISC_CONTROL (0x000004)
37 #define SM501_MISC_BUS_SH (0x0)
38 #define SM501_MISC_BUS_PCI (0x1)
39 #define SM501_MISC_BUS_XSCALE (0x2)
40 #define SM501_MISC_BUS_NEC (0x6)
41 #define SM501_MISC_BUS_MASK (0x7)
[all …]
/openbmc/linux/drivers/scsi/pm8001/
H A Dpm8001_hwi.h48 #define OPC_INB_ECHO 1 /* 0x000 */
49 #define OPC_INB_PHYSTART 4 /* 0x004 */
50 #define OPC_INB_PHYSTOP 5 /* 0x005 */
51 #define OPC_INB_SSPINIIOSTART 6 /* 0x006 */
52 #define OPC_INB_SSPINITMSTART 7 /* 0x007 */
53 #define OPC_INB_SSPINIEXTIOSTART 8 /* 0x008 */
54 #define OPC_INB_DEV_HANDLE_ACCEPT 9 /* 0x009 */
55 #define OPC_INB_SSPTGTIOSTART 10 /* 0x00A */
56 #define OPC_INB_SSPTGTRSPSTART 11 /* 0x00B */
57 #define OPC_INB_SSPINIEDCIOSTART 12 /* 0x00C */
[all …]
H A Dpm80xx_hwi.h48 #define OPC_INB_ECHO 1 /* 0x000 */
49 #define OPC_INB_PHYSTART 4 /* 0x004 */
50 #define OPC_INB_PHYSTOP 5 /* 0x005 */
51 #define OPC_INB_SSPINIIOSTART 6 /* 0x006 */
52 #define OPC_INB_SSPINITMSTART 7 /* 0x007 */
53 /* 0x8 RESV IN SPCv */
54 #define OPC_INB_RSVD 8 /* 0x008 */
55 #define OPC_INB_DEV_HANDLE_ACCEPT 9 /* 0x009 */
56 #define OPC_INB_SSPTGTIOSTART 10 /* 0x00A */
57 #define OPC_INB_SSPTGTRSPSTART 11 /* 0x00B */
[all …]
/openbmc/u-boot/include/
H A Dvsc9953.h15 #define VSC9953_OFFSET (CONFIG_SYS_CCSRBAR_DEFAULT + 0x800000)
17 #define VSC9953_SYS_OFFSET 0x010000
18 #define VSC9953_REW_OFFSET 0x030000
19 #define VSC9953_DEV_GMII_OFFSET 0x100000
20 #define VSC9953_QSYS_OFFSET 0x200000
21 #define VSC9953_ANA_OFFSET 0x280000
22 #define VSC9953_DEVCPU_GCB 0x070000
23 #define VSC9953_ES0 0x040000
24 #define VSC9953_IS1 0x050000
25 #define VSC9953_IS2 0x060000
[all …]
/openbmc/linux/arch/arm/boot/dts/arm/
H A Dvexpress-v2m-rs1.dtsi23 v2m_fixed_3v3: fixed-regulator-0 {
33 #clock-cells = <0>;
40 #clock-cells = <0>;
47 #clock-cells = <0>;
57 gpios = <&v2m_led_gpios 0 0>;
63 gpios = <&v2m_led_gpios 1 0>;
69 gpios = <&v2m_led_gpios 2 0>;
75 gpios = <&v2m_led_gpios 3 0>;
81 gpios = <&v2m_led_gpios 4 0>;
87 gpios = <&v2m_led_gpios 5 0>;
[all …]
/openbmc/linux/arch/mips/include/asm/
H A Dcpu.h16 register 15, select 0) is defined in this (backwards compatible) way:
24 that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
28 #define PRID_OPT_MASK 0xff000000
34 #define PRID_COMP_MASK 0xff0000
36 #define PRID_COMP_LEGACY 0x000000
37 #define PRID_COMP_MIPS 0x010000
38 #define PRID_COMP_BROADCOM 0x020000
39 #define PRID_COMP_ALCHEMY 0x030000
40 #define PRID_COMP_SIBYTE 0x040000
41 #define PRID_COMP_SANDCRAFT 0x050000
[all …]
/openbmc/linux/drivers/clk/imx/
H A Dclk-imx8-acm.c130 … IMX_ADMA_ACM_AUD_CLK0_SEL, imx8qm_aud_clk_sels, ARRAY_SIZE(imx8qm_aud_clk_sels), 0x000000, 0, 5 },
131 … IMX_ADMA_ACM_AUD_CLK1_SEL, imx8qm_aud_clk_sels, ARRAY_SIZE(imx8qm_aud_clk_sels), 0x010000, 0, 5 },
132 …MX_ADMA_ACM_MCLKOUT0_SEL, imx8qm_mclk_out_sels, ARRAY_SIZE(imx8qm_mclk_out_sels), 0x020000, 0, 3 },
133 …MX_ADMA_ACM_MCLKOUT1_SEL, imx8qm_mclk_out_sels, ARRAY_SIZE(imx8qm_mclk_out_sels), 0x030000, 0, 3 },
134 …SRC0_MUX_CLK_SEL, imx8qm_asrc_mux_clk_sels, ARRAY_SIZE(imx8qm_asrc_mux_clk_sels), 0x040000, 0, 2 },
135 …el", IMX_ADMA_ACM_ESAI0_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x060000, 0, 2 },
136 …el", IMX_ADMA_ACM_ESAI1_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x070000, 0, 2 },
137 …sel", IMX_ADMA_ACM_SAI0_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x0E0000, 0, 2 },
138 …sel", IMX_ADMA_ACM_SAI1_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x0F0000, 0, 2 },
139 …sel", IMX_ADMA_ACM_SAI2_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x100000, 0, 2 },
[all …]
/openbmc/linux/sound/soc/codecs/
H A Dcs43130.h17 #define CS43130_FIRSTREG 0x010000
18 #define CS43130_LASTREG 0x190000
19 #define CS43130_CHIP_ID 0x00043130
20 #define CS4399_CHIP_ID 0x00043990
21 #define CS43131_CHIP_ID 0x00043131
22 #define CS43198_CHIP_ID 0x00043198
23 #define CS43130_DEVID_AB 0x010000 /* Device ID A & B [RO] */
24 #define CS43130_DEVID_CD 0x010001 /* Device ID C & D [RO] */
25 #define CS43130_DEVID_E 0x010002 /* Device ID E [RO] */
26 #define CS43130_FAB_ID 0x010003 /* Fab ID [RO] */
[all …]
/openbmc/linux/drivers/staging/rtl8192e/rtl8192e/
H A Dr8192E_phyreg.h10 #define RF_DATA 0x1d4
12 #define rPMAC_Reset 0x100
13 #define rPMAC_TxStart 0x104
14 #define rPMAC_TxLegacySIG 0x108
15 #define rPMAC_TxHTSIG1 0x10c
16 #define rPMAC_TxHTSIG2 0x110
17 #define rPMAC_PHYDebug 0x114
18 #define rPMAC_TxPacketNum 0x118
19 #define rPMAC_TxIdle 0x11c
20 #define rPMAC_TxMACHeader0 0x120
[all …]
/openbmc/linux/drivers/staging/rtl8712/
H A Drtl871x_mp_phy_regdef.h36 * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
38 * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
39 * 3. RF register 0x00-2E
44 * 1. Page1(0x100)
46 #define rPMAC_Reset 0x100
47 #define rPMAC_TxStart 0x104
48 #define rPMAC_TxLegacySIG 0x108
49 #define rPMAC_TxHTSIG1 0x10c
50 #define rPMAC_TxHTSIG2 0x110
51 #define rPMAC_PHYDebug 0x114
[all …]
/openbmc/linux/drivers/staging/rtl8723bs/include/
H A DHal8192CPhyReg.h41 /* BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF */
43 /* 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 */
44 /* 3. RF register 0x00-2E */
52 /* 1. Page1(0x100) */
54 #define rPMAC_Reset 0x100
55 #define rPMAC_TxStart 0x104
56 #define rPMAC_TxLegacySIG 0x108
57 #define rPMAC_TxHTSIG1 0x10c
58 #define rPMAC_TxHTSIG2 0x110
59 #define rPMAC_PHYDebug 0x114
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/dispnv50/
H A Ddisp.c86 if (ret < 0) in nv50_chan_create()
89 while (oclass[0]) { in nv50_chan_create()
90 for (i = 0; i < n; i++) { in nv50_chan_create()
91 if (sclass[i].oclass == oclass[0]) { in nv50_chan_create()
92 ret = nvif_object_ctor(disp, "kmsChan", 0, in nv50_chan_create()
93 oclass[0], data, size, in nv50_chan_create()
95 if (ret == 0) in nv50_chan_create()
96 nvif_object_map(&chan->user, NULL, 0); in nv50_chan_create()
141 nvif_wr32(&device->object, 0x070000, 0x00000001); in nv50_dmac_kick()
143 if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002)) in nv50_dmac_kick()
[all …]
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1028a.dtsi23 #size-cells = <0>;
25 cpu0: cpu@0 {
28 reg = <0x0>;
30 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
31 i-cache-size = <0xc000>;
34 d-cache-size = <0x8000>;
45 reg = <0x1>;
47 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
48 i-cache-size = <0xc000>;
51 d-cache-size = <0x8000>;
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/
H A Dreg.h7 #define REG_SYS_ISO_CTRL 0x0000
8 #define REG_SYS_FUNC_EN 0x0002
9 #define REG_APS_FSMCO 0x0004
10 #define REG_SYS_CLKR 0x0008
11 #define REG_9346CR 0x000A
12 #define REG_EE_VPD 0x000C
13 #define REG_AFE_MISC 0x0010
14 #define REG_SPS0_CTRL 0x0011
15 #define REG_SPS_OCP_CFG 0x0018
16 #define REG_RSV_CTRL 0x001C
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/
H A Dreg.h7 #define REG_SYS_ISO_CTRL 0x0000
8 #define REG_SYS_FUNC_EN 0x0002
9 #define REG_APS_FSMCO 0x0004
10 #define REG_SYS_CLKR 0x0008
11 #define REG_9346CR 0x000A
12 #define REG_EE_VPD 0x000C
13 #define REG_AFE_MISC 0x0010
14 #define REG_SPS0_CTRL 0x0011
15 #define REG_SPS_OCP_CFG 0x0018
16 #define REG_RSV_CTRL 0x001C
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/
H A Dreg.h7 #define TXPKT_BUF_SELECT 0x69
8 #define RXPKT_BUF_SELECT 0xA5
9 #define DISABLE_TRXPKT_BUF_ACCESS 0x0
11 #define REG_SYS_ISO_CTRL 0x0000
12 #define REG_SYS_FUNC_EN 0x0002
13 #define REG_APS_FSMCO 0x0004
14 #define REG_SYS_CLKR 0x0008
15 #define REG_9346CR 0x000A
16 #define REG_EE_VPD 0x000C
17 #define REG_SYS_SWR_CTRL1 0x0010
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/
H A Dreg.h7 #define TXPKT_BUF_SELECT 0x69
8 #define RXPKT_BUF_SELECT 0xA5
9 #define DISABLE_TRXPKT_BUF_ACCESS 0x0
11 #define REG_SYS_ISO_CTRL 0x0000
12 #define REG_SYS_FUNC_EN 0x0002
13 #define REG_APS_FSMCO 0x0004
14 #define REG_SYS_CLKR 0x0008
15 #define REG_9346CR 0x000A
16 #define REG_EE_VPD 0x000C
17 #define REG_AFE_MISC 0x0010
[all …]

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