Lines Matching +full:0 +full:x070000
86 if (ret < 0) in nv50_chan_create()
89 while (oclass[0]) { in nv50_chan_create()
90 for (i = 0; i < n; i++) { in nv50_chan_create()
91 if (sclass[i].oclass == oclass[0]) { in nv50_chan_create()
92 ret = nvif_object_ctor(disp, "kmsChan", 0, in nv50_chan_create()
93 oclass[0], data, size, in nv50_chan_create()
95 if (ret == 0) in nv50_chan_create()
96 nvif_object_map(&chan->user, NULL, 0); in nv50_chan_create()
141 nvif_wr32(&device->object, 0x070000, 0x00000001); in nv50_dmac_kick()
143 if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002)) in nv50_dmac_kick()
171 if (get == 0) { in nv50_dmac_wind()
173 if (dmac->put == 0) in nv50_dmac_wind()
177 if (NVIF_TV32(&dmac->base.user, NV507C, GET, PTR, >, 0)) in nv50_dmac_wind()
179 ) < 0) in nv50_dmac_wind()
183 PUSH_RSVD(dmac->push, PUSH_JUMP(dmac->push, 0)); in nv50_dmac_wind()
184 dmac->cur = 0; in nv50_dmac_wind()
185 return 0; in nv50_dmac_wind()
211 ) < 0) { in nv50_dmac_wait()
220 return 0; in nv50_dmac_wait()
248 if ((nv50_dmac_vram_pushbuf > 0) || in nv50_dmac_create()
249 (nv50_dmac_vram_pushbuf < 0 && device->info.family == NV_DEVICE_INFO_V0_PASCAL)) in nv50_dmac_create()
252 ret = nvif_mem_ctor_map(&cli->mmu, "kmsChanPush", type, 0x1000, in nv50_dmac_create()
264 dmac->max = 0x1000/4 - 1; in nv50_dmac_create()
279 if (syncbuf < 0) in nv50_dmac_create()
280 return 0; in nv50_dmac_create()
287 .start = syncbuf + 0x0000, in nv50_dmac_create()
288 .limit = syncbuf + 0x0fff, in nv50_dmac_create()
299 .start = 0, in nv50_dmac_create()
335 return 0; in nv50_outp_atomic_check_view()
364 return 0; in nv50_outp_atomic_check_view()
417 return 0; in nv50_outp_atomic_check()
491 u32 ctrl = 0; in nv50_dac_atomic_enable()
494 case 0: ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, OWNER, HEAD0); break; in nv50_dac_atomic_enable()
508 asyh->or.depth = 0; in nv50_dac_atomic_enable()
521 if (loadval == 0) in nv50_dac_detect()
525 if (ret <= 0) in nv50_dac_detect()
577 encoder->possible_clones = 0; in nv50_dac_create()
607 int ret = 0; in nv50_audio_component_get_eld()
660 return 0; in nv50_audio_component_bind()
733 nvif_outp_hda_eld(&nv_encoder->outp, nv_crtc->index, NULL, 0); in nv50_audio_disable()
775 union hdmi_infoframe infoframe = { 0 }; in nv50_hdmi_enable()
777 u8 scdc = 0; in nv50_hdmi_enable()
782 } args = { 0 }; in nv50_hdmi_enable()
794 if (ret < 0) { in nv50_hdmi_enable()
806 if (ret < 0) in nv50_hdmi_enable()
807 NV_ERROR(drm, "Failure to write SCDC_TMDS_CONFIG = 0x%02x: %d\n", in nv50_hdmi_enable()
817 args.infoframe.version = 0; in nv50_hdmi_enable()
826 size = 0; in nv50_hdmi_enable()
832 memset(&args.data, 0, sizeof(args.data)); in nv50_hdmi_enable()
837 size = 0; in nv50_hdmi_enable()
927 nvif_outp_dp_mst_vcpi(&mstm->outp->outp, msto->head->base.index, 0, 0, 0, 0); in nv50_msto_prepare()
958 return 0; in nv50_msto_atomic_check()
984 if (slots < 0) in nv50_msto_atomic_check()
989 return 0; in nv50_msto_atomic_check()
1031 nvif_outp_acquire_dp(&mstm->outp->outp, mstm->outp->dp.dpcd, 0, 0, false, true); in nv50_msto_atomic_enable()
1054 mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0); in nv50_msto_atomic_disable()
1137 int ret = 0; in nv50_mstc_get_modes()
1183 if (ret < 0 && ret != -EACCES) { in nv50_mstc_detect()
1265 drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0); in nv50_mstc_new()
1266 drm_object_attach_property(&mstc->connector.base, dev->mode_config.tile_property, 0); in nv50_mstc_new()
1269 return 0; in nv50_mstc_new()
1409 return 0; in nv50_mstm_detect()
1416 ret = drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0); in nv50_mstm_detect()
1417 if (ret < 0) in nv50_mstm_detect()
1453 int ret = 0; in nv50_mstm_init()
1502 return 0; in nv50_mstm_new()
1518 nv_encoder->ctrl = 0; in nv50_sor_update()
1550 if (ret < 0) in nv50_sor_atomic_disable()
1559 if (ret == 0) { in nv50_sor_atomic_disable()
1566 nv_encoder->update(nv_encoder, nv_crtc->index, NULL, 0, 0); in nv50_sor_atomic_disable()
1605 nvif_outp_acquire_tmds(outp, nv_crtc->index, false, 0, 0, 0, false); in nv50_sor_atomic_enable()
1655 nvif_outp_acquire_dp(&nv_encoder->outp, nv_encoder->dp.dpcd, 0, 0, hda, false); in nv50_sor_atomic_enable()
1716 return data && ver >= 0x40 && (nvbios_rd08(bios, data + 0x08) & 0x04); in nv50_has_mst()
1747 encoder->possible_clones = 0; in nv50_sor_create()
1806 return 0; in nv50_pior_atomic_check()
1829 u32 ctrl = 0; in nv50_pior_atomic_enable()
1832 case 0: ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, HEAD0); break; in nv50_pior_atomic_enable()
1849 nvif_outp_acquire_tmds(&nv_encoder->outp, false, false, 0, 0, 0, false); in nv50_pior_atomic_enable()
1853 nvif_outp_acquire_dp(&nv_encoder->outp, nv_encoder->dp.dpcd, 0, 0, false, false); in nv50_pior_atomic_enable()
1929 encoder->possible_clones = 0; in nv50_pior_create()
2071 memset(interlock, 0x00, sizeof(interlock)); in nv50_disp_atomic_commit_tail()
2083 memset(interlock, 0x00, sizeof(interlock)); in nv50_disp_atomic_commit_tail()
2148 interlock[NV50_DISP_INTERLOCK_CORE] = 0; in nv50_disp_atomic_commit_tail()
2264 if (ret < 0 && ret != -EACCES) { in nv50_disp_atomic_commit()
2347 return 0; in nv50_disp_outp_atomic_check_clr()
2364 return 0; in nv50_disp_outp_atomic_check_clr()
2377 return 0; in nv50_disp_outp_atomic_check_set()
2389 return 0; in nv50_disp_outp_atomic_check_set()
2447 return 0; in nv50_disp_atomic_check()
2477 drm_atomic_state_init(dev, &atom->state) < 0) { in nv50_disp_atomic_state_alloc()
2537 return 0; in nv50_display_init()
2589 ret = nouveau_bo_new(&drm->client, 4096, 0x1000, in nv50_display_create()
2591 0, 0x0000, NULL, NULL, &disp->sync); in nv50_display_create()
2648 crtcs = nvif_rd32(&device->object, 0x610060) & 0xff; in nv50_display_create()
2651 crtcs = nvif_rd32(&device->object, 0x612004) & 0xf; in nv50_display_create()
2653 crtcs = 0x3; in nv50_display_create()
2655 for (i = 0; i < fls(crtcs); i++) { in nv50_display_create()
2690 for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) { in nv50_display_create()
2717 ret = 0; in nv50_display_create()
2753 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 0),
2754 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 1),
2755 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 2),
2756 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 3),
2757 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 4),
2758 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 5),
2759 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 0),
2760 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 1),
2761 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 2),
2762 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 3),
2763 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 4),
2764 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 5),
2765 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 0),
2766 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 1),
2767 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 2),
2768 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 3),
2769 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 4),
2770 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 5),
2782 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 0),
2783 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 1),
2784 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 2),
2785 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 3),
2786 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 4),
2787 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 5),