| /openbmc/u-boot/arch/arm/mach-sunxi/dram_timings/ |
| H A D | ddr2_v3s.c | 16 u8 twtr = max(ns_to_t(8), 2); in mctl_set_timing_params() local
44 u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */ in mctl_set_timing_params()
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| H A D | ddr3_1333.c | 16 u8 twtr = max(ns_to_t(8), 4); in mctl_set_timing_params() local
44 u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */ in mctl_set_timing_params()
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| H A D | lpddr3_stock.c | 16 u8 twtr = max(ns_to_t(8), 2); in mctl_set_timing_params() local
44 u8 twr2rd = tcwl + 4 + 1 + twtr; in mctl_set_timing_params()
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| /openbmc/u-boot/arch/arm/mach-sunxi/ |
| H A D | dram_sun8i_a83t.c | 98 u8 twtr = max(ns_to_t(8), 4); in auto_set_timing_para() local
127 u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */ in auto_set_timing_para()
150 twtr = max(ns_to_t(8), 2); in auto_set_timing_para()
166 twr2rd = tcwl + 4 + 1 + twtr; /* WL + BL / 2 + tWTR */ in auto_set_timing_para()
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| H A D | dram_sun8i_a33.c | 98 u8 twtr = max(ns_to_t(8), 4); in auto_set_timing_para() local
127 u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */ in auto_set_timing_para()
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| H A D | dram_sun50i_h6.c | 192 u8 twtr = max(ns_to_t(8), 2); in mctl_set_timing_lpddr3() local
237 u8 twr2rd = tcwl + 4 + 1 + twtr; in mctl_set_timing_lpddr3()
275 writel((trc << 17) | (trcd << 9) | (twtr << 1), &mctl_phy->dtpr[5]); in mctl_set_timing_lpddr3()
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| /openbmc/u-boot/arch/arm/mach-imx/mx6/ |
| H A D | ddr.c | 1000 u16 tras, twr, tmrd, trtp, twtr, trfc, txsr; in mx6_lpddr2_cfg() local
1067 twtr = DIV_ROUND_UP(7500, clkper) - 1; in mx6_lpddr2_cfg()
1093 debug("twtr=%d\n", twtr); in mx6_lpddr2_cfg()
1143 mmdc0->mdcfg2 = (trtp << 6) | (twtr << 3) | trrd; in mx6_lpddr2_cfg()
1231 u16 trcd, trc, tras, twr, tmrd, trtp, trp, twtr, trfc, txs, txpr; in mx6_ddr3_cfg() local
1338 twtr = ROUND(max(4 * clkper, 7500) / clkper, 1) - 1; in mx6_ddr3_cfg()
1340 trtp = twtr; in mx6_ddr3_cfg()
1370 debug("twtr=%d\n", twtr); in mx6_ddr3_cfg()
1437 mmdc0->mdcfg2 = (tdllk << 16) | (trtp << 6) | (twtr << 3) | trrd; in mx6_ddr3_cfg()
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| /openbmc/u-boot/include/ |
| H A D | spd.h | 52 unsigned char twtr; /* 37 Int write to read delay tWTR */ member
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| H A D | ddr_spd.h | 116 unsigned char twtr; /* 37 Int write to read delay tWTR */ member
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| /openbmc/u-boot/arch/arm/include/asm/arch-omap3/ |
| H A D | mem.h | 82 #define ACTIM_CTRLB(twtr, tcke, txp, txsr) \ argument
83 ACTIM_CTRLB_TWTR(twtr) | \
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| /openbmc/u-boot/arch/arm/include/asm/arch-vf610/ |
| H A D | ddrmc-vf610.h | 25 u8 twtr; member
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| /openbmc/u-boot/arch/arm/include/asm/arch-rockchip/ |
| H A D | sdram.h | 62 u32 twtr; member
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| H A D | sdram_rk3036.h | 59 u32 twtr; member
256 u32 twtr; member
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| H A D | sdram_rk322x.h | 95 u32 twtr; member
221 u32 twtr; member
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| H A D | ddr_rk3368.h | 63 u32 twtr; member
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| H A D | ddr_rk3288.h | 58 u32 twtr; member
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| /openbmc/u-boot/doc/device-tree-bindings/misc/ |
| H A D | intel,baytrail-fsp.txt | 84 - fsp,dimm-twtr
147 fsp,dimm-twtr = <6>;
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| /openbmc/u-boot/drivers/ddr/fsl/ |
| H A D | ddr2_dimm_params.c | 310 pdimm->twtr_ps = spd->twtr * 250; in ddr_compute_dimm_parameters()
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| /openbmc/u-boot/board/phytec/pcm052/ |
| H A D | pcm052.c | 221 .twtr = 4, in dram_init()
276 .twtr = 4, in dram_init()
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| /openbmc/linux/arch/mips/include/asm/octeon/ |
| H A D | cvmx-lmcx-defs.h | 1832 uint64_t twtr:4; member
1838 uint64_t twtr:4;
1856 uint64_t twtr:4; member
1862 uint64_t twtr:4;
2693 uint64_t twtr:4; member
2701 uint64_t twtr:4;
2723 uint64_t twtr:4; member
2731 uint64_t twtr:4;
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| /openbmc/u-boot/arch/arm/mach-imx/ |
| H A D | ddrmc-vf610.c | 131 DDRMC_CR14_TWTR(timings->twtr) | in ddrmc_ctrl_init_ddr3()
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| /openbmc/u-boot/board/freescale/vf610twr/ |
| H A D | vf610twr.c | 99 .twtr = 4, in dram_init()
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| /openbmc/u-boot/arch/arm/include/asm/arch-sunxi/ |
| H A D | dram_sun6i.h | 86 u32 twtr; /* 0x108 */ member
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| /openbmc/u-boot/doc/device-tree-bindings/clock/ |
| H A D | rockchip,rk3288-dmc.txt | 72 twtr
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| /openbmc/u-boot/board/toradex/colibri_vf/ |
| H A D | colibri_vf.c | 111 .twtr = 4, in dram_init()
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