1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0 */ 25ff093abSSimon Glass /* 35ff093abSSimon Glass * (C) Copyright 2015 Google, Inc 45ff093abSSimon Glass */ 55ff093abSSimon Glass 65ff093abSSimon Glass #ifndef _ASM_ARCH_DDR_RK3288_H 75ff093abSSimon Glass #define _ASM_ARCH_DDR_RK3288_H 85ff093abSSimon Glass 95ff093abSSimon Glass struct rk3288_ddr_pctl { 105ff093abSSimon Glass u32 scfg; 115ff093abSSimon Glass u32 sctl; 125ff093abSSimon Glass u32 stat; 135ff093abSSimon Glass u32 intrstat; 145ff093abSSimon Glass u32 reserved0[12]; 155ff093abSSimon Glass u32 mcmd; 165ff093abSSimon Glass u32 powctl; 175ff093abSSimon Glass u32 powstat; 185ff093abSSimon Glass u32 cmdtstat; 195ff093abSSimon Glass u32 tstaten; 205ff093abSSimon Glass u32 reserved1[3]; 215ff093abSSimon Glass u32 mrrcfg0; 225ff093abSSimon Glass u32 mrrstat0; 235ff093abSSimon Glass u32 mrrstat1; 245ff093abSSimon Glass u32 reserved2[4]; 255ff093abSSimon Glass u32 mcfg1; 265ff093abSSimon Glass u32 mcfg; 275ff093abSSimon Glass u32 ppcfg; 285ff093abSSimon Glass u32 mstat; 295ff093abSSimon Glass u32 lpddr2zqcfg; 305ff093abSSimon Glass u32 reserved3; 315ff093abSSimon Glass u32 dtupdes; 325ff093abSSimon Glass u32 dtuna; 335ff093abSSimon Glass u32 dtune; 345ff093abSSimon Glass u32 dtuprd0; 355ff093abSSimon Glass u32 dtuprd1; 365ff093abSSimon Glass u32 dtuprd2; 375ff093abSSimon Glass u32 dtuprd3; 385ff093abSSimon Glass u32 dtuawdt; 395ff093abSSimon Glass u32 reserved4[3]; 405ff093abSSimon Glass u32 togcnt1u; 415ff093abSSimon Glass u32 tinit; 425ff093abSSimon Glass u32 trsth; 435ff093abSSimon Glass u32 togcnt100n; 445ff093abSSimon Glass u32 trefi; 455ff093abSSimon Glass u32 tmrd; 465ff093abSSimon Glass u32 trfc; 475ff093abSSimon Glass u32 trp; 485ff093abSSimon Glass u32 trtw; 495ff093abSSimon Glass u32 tal; 505ff093abSSimon Glass u32 tcl; 515ff093abSSimon Glass u32 tcwl; 525ff093abSSimon Glass u32 tras; 535ff093abSSimon Glass u32 trc; 545ff093abSSimon Glass u32 trcd; 555ff093abSSimon Glass u32 trrd; 565ff093abSSimon Glass u32 trtp; 575ff093abSSimon Glass u32 twr; 585ff093abSSimon Glass u32 twtr; 595ff093abSSimon Glass u32 texsr; 605ff093abSSimon Glass u32 txp; 615ff093abSSimon Glass u32 txpdll; 625ff093abSSimon Glass u32 tzqcs; 635ff093abSSimon Glass u32 tzqcsi; 645ff093abSSimon Glass u32 tdqs; 655ff093abSSimon Glass u32 tcksre; 665ff093abSSimon Glass u32 tcksrx; 675ff093abSSimon Glass u32 tcke; 685ff093abSSimon Glass u32 tmod; 695ff093abSSimon Glass u32 trstl; 705ff093abSSimon Glass u32 tzqcl; 715ff093abSSimon Glass u32 tmrr; 725ff093abSSimon Glass u32 tckesr; 735ff093abSSimon Glass u32 tdpd; 745ff093abSSimon Glass u32 reserved5[14]; 755ff093abSSimon Glass u32 ecccfg; 765ff093abSSimon Glass u32 ecctst; 775ff093abSSimon Glass u32 eccclr; 785ff093abSSimon Glass u32 ecclog; 795ff093abSSimon Glass u32 reserved6[28]; 805ff093abSSimon Glass u32 dtuwactl; 815ff093abSSimon Glass u32 dturactl; 825ff093abSSimon Glass u32 dtucfg; 835ff093abSSimon Glass u32 dtuectl; 845ff093abSSimon Glass u32 dtuwd0; 855ff093abSSimon Glass u32 dtuwd1; 865ff093abSSimon Glass u32 dtuwd2; 875ff093abSSimon Glass u32 dtuwd3; 885ff093abSSimon Glass u32 dtuwdm; 895ff093abSSimon Glass u32 dturd0; 905ff093abSSimon Glass u32 dturd1; 915ff093abSSimon Glass u32 dturd2; 925ff093abSSimon Glass u32 dturd3; 935ff093abSSimon Glass u32 dtulfsrwd; 945ff093abSSimon Glass u32 dtulfsrrd; 955ff093abSSimon Glass u32 dtueaf; 965ff093abSSimon Glass u32 dfitctrldelay; 975ff093abSSimon Glass u32 dfiodtcfg; 985ff093abSSimon Glass u32 dfiodtcfg1; 995ff093abSSimon Glass u32 dfiodtrankmap; 1005ff093abSSimon Glass u32 dfitphywrdata; 1015ff093abSSimon Glass u32 dfitphywrlat; 1025ff093abSSimon Glass u32 reserved7[2]; 1035ff093abSSimon Glass u32 dfitrddataen; 1045ff093abSSimon Glass u32 dfitphyrdlat; 1055ff093abSSimon Glass u32 reserved8[2]; 1065ff093abSSimon Glass u32 dfitphyupdtype0; 1075ff093abSSimon Glass u32 dfitphyupdtype1; 1085ff093abSSimon Glass u32 dfitphyupdtype2; 1095ff093abSSimon Glass u32 dfitphyupdtype3; 1105ff093abSSimon Glass u32 dfitctrlupdmin; 1115ff093abSSimon Glass u32 dfitctrlupdmax; 1125ff093abSSimon Glass u32 dfitctrlupddly; 1135ff093abSSimon Glass u32 reserved9; 1145ff093abSSimon Glass u32 dfiupdcfg; 1155ff093abSSimon Glass u32 dfitrefmski; 1165ff093abSSimon Glass u32 dfitctrlupdi; 1175ff093abSSimon Glass u32 reserved10[4]; 1185ff093abSSimon Glass u32 dfitrcfg0; 1195ff093abSSimon Glass u32 dfitrstat0; 1205ff093abSSimon Glass u32 dfitrwrlvlen; 1215ff093abSSimon Glass u32 dfitrrdlvlen; 1225ff093abSSimon Glass u32 dfitrrdlvlgateen; 1235ff093abSSimon Glass u32 dfiststat0; 1245ff093abSSimon Glass u32 dfistcfg0; 1255ff093abSSimon Glass u32 dfistcfg1; 1265ff093abSSimon Glass u32 reserved11; 1275ff093abSSimon Glass u32 dfitdramclken; 1285ff093abSSimon Glass u32 dfitdramclkdis; 1295ff093abSSimon Glass u32 dfistcfg2; 1305ff093abSSimon Glass u32 dfistparclr; 1315ff093abSSimon Glass u32 dfistparlog; 1325ff093abSSimon Glass u32 reserved12[3]; 1335ff093abSSimon Glass u32 dfilpcfg0; 1345ff093abSSimon Glass u32 reserved13[3]; 1355ff093abSSimon Glass u32 dfitrwrlvlresp0; 1365ff093abSSimon Glass u32 dfitrwrlvlresp1; 1375ff093abSSimon Glass u32 dfitrwrlvlresp2; 1385ff093abSSimon Glass u32 dfitrrdlvlresp0; 1395ff093abSSimon Glass u32 dfitrrdlvlresp1; 1405ff093abSSimon Glass u32 dfitrrdlvlresp2; 1415ff093abSSimon Glass u32 dfitrwrlvldelay0; 1425ff093abSSimon Glass u32 dfitrwrlvldelay1; 1435ff093abSSimon Glass u32 dfitrwrlvldelay2; 1445ff093abSSimon Glass u32 dfitrrdlvldelay0; 1455ff093abSSimon Glass u32 dfitrrdlvldelay1; 1465ff093abSSimon Glass u32 dfitrrdlvldelay2; 1475ff093abSSimon Glass u32 dfitrrdlvlgatedelay0; 1485ff093abSSimon Glass u32 dfitrrdlvlgatedelay1; 1495ff093abSSimon Glass u32 dfitrrdlvlgatedelay2; 1505ff093abSSimon Glass u32 dfitrcmd; 1515ff093abSSimon Glass u32 reserved14[46]; 1525ff093abSSimon Glass u32 ipvr; 1535ff093abSSimon Glass u32 iptr; 1545ff093abSSimon Glass }; 1555ff093abSSimon Glass check_member(rk3288_ddr_pctl, iptr, 0x03fc); 1565ff093abSSimon Glass 1575ff093abSSimon Glass struct rk3288_ddr_publ_datx { 1585ff093abSSimon Glass u32 dxgcr; 1595ff093abSSimon Glass u32 dxgsr[2]; 1605ff093abSSimon Glass u32 dxdllcr; 1615ff093abSSimon Glass u32 dxdqtr; 1625ff093abSSimon Glass u32 dxdqstr; 1635ff093abSSimon Glass u32 reserved[10]; 1645ff093abSSimon Glass }; 1655ff093abSSimon Glass 1665ff093abSSimon Glass struct rk3288_ddr_publ { 1675ff093abSSimon Glass u32 ridr; 1685ff093abSSimon Glass u32 pir; 1695ff093abSSimon Glass u32 pgcr; 1705ff093abSSimon Glass u32 pgsr; 1715ff093abSSimon Glass u32 dllgcr; 1725ff093abSSimon Glass u32 acdllcr; 1735ff093abSSimon Glass u32 ptr[3]; 1745ff093abSSimon Glass u32 aciocr; 1755ff093abSSimon Glass u32 dxccr; 1765ff093abSSimon Glass u32 dsgcr; 1775ff093abSSimon Glass u32 dcr; 1785ff093abSSimon Glass u32 dtpr[3]; 1795ff093abSSimon Glass u32 mr[4]; 1805ff093abSSimon Glass u32 odtcr; 1815ff093abSSimon Glass u32 dtar; 1825ff093abSSimon Glass u32 dtdr[2]; 1835ff093abSSimon Glass u32 reserved1[24]; 1845ff093abSSimon Glass u32 dcuar; 1855ff093abSSimon Glass u32 dcudr; 1865ff093abSSimon Glass u32 dcurr; 1875ff093abSSimon Glass u32 dculr; 1885ff093abSSimon Glass u32 dcugcr; 1895ff093abSSimon Glass u32 dcutpr; 1905ff093abSSimon Glass u32 dcusr[2]; 1915ff093abSSimon Glass u32 reserved2[8]; 1925ff093abSSimon Glass u32 bist[17]; 1935ff093abSSimon Glass u32 reserved3[15]; 1945ff093abSSimon Glass u32 zq0cr[2]; 1955ff093abSSimon Glass u32 zq0sr[2]; 1965ff093abSSimon Glass u32 zq1cr[2]; 1975ff093abSSimon Glass u32 zq1sr[2]; 1985ff093abSSimon Glass u32 zq2cr[2]; 1995ff093abSSimon Glass u32 zq2sr[2]; 2005ff093abSSimon Glass u32 zq3cr[2]; 2015ff093abSSimon Glass u32 zq3sr[2]; 2025ff093abSSimon Glass struct rk3288_ddr_publ_datx datx8[4]; 2035ff093abSSimon Glass }; 2045ff093abSSimon Glass check_member(rk3288_ddr_publ, datx8[3].dxdqstr, 0x0294); 2055ff093abSSimon Glass 2065ff093abSSimon Glass struct rk3288_msch { 2075ff093abSSimon Glass u32 coreid; 2085ff093abSSimon Glass u32 revisionid; 2095ff093abSSimon Glass u32 ddrconf; 2105ff093abSSimon Glass u32 ddrtiming; 2115ff093abSSimon Glass u32 ddrmode; 2125ff093abSSimon Glass u32 readlatency; 2135ff093abSSimon Glass u32 reserved1[8]; 2145ff093abSSimon Glass u32 activate; 2155ff093abSSimon Glass u32 devtodev; 2165ff093abSSimon Glass }; 2175ff093abSSimon Glass check_member(rk3288_msch, devtodev, 0x003c); 2185ff093abSSimon Glass 2195ff093abSSimon Glass /* PCT_DFISTCFG0 */ 2205ff093abSSimon Glass #define DFI_INIT_START (1 << 0) 2215ff093abSSimon Glass 2225ff093abSSimon Glass /* PCT_DFISTCFG1 */ 2235ff093abSSimon Glass #define DFI_DRAM_CLK_SR_EN (1 << 0) 2245ff093abSSimon Glass #define DFI_DRAM_CLK_DPD_EN (1 << 1) 2255ff093abSSimon Glass 2265ff093abSSimon Glass /* PCT_DFISTCFG2 */ 2275ff093abSSimon Glass #define DFI_PARITY_INTR_EN (1 << 0) 2285ff093abSSimon Glass #define DFI_PARITY_EN (1 << 1) 2295ff093abSSimon Glass 2305ff093abSSimon Glass /* PCT_DFILPCFG0 */ 2315ff093abSSimon Glass #define TLP_RESP_TIME_SHIFT 16 2325ff093abSSimon Glass #define LP_SR_EN (1 << 8) 2335ff093abSSimon Glass #define LP_PD_EN (1 << 0) 2345ff093abSSimon Glass 2355ff093abSSimon Glass /* PCT_DFITCTRLDELAY */ 2365ff093abSSimon Glass #define TCTRL_DELAY_TIME_SHIFT 0 2375ff093abSSimon Glass 2385ff093abSSimon Glass /* PCT_DFITPHYWRDATA */ 2395ff093abSSimon Glass #define TPHY_WRDATA_TIME_SHIFT 0 2405ff093abSSimon Glass 2415ff093abSSimon Glass /* PCT_DFITPHYRDLAT */ 2425ff093abSSimon Glass #define TPHY_RDLAT_TIME_SHIFT 0 2435ff093abSSimon Glass 2445ff093abSSimon Glass /* PCT_DFITDRAMCLKDIS */ 2455ff093abSSimon Glass #define TDRAM_CLK_DIS_TIME_SHIFT 0 2465ff093abSSimon Glass 2475ff093abSSimon Glass /* PCT_DFITDRAMCLKEN */ 2485ff093abSSimon Glass #define TDRAM_CLK_EN_TIME_SHIFT 0 2495ff093abSSimon Glass 2505ff093abSSimon Glass /* PCTL_DFIODTCFG */ 2515ff093abSSimon Glass #define RANK0_ODT_WRITE_SEL (1 << 3) 2525ff093abSSimon Glass #define RANK1_ODT_WRITE_SEL (1 << 11) 2535ff093abSSimon Glass 2545ff093abSSimon Glass /* PCTL_DFIODTCFG1 */ 2555ff093abSSimon Glass #define ODT_LEN_BL8_W_SHIFT 16 2565ff093abSSimon Glass 2575ff093abSSimon Glass /* PUBL_ACDLLCR */ 2585ff093abSSimon Glass #define ACDLLCR_DLLDIS (1 << 31) 2595ff093abSSimon Glass #define ACDLLCR_DLLSRST (1 << 30) 2605ff093abSSimon Glass 2615ff093abSSimon Glass /* PUBL_DXDLLCR */ 2625ff093abSSimon Glass #define DXDLLCR_DLLDIS (1 << 31) 2635ff093abSSimon Glass #define DXDLLCR_DLLSRST (1 << 30) 2645ff093abSSimon Glass 2655ff093abSSimon Glass /* PUBL_DLLGCR */ 2665ff093abSSimon Glass #define DLLGCR_SBIAS (1 << 30) 2675ff093abSSimon Glass 2685ff093abSSimon Glass /* PUBL_DXGCR */ 2695ff093abSSimon Glass #define DQSRTT (1 << 9) 2705ff093abSSimon Glass #define DQRTT (1 << 10) 2715ff093abSSimon Glass 2725ff093abSSimon Glass /* PIR */ 2735ff093abSSimon Glass #define PIR_INIT (1 << 0) 2745ff093abSSimon Glass #define PIR_DLLSRST (1 << 1) 2755ff093abSSimon Glass #define PIR_DLLLOCK (1 << 2) 2765ff093abSSimon Glass #define PIR_ZCAL (1 << 3) 2775ff093abSSimon Glass #define PIR_ITMSRST (1 << 4) 2785ff093abSSimon Glass #define PIR_DRAMRST (1 << 5) 2795ff093abSSimon Glass #define PIR_DRAMINIT (1 << 6) 2805ff093abSSimon Glass #define PIR_QSTRN (1 << 7) 2815ff093abSSimon Glass #define PIR_RVTRN (1 << 8) 2825ff093abSSimon Glass #define PIR_ICPC (1 << 16) 2835ff093abSSimon Glass #define PIR_DLLBYP (1 << 17) 2845ff093abSSimon Glass #define PIR_CTLDINIT (1 << 18) 2855ff093abSSimon Glass #define PIR_CLRSR (1 << 28) 2865ff093abSSimon Glass #define PIR_LOCKBYP (1 << 29) 2875ff093abSSimon Glass #define PIR_ZCALBYP (1 << 30) 2885ff093abSSimon Glass #define PIR_INITBYP (1u << 31) 2895ff093abSSimon Glass 2905ff093abSSimon Glass /* PGCR */ 2915ff093abSSimon Glass #define PGCR_DFTLMT_SHIFT 3 2925ff093abSSimon Glass #define PGCR_DFTCMP_SHIFT 2 2935ff093abSSimon Glass #define PGCR_DQSCFG_SHIFT 1 2945ff093abSSimon Glass #define PGCR_ITMDMD_SHIFT 0 2955ff093abSSimon Glass 2965ff093abSSimon Glass /* PGSR */ 2975ff093abSSimon Glass #define PGSR_IDONE (1 << 0) 2985ff093abSSimon Glass #define PGSR_DLDONE (1 << 1) 2995ff093abSSimon Glass #define PGSR_ZCDONE (1 << 2) 3005ff093abSSimon Glass #define PGSR_DIDONE (1 << 3) 3015ff093abSSimon Glass #define PGSR_DTDONE (1 << 4) 3025ff093abSSimon Glass #define PGSR_DTERR (1 << 5) 3035ff093abSSimon Glass #define PGSR_DTIERR (1 << 6) 3045ff093abSSimon Glass #define PGSR_DFTERR (1 << 7) 3055ff093abSSimon Glass #define PGSR_RVERR (1 << 8) 3065ff093abSSimon Glass #define PGSR_RVEIRR (1 << 9) 3075ff093abSSimon Glass 3085ff093abSSimon Glass /* PTR0 */ 3095ff093abSSimon Glass #define PRT_ITMSRST_SHIFT 18 3105ff093abSSimon Glass #define PRT_DLLLOCK_SHIFT 6 3115ff093abSSimon Glass #define PRT_DLLSRST_SHIFT 0 3125ff093abSSimon Glass 3135ff093abSSimon Glass /* PTR1 */ 3145ff093abSSimon Glass #define PRT_DINIT0_SHIFT 0 3155ff093abSSimon Glass #define PRT_DINIT1_SHIFT 19 3165ff093abSSimon Glass 3175ff093abSSimon Glass /* PTR2 */ 3185ff093abSSimon Glass #define PRT_DINIT2_SHIFT 0 3195ff093abSSimon Glass #define PRT_DINIT3_SHIFT 17 3205ff093abSSimon Glass 3215ff093abSSimon Glass /* DCR */ 3225ff093abSSimon Glass #define DDRMD_LPDDR 0 3235ff093abSSimon Glass #define DDRMD_DDR 1 3245ff093abSSimon Glass #define DDRMD_DDR2 2 3255ff093abSSimon Glass #define DDRMD_DDR3 3 3265ff093abSSimon Glass #define DDRMD_LPDDR2_LPDDR3 4 3275ff093abSSimon Glass #define DDRMD_MASK 7 3285ff093abSSimon Glass #define DDRMD_SHIFT 0 3295ff093abSSimon Glass #define PDQ_MASK 7 3305ff093abSSimon Glass #define PDQ_SHIFT 4 3315ff093abSSimon Glass 3325ff093abSSimon Glass /* DXCCR */ 3335ff093abSSimon Glass #define DQSNRES_MASK 0xf 3345ff093abSSimon Glass #define DQSNRES_SHIFT 8 3355ff093abSSimon Glass #define DQSRES_MASK 0xf 3365ff093abSSimon Glass #define DQSRES_SHIFT 4 3375ff093abSSimon Glass 3385ff093abSSimon Glass /* DTPR */ 3395ff093abSSimon Glass #define TDQSCKMAX_SHIFT 27 3405ff093abSSimon Glass #define TDQSCKMAX_MASK 7 3415ff093abSSimon Glass #define TDQSCK_SHIFT 24 3425ff093abSSimon Glass #define TDQSCK_MASK 7 3435ff093abSSimon Glass 3445ff093abSSimon Glass /* DSGCR */ 3455ff093abSSimon Glass #define DQSGX_SHIFT 5 3465ff093abSSimon Glass #define DQSGX_MASK 7 3475ff093abSSimon Glass #define DQSGE_SHIFT 8 3485ff093abSSimon Glass #define DQSGE_MASK 7 3495ff093abSSimon Glass 3505ff093abSSimon Glass /* SCTL */ 3515ff093abSSimon Glass #define INIT_STATE 0 3525ff093abSSimon Glass #define CFG_STATE 1 3535ff093abSSimon Glass #define GO_STATE 2 3545ff093abSSimon Glass #define SLEEP_STATE 3 3555ff093abSSimon Glass #define WAKEUP_STATE 4 3565ff093abSSimon Glass 3575ff093abSSimon Glass /* STAT */ 3585ff093abSSimon Glass #define LP_TRIG_SHIFT 4 3595ff093abSSimon Glass #define LP_TRIG_MASK 7 3605ff093abSSimon Glass #define PCTL_STAT_MSK 7 3615ff093abSSimon Glass #define INIT_MEM 0 3625ff093abSSimon Glass #define CONFIG 1 3635ff093abSSimon Glass #define CONFIG_REQ 2 3645ff093abSSimon Glass #define ACCESS 3 3655ff093abSSimon Glass #define ACCESS_REQ 4 3665ff093abSSimon Glass #define LOW_POWER 5 3675ff093abSSimon Glass #define LOW_POWER_ENTRY_REQ 6 3685ff093abSSimon Glass #define LOW_POWER_EXIT_REQ 7 3695ff093abSSimon Glass 3705ff093abSSimon Glass /* ZQCR*/ 3715ff093abSSimon Glass #define PD_OUTPUT_SHIFT 0 3725ff093abSSimon Glass #define PU_OUTPUT_SHIFT 5 3735ff093abSSimon Glass #define PD_ONDIE_SHIFT 10 3745ff093abSSimon Glass #define PU_ONDIE_SHIFT 15 3755ff093abSSimon Glass #define ZDEN_SHIFT 28 3765ff093abSSimon Glass 3775ff093abSSimon Glass /* DDLGCR */ 3785ff093abSSimon Glass #define SBIAS_BYPASS (1 << 23) 3795ff093abSSimon Glass 3805ff093abSSimon Glass /* MCFG */ 3815ff093abSSimon Glass #define MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT 24 3825ff093abSSimon Glass #define PD_IDLE_SHIFT 8 3835ff093abSSimon Glass #define MDDR_EN (2 << 22) 3845ff093abSSimon Glass #define LPDDR2_EN (3 << 22) 3855ff093abSSimon Glass #define DDR2_EN (0 << 5) 3865ff093abSSimon Glass #define DDR3_EN (1 << 5) 3875ff093abSSimon Glass #define LPDDR2_S2 (0 << 6) 3885ff093abSSimon Glass #define LPDDR2_S4 (1 << 6) 3895ff093abSSimon Glass #define MDDR_LPDDR2_BL_2 (0 << 20) 3905ff093abSSimon Glass #define MDDR_LPDDR2_BL_4 (1 << 20) 3915ff093abSSimon Glass #define MDDR_LPDDR2_BL_8 (2 << 20) 3925ff093abSSimon Glass #define MDDR_LPDDR2_BL_16 (3 << 20) 3935ff093abSSimon Glass #define DDR2_DDR3_BL_4 0 3945ff093abSSimon Glass #define DDR2_DDR3_BL_8 1 3955ff093abSSimon Glass #define TFAW_SHIFT 18 3965ff093abSSimon Glass #define PD_EXIT_SLOW (0 << 17) 3975ff093abSSimon Glass #define PD_EXIT_FAST (1 << 17) 3985ff093abSSimon Glass #define PD_TYPE_SHIFT 16 3995ff093abSSimon Glass #define BURSTLENGTH_SHIFT 20 4005ff093abSSimon Glass 4015ff093abSSimon Glass /* POWCTL */ 4025ff093abSSimon Glass #define POWER_UP_START (1 << 0) 4035ff093abSSimon Glass 4045ff093abSSimon Glass /* POWSTAT */ 4055ff093abSSimon Glass #define POWER_UP_DONE (1 << 0) 4065ff093abSSimon Glass 4075ff093abSSimon Glass /* MCMD */ 4085ff093abSSimon Glass enum { 4095ff093abSSimon Glass DESELECT_CMD = 0, 4105ff093abSSimon Glass PREA_CMD, 4115ff093abSSimon Glass REF_CMD, 4125ff093abSSimon Glass MRS_CMD, 4135ff093abSSimon Glass ZQCS_CMD, 4145ff093abSSimon Glass ZQCL_CMD, 4155ff093abSSimon Glass RSTL_CMD, 4165ff093abSSimon Glass MRR_CMD = 8, 4175ff093abSSimon Glass DPDE_CMD, 4185ff093abSSimon Glass }; 4195ff093abSSimon Glass 4205ff093abSSimon Glass #define LPDDR2_MA_SHIFT 4 4215ff093abSSimon Glass #define LPDDR2_MA_MASK 0xff 4225ff093abSSimon Glass #define LPDDR2_OP_SHIFT 12 4235ff093abSSimon Glass #define LPDDR2_OP_MASK 0xff 4245ff093abSSimon Glass 4255ff093abSSimon Glass #define START_CMD (1u << 31) 4265ff093abSSimon Glass 427bd7e6086SHeiko Stübner /* 428bd7e6086SHeiko Stübner * DDRCONF 429bd7e6086SHeiko Stübner * [5:4] row(13+n) 430bd7e6086SHeiko Stübner * [1:0] col(9+n), assume bw=2 431bd7e6086SHeiko Stübner */ 432bd7e6086SHeiko Stübner #define DDRCONF_ROW_SHIFT 4 433bd7e6086SHeiko Stübner #define DDRCONF_COL_SHIFT 0 434bd7e6086SHeiko Stübner 4355ff093abSSimon Glass /* DEVTODEV */ 4365ff093abSSimon Glass #define BUSWRTORD_SHIFT 4 4375ff093abSSimon Glass #define BUSRDTOWR_SHIFT 2 4385ff093abSSimon Glass #define BUSRDTORD_SHIFT 0 4395ff093abSSimon Glass 4405ff093abSSimon Glass /* mr1 for ddr3 */ 4415ff093abSSimon Glass #define DDR3_DLL_DISABLE 1 4425ff093abSSimon Glass 4435ff093abSSimon Glass #endif 444