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Searched refs:tmrd (Results 1 – 25 of 28) sorted by relevance

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/openbmc/u-boot/board/work-microwave/work_92105/
H A Dwork_92105_spl.c31 .tmrd = 1,
51 .tmrd = 1,
/openbmc/u-boot/arch/arm/mach-sunxi/dram_timings/
H A Dddr2_v3s.c25 u8 tmrd = 2; in mctl_set_timing_params() local
62 writel(DRAMTMG3_TMRW(tmrw) | DRAMTMG3_TMRD(tmrd) | DRAMTMG3_TMOD(tmod), in mctl_set_timing_params()
H A Dddr3_1333.c25 u8 tmrd = 4; in mctl_set_timing_params() local
65 writel(DRAMTMG3_TMRW(tmrw) | DRAMTMG3_TMRD(tmrd) | DRAMTMG3_TMOD(tmod), in mctl_set_timing_params()
H A Dlpddr3_stock.c25 u8 tmrd = 5; in mctl_set_timing_params() local
61 writel(DRAMTMG3_TMRW(tmrw) | DRAMTMG3_TMRD(tmrd) | DRAMTMG3_TMOD(tmod), in mctl_set_timing_params()
/openbmc/u-boot/board/timll/devkit3250/
H A Ddevkit3250_spl.c38 .tmrd = 1,
/openbmc/u-boot/drivers/ram/
H A Dstm32_sdram.c120 u8 tmrd; member
202 | timing->tmrd << FMC_SDTR_TMRD_SHIFT, in stm32_sdram_init()
212 | timing->tmrd << FMC_SDTR_TMRD_SHIFT, in stm32_sdram_init()
/openbmc/u-boot/arch/arm/mach-imx/mx6/
H A Dddr.c1000 u16 tras, twr, tmrd, trtp, twtr, trfc, txsr; in mx6_lpddr2_cfg() local
1057 tmrd = 5; in mx6_lpddr2_cfg()
1090 debug("tmrd=%d\n", tmrd); in mx6_lpddr2_cfg()
1142 mmdc0->mdcfg1 = (tras << 16) | (twr << 9) | (tmrd << 5) | twl; in mx6_lpddr2_cfg()
1231 u16 trcd, trc, tras, twr, tmrd, trtp, trp, twtr, trfc, txs, txpr; in mx6_ddr3_cfg() local
1333 tmrd = DIV_ROUND_UP(max(12 * clkper, 15000), clkper) - 1; in mx6_ddr3_cfg()
1366 debug("tmrd=%d\n", tmrd); in mx6_ddr3_cfg()
1436 (twr << 9) | (tmrd << 5) | tcwl; in mx6_ddr3_cfg()
/openbmc/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun8i_a83t.c109 u8 tmrd = 4; in auto_set_timing_para() local
157 tmrd = 5; in auto_set_timing_para()
176 reg_val = (tmrw << 16) | (tmrd << 12) | (tmod << 0); in auto_set_timing_para()
H A Ddram_sun8i_a33.c109 u8 tmrd = 4; in auto_set_timing_para() local
144 reg_val = (tmrw << 16) | (tmrd << 12) | (tmod << 0); in auto_set_timing_para()
H A Ddram_sun50i_h6.c210 u8 tmrd = 5; in mctl_set_timing_lpddr3() local
249 writel((tmrw << 20) | (tmrd << 12) | tmod, &mctl_ctl->dramtmg[3]); in mctl_set_timing_lpddr3()
270 writel((tfaw << 17) | 0x28000400 | (tmrd << 1), &mctl_phy->dtpr[1]); in mctl_set_timing_lpddr3()
/openbmc/u-boot/arch/arm/include/asm/arch-vf610/
H A Dddrmc-vf610.h27 u8 tmrd; member
/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dsdram.h49 u32 tmrd; member
H A Dsdram_rk3036.h46 u32 tmrd; member
243 u32 tmrd; member
H A Dsdram_rk322x.h82 u32 tmrd; member
208 u32 tmrd; member
H A Dddr_rk3368.h50 u32 tmrd; member
H A Dddr_rk3288.h45 u32 tmrd; member
/openbmc/u-boot/arch/arm/cpu/arm926ejs/lpc32xx/
H A Ddram.c49 writel(dram->tmrd, &emc->t_mrd); in ddr_init()
/openbmc/u-boot/arch/arm/include/asm/arch-lpc32xx/
H A Demc.h92 u32 tmrd; member
/openbmc/u-boot/doc/device-tree-bindings/memory-controllers/
H A Dst,stm32-fmc.txt19 tmrd
/openbmc/linux/arch/mips/include/asm/octeon/
H A Dcvmx-lmcx-defs.h1829 uint64_t tmrd:3; member
1841 uint64_t tmrd:3;
1853 uint64_t tmrd:3; member
1865 uint64_t tmrd:3;
2602 uint64_t tmrd:4; member
2612 uint64_t tmrd:4;
2631 uint64_t tmrd:4; member
2641 uint64_t tmrd:4;
2659 uint64_t tmrd:4; member
2669 uint64_t tmrd:4;
/openbmc/u-boot/board/phytec/pcm052/
H A Dpcm052.c223 .tmrd = 4, in dram_init()
278 .tmrd = 4, in dram_init()
/openbmc/u-boot/arch/arm/mach-imx/
H A Dddrmc-vf610.c133 writel(DDRMC_CR16_TMRD(timings->tmrd) | in ddrmc_ctrl_init_ddr3()
/openbmc/u-boot/board/freescale/vf610twr/
H A Dvf610twr.c101 .tmrd = 4, in dram_init()
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Ddram_sun6i.h73 u32 tmrd; /* 0xd4 */ member
/openbmc/u-boot/doc/device-tree-bindings/clock/
H A Drockchip,rk3288-dmc.txt59 tmrd

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