| /openbmc/u-boot/board/k+p/kp_imx53/ |
| H A D | kp_imx53.c | 130 u32 ref_clk = MXC_HCLK; in setup_clocks() local
134 ret = mxc_set_clock(ref_clk, 800, MXC_ARM_CLK); in setup_clocks()
138 ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK); in setup_clocks()
139 ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK); in setup_clocks()
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| /openbmc/u-boot/board/beckhoff/mx53cx9020/ |
| H A D | mx53cx9020.c | 198 u32 ref_clk = MXC_HCLK; in clock_1GHz() local
203 ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK); in clock_1GHz()
207 ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK); in clock_1GHz()
208 ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK); in clock_1GHz()
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| /openbmc/u-boot/doc/device-tree-bindings/spi/ |
| H A D | spi-zynq-qspi.txt | 10 - clock-names : List of input clock names - "ref_clk", "pclk"
20 clock-names = "ref_clk", "pclk";
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| H A D | spi-zynq.txt | 10 - clock-names : List of input clock names - "ref_clk", "pclk"
25 clock-names = "ref_clk", "pclk";
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| H A D | spi-cadence.txt | 21 - cdns,tshsl-ns : Added delay in master reference clocks (ref_clk) for
24 - cdns,tsd2d-ns : Delay in master reference clocks (ref_clk) between one
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| /openbmc/u-boot/board/ge/mx53ppd/ |
| H A D | mx53ppd.c | 229 u32 ref_clk = MXC_HCLK; in clock_1GHz() local
234 ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK); in clock_1GHz()
240 ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK); in clock_1GHz()
241 ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK); in clock_1GHz()
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| /openbmc/u-boot/board/freescale/mx53loco/ |
| H A D | mx53loco.c | 308 u32 ref_clk = MXC_HCLK; in clock_1GHz() local
313 ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK); in clock_1GHz()
317 ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK); in clock_1GHz()
318 ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK); in clock_1GHz()
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| /openbmc/u-boot/board/menlo/m53menlo/ |
| H A D | m53menlo.c | 423 const u32 ref_clk = MXC_HCLK; in m53_set_clock() local
434 ret = mxc_set_clock(ref_clk, cpuclk, MXC_ARM_CLK); in m53_set_clock()
438 ret = mxc_set_clock(ref_clk, dramclk, MXC_PERIPH_CLK); in m53_set_clock()
444 ret = mxc_set_clock(ref_clk, dramclk, MXC_DDR_CLK); in m53_set_clock()
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| /openbmc/u-boot/drivers/video/rockchip/ |
| H A D | rk3288_mipi.c | 91 priv->ref_clk = 24 * MHz; in rk_mipi_enable()
92 priv->sys_clk = priv->ref_clk; in rk_mipi_enable()
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| H A D | rk3399_mipi.c | 83 priv->ref_clk = 24 * MHz; in rk_display_enable()
84 priv->sys_clk = priv->ref_clk; in rk_display_enable()
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| H A D | rk_mipi.h | 15 u32 ref_clk; member
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| H A D | rk_mipi.c | 207 u32 refclk = priv->ref_clk; in rk_mipi_phy_enable()
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| /openbmc/u-boot/board/inversepath/usbarmory/ |
| H A D | usbarmory.c | 369 u32 ref_clk = MXC_HCLK; in set_clock() local
374 ret = mxc_set_clock(ref_clk, cpuclk, MXC_ARM_CLK); in set_clock()
378 ret = mxc_set_clock(ref_clk, dramclk, MXC_PERIPH_CLK); in set_clock()
383 ret = mxc_set_clock(ref_clk, dramclk, MXC_DDR_CLK); in set_clock()
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | zynq-7000.dtsi | 187 clock-names = "ref_clk", "pclk";
199 clock-names = "ref_clk", "pclk";
205 clock-names = "ref_clk", "pclk";
322 clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";
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| H A D | zynqmp-mini-qspi.dts | 48 clock-names = "ref_clk", "pclk";
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| H A D | da850.dtsi | 36 ref_clk: ref_clk { label
39 clock-output-names = "ref_clk";
92 clocks = <&ref_clk>, <&pll1_sysclk 3>;
657 clocks = <&ref_clk>;
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| H A D | zynq-cse-qspi.dtsi | 52 clock-names = "ref_clk", "pclk";
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| H A D | zynqmp.dtsi | 638 clock-names = "ref_clk", "pclk";
759 clock-names = "ref_clk", "pclk";
770 clock-names = "ref_clk", "pclk";
837 clock-names = "bus_clk", "ref_clk";
862 clock-names = "bus_clk", "ref_clk";
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| H A D | da850-lcdk.dts | 126 &ref_clk {
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| H A D | ulcb.dtsi | 220 clock-names = "clk_in", "ref_clk";
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| H A D | da850-evm.dts | 160 &ref_clk {
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| H A D | salvator-common.dtsi | 390 clock-names = "clk_in", "ref_clk";
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| /openbmc/u-boot/drivers/spi/ |
| H A D | cadence_qspi.h | 73 unsigned int ref_clk, unsigned int sclk_hz,
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| H A D | cadence_qspi_apb.c | 337 unsigned int ref_clk, unsigned int sclk_hz, in cadence_qspi_apb_delay() argument
349 ref_clk_ns = DIV_ROUND_UP(1000000000, ref_clk); in cadence_qspi_apb_delay()
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| /openbmc/u-boot/arch/arm/mach-imx/mx5/ |
| H A D | clock.c | 67 #define PLL_FREQ_MAX(ref_clk) (4 * (ref_clk) * PLL_MFI_MAX) argument
68 #define PLL_FREQ_MIN(ref_clk) \ argument
69 ((2 * (ref_clk) * (PLL_MFI_MIN - 1)) / PLL_PD_MAX)
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