xref: /openbmc/u-boot/board/menlo/m53menlo/m53menlo.c (revision 2f07a9a6)
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Menlosystems M53Menlo board
4  *
5  * Copyright (C) 2012-2017 Marek Vasut <marex@denx.de>
6  * Copyright (C) 2014-2017 Olaf Mandel <o.mandel@menlosystems.com>
7  */
8 
9 #include <common.h>
10 #include <asm/io.h>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/sys_proto.h>
13 #include <asm/arch/crm_regs.h>
14 #include <asm/arch/clock.h>
15 #include <asm/arch/iomux-mx53.h>
16 #include <asm/mach-imx/mx5_video.h>
17 #include <asm/mach-imx/video.h>
18 #include <asm/gpio.h>
19 #include <asm/spl.h>
20 #include <fdt_support.h>
21 #include <fsl_esdhc.h>
22 #include <i2c.h>
23 #include <ipu_pixfmt.h>
24 #include <linux/errno.h>
25 #include <linux/fb.h>
26 #include <mmc.h>
27 #include <netdev.h>
28 #include <spl.h>
29 #include <splash.h>
30 #include <usb/ehci-ci.h>
31 
32 DECLARE_GLOBAL_DATA_PTR;
33 
34 static u32 mx53_dram_size[2];
35 
board_get_usable_ram_top(ulong total_size)36 ulong board_get_usable_ram_top(ulong total_size)
37 {
38 	/*
39 	 * WARNING: We must override get_effective_memsize() function here
40 	 * to report only the size of the first DRAM bank. This is to make
41 	 * U-Boot relocator place U-Boot into valid memory, that is, at the
42 	 * end of the first DRAM bank. If we did not override this function
43 	 * like so, U-Boot would be placed at the address of the first DRAM
44 	 * bank + total DRAM size - sizeof(uboot), which in the setup where
45 	 * each DRAM bank contains 512MiB of DRAM would result in placing
46 	 * U-Boot into invalid memory area close to the end of the first
47 	 * DRAM bank.
48 	 */
49 	return PHYS_SDRAM_2 + mx53_dram_size[1];
50 }
51 
dram_init(void)52 int dram_init(void)
53 {
54 	mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
55 	mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
56 
57 	gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1];
58 
59 	return 0;
60 }
61 
dram_init_banksize(void)62 int dram_init_banksize(void)
63 {
64 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
65 	gd->bd->bi_dram[0].size = mx53_dram_size[0];
66 
67 	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
68 	gd->bd->bi_dram[1].size = mx53_dram_size[1];
69 
70 	return 0;
71 }
72 
setup_iomux_uart(void)73 static void setup_iomux_uart(void)
74 {
75 	static const iomux_v3_cfg_t uart_pads[] = {
76 		MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
77 		MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
78 	};
79 
80 	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
81 }
82 
83 #ifdef CONFIG_USB_EHCI_MX5
board_ehci_hcd_init(int port)84 int board_ehci_hcd_init(int port)
85 {
86 	if (port == 0) {
87 		/* USB OTG PWRON */
88 		imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_4__GPIO1_4,
89 						    PAD_CTL_PKE |
90 						    PAD_CTL_DSE_HIGH));
91 		gpio_direction_output(IMX_GPIO_NR(1, 4), 0);
92 
93 		/* USB OTG Over Current */
94 		imx_iomux_v3_setup_pad(MX53_PAD_GPIO_18__GPIO7_13);
95 	} else if (port == 1) {
96 		/* USB Host PWRON */
97 		imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_2__GPIO1_2,
98 						    PAD_CTL_PKE |
99 						    PAD_CTL_DSE_HIGH));
100 		gpio_direction_output(IMX_GPIO_NR(1, 2), 0);
101 
102 		/* USB Host Over Current */
103 		imx_iomux_v3_setup_pad(MX53_PAD_GPIO_3__USBOH3_USBH1_OC);
104 	}
105 
106 	return 0;
107 }
108 #endif
109 
setup_iomux_fec(void)110 static void setup_iomux_fec(void)
111 {
112 	static const iomux_v3_cfg_t fec_pads[] = {
113 		/* MDIO pads */
114 		NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
115 			PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
116 		NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
117 
118 		/* FEC 0 pads */
119 		NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
120 			     PAD_CTL_HYS | PAD_CTL_PKE),
121 		NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
122 			     PAD_CTL_HYS | PAD_CTL_PKE),
123 		NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
124 			     PAD_CTL_HYS | PAD_CTL_PKE),
125 		NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
126 		NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
127 			     PAD_CTL_HYS | PAD_CTL_PKE),
128 		NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
129 			     PAD_CTL_HYS | PAD_CTL_PKE),
130 		NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
131 		NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
132 
133 		/* FEC 1 pads */
134 		NEW_PAD_CTRL(MX53_PAD_KEY_COL0__FEC_RDATA_3,
135 			     PAD_CTL_HYS | PAD_CTL_PKE),
136 		NEW_PAD_CTRL(MX53_PAD_KEY_ROW0__FEC_TX_ER,
137 			     PAD_CTL_HYS | PAD_CTL_PKE),
138 		NEW_PAD_CTRL(MX53_PAD_KEY_COL1__FEC_RX_CLK,
139 			     PAD_CTL_HYS | PAD_CTL_PKE),
140 		NEW_PAD_CTRL(MX53_PAD_KEY_ROW1__FEC_COL,
141 			     PAD_CTL_HYS | PAD_CTL_PKE),
142 		NEW_PAD_CTRL(MX53_PAD_KEY_COL2__FEC_RDATA_2,
143 			     PAD_CTL_HYS | PAD_CTL_PKE),
144 		NEW_PAD_CTRL(MX53_PAD_KEY_ROW2__FEC_TDATA_2, PAD_CTL_DSE_HIGH),
145 		NEW_PAD_CTRL(MX53_PAD_KEY_COL3__FEC_CRS,
146 			     PAD_CTL_HYS | PAD_CTL_PKE),
147 		NEW_PAD_CTRL(MX53_PAD_GPIO_19__FEC_TDATA_3, PAD_CTL_DSE_HIGH),
148 	};
149 
150 	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
151 }
152 
153 #ifdef CONFIG_FSL_ESDHC
154 struct fsl_esdhc_cfg esdhc_cfg = {
155 	MMC_SDHC1_BASE_ADDR,
156 };
157 
board_mmc_getcd(struct mmc * mmc)158 int board_mmc_getcd(struct mmc *mmc)
159 {
160 	imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1);
161 	gpio_direction_input(IMX_GPIO_NR(1, 1));
162 
163 	return !gpio_get_value(IMX_GPIO_NR(1, 1));
164 }
165 
166 #define SD_CMD_PAD_CTRL		(PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
167 				 PAD_CTL_PUS_100K_UP)
168 #define SD_PAD_CTRL		(PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
169 				 PAD_CTL_DSE_HIGH)
170 
board_mmc_init(bd_t * bis)171 int board_mmc_init(bd_t *bis)
172 {
173 	static const iomux_v3_cfg_t sd1_pads[] = {
174 		NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
175 		NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
176 		NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
177 		NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
178 		NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
179 		NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
180 	};
181 
182 	esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
183 
184 	imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
185 
186 	return fsl_esdhc_initialize(bis, &esdhc_cfg);
187 }
188 #endif
189 
190 #ifdef CONFIG_VIDEO
enable_lvds_clock(struct display_info_t const * dev,const u8 hclk)191 static void enable_lvds_clock(struct display_info_t const *dev, const u8 hclk)
192 {
193 	static struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
194 	int ret;
195 
196 	/* For ETM0430G0DH6 model, this must be enabled before the clock. */
197 	gpio_direction_output(IMX_GPIO_NR(6, 0), 1);
198 
199 	/*
200 	 * Set LVDS clock to 33.28 MHz for the display. The PLL4 is set to
201 	 * 233 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
202 	 */
203 	ret = mxc_set_clock(MXC_HCLK, hclk, MXC_LDB_CLK);
204 	if (ret)
205 		puts("IPU:   Failed to configure LDB clock\n");
206 
207 	/* Configure CCM_CSCMR2 */
208 	clrsetbits_le32(&mxc_ccm->cscmr2,
209 			(0x7 << 26) | BIT(10) | BIT(8),
210 			(0x5 << 26) | BIT(10) | BIT(8));
211 
212 	/* Configure LDB_CTRL */
213 	writel(0x201, 0x53fa8008);
214 }
215 
enable_lvds_etm0430g0dh6(struct display_info_t const * dev)216 static void enable_lvds_etm0430g0dh6(struct display_info_t const *dev)
217 {
218 	/* For ETM0430G0DH6 model, this must be enabled before the clock. */
219 	gpio_direction_output(IMX_GPIO_NR(6, 0), 1);
220 
221 	/*
222 	 * Set LVDS clock to 9 MHz for the display. The PLL4 is set to
223 	 * 63 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
224 	 */
225 	enable_lvds_clock(dev, 63);
226 }
227 
enable_lvds_etm0700g0dh6(struct display_info_t const * dev)228 static void enable_lvds_etm0700g0dh6(struct display_info_t const *dev)
229 {
230 	/*
231 	 * Set LVDS clock to 33.28 MHz for the display. The PLL4 is set to
232 	 * 233 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
233 	 */
234 	enable_lvds_clock(dev, 233);
235 
236 	/* For ETM0700G0DH6 model, this may be enabled after the clock. */
237 	gpio_direction_output(IMX_GPIO_NR(6, 0), 1);
238 }
239 
240 static const char *lvds_compat_string;
241 
detect_lvds(struct display_info_t const * dev)242 static int detect_lvds(struct display_info_t const *dev)
243 {
244 	u8 touchid[23];
245 	u8 *touchptr = &touchid[0];
246 	int ret;
247 
248 	ret = i2c_set_bus_num(0);
249 	if (ret)
250 		return 0;
251 
252 	/* Touchscreen is at address 0x38, ID register is 0xbb. */
253 	ret = i2c_read(0x38, 0xbb, 1, touchid, sizeof(touchid));
254 	if (ret)
255 		return 0;
256 
257 	/* EP0430 prefixes the response with 0xbb, skip it. */
258 	if (*touchptr == 0xbb)
259 		touchptr++;
260 
261 	/* Skip the 'EP' prefix. */
262 	touchptr += 2;
263 
264 	ret = !memcmp(touchptr, &dev->mode.name[7], 4);
265 	if (ret)
266 		lvds_compat_string = dev->mode.name;
267 
268 	return ret;
269 }
270 
board_preboot_os(void)271 void board_preboot_os(void)
272 {
273 	/* Power off the LCD to prevent awful color flicker */
274 	gpio_direction_output(IMX_GPIO_NR(6, 0), 0);
275 }
276 
ft_board_setup(void * blob,bd_t * bd)277 int ft_board_setup(void *blob, bd_t *bd)
278 {
279 	if (lvds_compat_string)
280 		do_fixup_by_path_string(blob, "/panel", "compatible",
281 					lvds_compat_string);
282 
283 	return 0;
284 }
285 
286 struct display_info_t const displays[] = {
287 	{
288 		.bus	= 0,
289 		.addr	= 0,
290 		.detect	= detect_lvds,
291 		.enable	= enable_lvds_etm0430g0dh6,
292 		.pixfmt	= IPU_PIX_FMT_RGB666,
293 		.mode	= {
294 			.name		= "edt,etm0430g0dh6",
295 			.refresh	= 60,
296 			.xres		= 480,
297 			.yres		= 272,
298 			.pixclock	= 111111, /* picosecond (9 MHz) */
299 			.left_margin	= 2,
300 			.right_margin	= 2,
301 			.upper_margin	= 2,
302 			.lower_margin	= 2,
303 			.hsync_len	= 41,
304 			.vsync_len	= 10,
305 			.sync		= 0x40000000,
306 			.vmode          = FB_VMODE_NONINTERLACED
307 		}
308 	}, {
309 		.bus	= 0,
310 		.addr	= 0,
311 		.detect	= detect_lvds,
312 		.enable	= enable_lvds_etm0700g0dh6,
313 		.pixfmt	= IPU_PIX_FMT_RGB666,
314 		.mode	= {
315 			.name		= "edt,etm0700g0dh6",
316 			.refresh	= 60,
317 			.xres		= 800,
318 			.yres		= 480,
319 			.pixclock	= 30048, /* picosecond (33.28 MHz) */
320 			.left_margin	= 40,
321 			.right_margin	= 88,
322 			.upper_margin	= 10,
323 			.lower_margin	= 33,
324 			.hsync_len	= 128,
325 			.vsync_len	= 2,
326 			.sync		= FB_SYNC_EXT,
327 			.vmode          = FB_VMODE_NONINTERLACED
328 		}
329 	}
330 };
331 
332 size_t display_count = ARRAY_SIZE(displays);
333 #endif
334 
335 #ifdef CONFIG_SPLASH_SCREEN
336 static struct splash_location default_splash_locations[] = {
337 	{
338 		.name		= "mmc_fs",
339 		.storage	= SPLASH_STORAGE_MMC,
340 		.flags		= SPLASH_STORAGE_FS,
341 		.devpart	= "0:1",
342 	},
343 };
344 
splash_screen_prepare(void)345 int splash_screen_prepare(void)
346 {
347 	return splash_source_load(default_splash_locations,
348 				  ARRAY_SIZE(default_splash_locations));
349 }
350 #endif
351 
352 #define I2C_PAD_CTRL	(PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
353 			 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
354 
setup_iomux_i2c(void)355 static void setup_iomux_i2c(void)
356 {
357 	static const iomux_v3_cfg_t i2c_pads[] = {
358 		/* I2C1 */
359 		NEW_PAD_CTRL(MX53_PAD_EIM_D28__I2C1_SDA, I2C_PAD_CTRL),
360 		NEW_PAD_CTRL(MX53_PAD_EIM_D21__I2C1_SCL, I2C_PAD_CTRL),
361 		/* I2C2 */
362 		NEW_PAD_CTRL(MX53_PAD_EIM_D16__I2C2_SDA, I2C_PAD_CTRL),
363 		NEW_PAD_CTRL(MX53_PAD_EIM_EB2__I2C2_SCL, I2C_PAD_CTRL),
364 	};
365 
366 	imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
367 }
368 
setup_iomux_video(void)369 static void setup_iomux_video(void)
370 {
371 	static const iomux_v3_cfg_t lcd_pads[] = {
372 		MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
373 		MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
374 		MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
375 		MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
376 		MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
377 	};
378 
379 	imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
380 }
381 
setup_iomux_nand(void)382 static void setup_iomux_nand(void)
383 {
384 	static const iomux_v3_cfg_t nand_pads[] = {
385 		NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B,
386 			     PAD_CTL_DSE_HIGH),
387 		NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B,
388 			     PAD_CTL_DSE_HIGH),
389 		NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__EMI_NANDF_CLE,
390 			     PAD_CTL_DSE_HIGH),
391 		NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__EMI_NANDF_ALE,
392 			     PAD_CTL_DSE_HIGH),
393 		NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B,
394 			     PAD_CTL_PUS_100K_UP),
395 		NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0,
396 			     PAD_CTL_PUS_100K_UP),
397 		NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0,
398 			     PAD_CTL_DSE_HIGH),
399 		NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__EMI_NANDF_D_0,
400 			     PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
401 		NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__EMI_NANDF_D_1,
402 			     PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
403 		NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__EMI_NANDF_D_2,
404 			     PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
405 		NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__EMI_NANDF_D_3,
406 			     PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
407 		NEW_PAD_CTRL(MX53_PAD_PATA_DATA4__EMI_NANDF_D_4,
408 			     PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
409 		NEW_PAD_CTRL(MX53_PAD_PATA_DATA5__EMI_NANDF_D_5,
410 			     PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
411 		NEW_PAD_CTRL(MX53_PAD_PATA_DATA6__EMI_NANDF_D_6,
412 			     PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
413 		NEW_PAD_CTRL(MX53_PAD_PATA_DATA7__EMI_NANDF_D_7,
414 			     PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
415 	};
416 
417 	imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
418 }
419 
m53_set_clock(void)420 static void m53_set_clock(void)
421 {
422 	int ret;
423 	const u32 ref_clk = MXC_HCLK;
424 	const u32 dramclk = 400;
425 	u32 cpuclk;
426 
427 	imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_10__GPIO4_0,
428 					    PAD_CTL_DSE_HIGH | PAD_CTL_PKE));
429 	gpio_direction_input(IMX_GPIO_NR(4, 0));
430 
431 	/* GPIO10 selects modules' CPU speed, 1 = 1200MHz ; 0 = 800MHz */
432 	cpuclk = gpio_get_value(IMX_GPIO_NR(4, 0)) ? 1200 : 800;
433 
434 	ret = mxc_set_clock(ref_clk, cpuclk, MXC_ARM_CLK);
435 	if (ret)
436 		printf("CPU:   Switch CPU clock to %dMHz failed\n", cpuclk);
437 
438 	ret = mxc_set_clock(ref_clk, dramclk, MXC_PERIPH_CLK);
439 	if (ret) {
440 		printf("CPU:   Switch peripheral clock to %dMHz failed\n",
441 		       dramclk);
442 	}
443 
444 	ret = mxc_set_clock(ref_clk, dramclk, MXC_DDR_CLK);
445 	if (ret)
446 		printf("CPU:   Switch DDR clock to %dMHz failed\n", dramclk);
447 }
448 
m53_set_nand(void)449 static void m53_set_nand(void)
450 {
451 	u32 i;
452 
453 	/* NAND flash is muxed on ATA pins */
454 	setbits_le32(M4IF_BASE_ADDR + 0xc, M4IF_GENP_WEIM_MM_MASK);
455 
456 	/* Wait for Grant/Ack sequence (see EIM_CSnGCR2:MUX16_BYP_GRANT) */
457 	for (i = 0x4; i < 0x94; i += 0x18) {
458 		clrbits_le32(WEIM_BASE_ADDR + i,
459 			     WEIM_GCR2_MUX16_BYP_GRANT_MASK);
460 	}
461 
462 	mxc_set_clock(0, 33, MXC_NFC_CLK);
463 	enable_nfc_clk(1);
464 }
465 
board_early_init_f(void)466 int board_early_init_f(void)
467 {
468 	setup_iomux_uart();
469 	setup_iomux_fec();
470 	setup_iomux_i2c();
471 	setup_iomux_nand();
472 	setup_iomux_video();
473 
474 	m53_set_clock();
475 
476 	mxc_set_sata_internal_clock();
477 
478 	/* NAND clock @ 33MHz */
479 	m53_set_nand();
480 
481 	return 0;
482 }
483 
board_init(void)484 int board_init(void)
485 {
486 	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
487 
488 	return 0;
489 }
490 
checkboard(void)491 int checkboard(void)
492 {
493 	puts("Board: Menlosystems M53Menlo\n");
494 
495 	return 0;
496 }
497 
498 /*
499  * NAND SPL
500  */
501 #ifdef CONFIG_SPL_BUILD
spl_board_init(void)502 void spl_board_init(void)
503 {
504 	setup_iomux_nand();
505 	m53_set_clock();
506 	m53_set_nand();
507 }
508 
spl_boot_device(void)509 u32 spl_boot_device(void)
510 {
511 	return BOOT_DEVICE_NAND;
512 }
513 #endif
514