xref: /openbmc/u-boot/arch/arm/dts/zynqmp.dtsi (revision 500ad54e)
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * dts file for Xilinx ZynqMP
4 *
5 * (C) Copyright 2014 - 2015, Xilinx, Inc.
6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 */
14
15/ {
16	compatible = "xlnx,zynqmp";
17	#address-cells = <2>;
18	#size-cells = <2>;
19
20	cpus {
21		#address-cells = <1>;
22		#size-cells = <0>;
23
24		cpu0: cpu@0 {
25			compatible = "arm,cortex-a53", "arm,armv8";
26			device_type = "cpu";
27			enable-method = "psci";
28			operating-points-v2 = <&cpu_opp_table>;
29			reg = <0x0>;
30			cpu-idle-states = <&CPU_SLEEP_0>;
31		};
32
33		cpu1: cpu@1 {
34			compatible = "arm,cortex-a53", "arm,armv8";
35			device_type = "cpu";
36			enable-method = "psci";
37			reg = <0x1>;
38			operating-points-v2 = <&cpu_opp_table>;
39			cpu-idle-states = <&CPU_SLEEP_0>;
40		};
41
42		cpu2: cpu@2 {
43			compatible = "arm,cortex-a53", "arm,armv8";
44			device_type = "cpu";
45			enable-method = "psci";
46			reg = <0x2>;
47			operating-points-v2 = <&cpu_opp_table>;
48			cpu-idle-states = <&CPU_SLEEP_0>;
49		};
50
51		cpu3: cpu@3 {
52			compatible = "arm,cortex-a53", "arm,armv8";
53			device_type = "cpu";
54			enable-method = "psci";
55			reg = <0x3>;
56			operating-points-v2 = <&cpu_opp_table>;
57			cpu-idle-states = <&CPU_SLEEP_0>;
58		};
59
60		idle-states {
61			entry-method = "psci";
62
63			CPU_SLEEP_0: cpu-sleep-0 {
64				compatible = "arm,idle-state";
65				arm,psci-suspend-param = <0x40000000>;
66				local-timer-stop;
67				entry-latency-us = <300>;
68				exit-latency-us = <600>;
69				min-residency-us = <10000>;
70			};
71		};
72	};
73
74	cpu_opp_table: cpu_opp_table {
75		compatible = "operating-points-v2";
76		opp-shared;
77		opp00 {
78			opp-hz = /bits/ 64 <1199999988>;
79			opp-microvolt = <1000000>;
80			clock-latency-ns = <500000>;
81		};
82		opp01 {
83			opp-hz = /bits/ 64 <599999994>;
84			opp-microvolt = <1000000>;
85			clock-latency-ns = <500000>;
86		};
87		opp02 {
88			opp-hz = /bits/ 64 <399999996>;
89			opp-microvolt = <1000000>;
90			clock-latency-ns = <500000>;
91		};
92		opp03 {
93			opp-hz = /bits/ 64 <299999997>;
94			opp-microvolt = <1000000>;
95			clock-latency-ns = <500000>;
96		};
97	};
98
99	dcc: dcc {
100		compatible = "arm,dcc";
101		status = "disabled";
102		u-boot,dm-pre-reloc;
103	};
104
105	pmu {
106		compatible = "arm,armv8-pmuv3";
107		interrupt-parent = <&gic>;
108		interrupts = <0 143 4>,
109			     <0 144 4>,
110			     <0 145 4>,
111			     <0 146 4>;
112	};
113
114	psci {
115		compatible = "arm,psci-0.2";
116		method = "smc";
117	};
118
119	pmufw: firmware {
120		compatible = "xlnx,zynqmp-pm";
121		method = "smc";
122		interrupt-parent = <&gic>;
123		interrupts = <0 35 4>;
124	};
125
126	timer {
127		compatible = "arm,armv8-timer";
128		interrupt-parent = <&gic>;
129		interrupts = <1 13 0xf08>,
130			     <1 14 0xf08>,
131			     <1 11 0xf08>,
132			     <1 10 0xf08>;
133	};
134
135	edac {
136		compatible = "arm,cortex-a53-edac";
137	};
138
139	fpga_full: fpga-full {
140		compatible = "fpga-region";
141		fpga-mgr = <&pcap>;
142		#address-cells = <2>;
143		#size-cells = <2>;
144	};
145
146	nvmem_firmware {
147		compatible = "xlnx,zynqmp-nvmem-fw";
148		#address-cells = <1>;
149		#size-cells = <1>;
150
151		soc_revision: soc_revision@0 {
152			reg = <0x0 0x4>;
153		};
154	};
155
156	pcap: pcap {
157		compatible = "xlnx,zynqmp-pcap-fpga";
158	};
159
160	rst: reset-controller {
161		compatible = "xlnx,zynqmp-reset";
162		#reset-cells = <1>;
163	};
164
165	xlnx_dp_snd_card: dp_snd_card {
166		compatible = "xlnx,dp-snd-card";
167		status = "disabled";
168		xlnx,dp-snd-pcm = <&xlnx_dp_snd_pcm0>, <&xlnx_dp_snd_pcm1>;
169		xlnx,dp-snd-codec = <&xlnx_dp_snd_codec0>;
170	};
171
172	xlnx_dp_snd_codec0: dp_snd_codec0 {
173		compatible = "xlnx,dp-snd-codec";
174		status = "disabled";
175		clock-names = "aud_clk";
176	};
177
178	xlnx_dp_snd_pcm0: dp_snd_pcm0 {
179		compatible = "xlnx,dp-snd-pcm";
180		status = "disabled";
181		dmas = <&xlnx_dpdma 4>;
182		dma-names = "tx";
183	};
184
185	xlnx_dp_snd_pcm1: dp_snd_pcm1 {
186		compatible = "xlnx,dp-snd-pcm";
187		status = "disabled";
188		dmas = <&xlnx_dpdma 5>;
189		dma-names = "tx";
190	};
191
192	xilinx_drm: xilinx_drm {
193		compatible = "xlnx,drm";
194		status = "disabled";
195		xlnx,encoder-slave = <&xlnx_dp>;
196		xlnx,connector-type = "DisplayPort";
197		xlnx,dp-sub = <&xlnx_dp_sub>;
198		planes {
199			xlnx,pixel-format = "rgb565";
200			plane0 {
201				dmas = <&xlnx_dpdma 3>;
202				dma-names = "dma0";
203			};
204			plane1 {
205				dmas = <&xlnx_dpdma 0>,
206					<&xlnx_dpdma 1>,
207					<&xlnx_dpdma 2>;
208				dma-names = "dma0", "dma1", "dma2";
209			};
210		};
211	};
212
213	amba_apu: amba_apu@0 {
214		compatible = "simple-bus";
215		#address-cells = <2>;
216		#size-cells = <1>;
217		ranges = <0 0 0 0 0xffffffff>;
218
219		gic: interrupt-controller@f9010000 {
220			compatible = "arm,gic-400", "arm,cortex-a15-gic";
221			#interrupt-cells = <3>;
222			reg = <0x0 0xf9010000 0x10000>,
223			      <0x0 0xf9020000 0x20000>,
224			      <0x0 0xf9040000 0x20000>,
225			      <0x0 0xf9060000 0x20000>;
226			interrupt-controller;
227			interrupt-parent = <&gic>;
228			interrupts = <1 9 0xf04>;
229		};
230	};
231
232	amba: amba {
233		compatible = "simple-bus";
234		u-boot,dm-pre-reloc;
235		#address-cells = <2>;
236		#size-cells = <2>;
237		ranges;
238
239		can0: can@ff060000 {
240			compatible = "xlnx,zynq-can-1.0";
241			status = "disabled";
242			clock-names = "can_clk", "pclk";
243			reg = <0x0 0xff060000 0x0 0x1000>;
244			interrupts = <0 23 4>;
245			interrupt-parent = <&gic>;
246			tx-fifo-depth = <0x40>;
247			rx-fifo-depth = <0x40>;
248		};
249
250		can1: can@ff070000 {
251			compatible = "xlnx,zynq-can-1.0";
252			status = "disabled";
253			clock-names = "can_clk", "pclk";
254			reg = <0x0 0xff070000 0x0 0x1000>;
255			interrupts = <0 24 4>;
256			interrupt-parent = <&gic>;
257			tx-fifo-depth = <0x40>;
258			rx-fifo-depth = <0x40>;
259		};
260
261		cci: cci@fd6e0000 {
262			compatible = "arm,cci-400";
263			reg = <0x0 0xfd6e0000 0x0 0x9000>;
264			ranges = <0x0 0x0 0xfd6e0000 0x10000>;
265			#address-cells = <1>;
266			#size-cells = <1>;
267
268			pmu@9000 {
269				compatible = "arm,cci-400-pmu,r1";
270				reg = <0x9000 0x5000>;
271				interrupt-parent = <&gic>;
272				interrupts = <0 123 4>,
273					     <0 123 4>,
274					     <0 123 4>,
275					     <0 123 4>,
276					     <0 123 4>;
277			};
278		};
279
280		/* GDMA */
281		fpd_dma_chan1: dma@fd500000 {
282			status = "disabled";
283			compatible = "xlnx,zynqmp-dma-1.0";
284			reg = <0x0 0xfd500000 0x0 0x1000>;
285			interrupt-parent = <&gic>;
286			interrupts = <0 124 4>;
287			clock-names = "clk_main", "clk_apb";
288			xlnx,bus-width = <128>;
289			#stream-id-cells = <1>;
290			iommus = <&smmu 0x14e8>;
291		};
292
293		fpd_dma_chan2: dma@fd510000 {
294			status = "disabled";
295			compatible = "xlnx,zynqmp-dma-1.0";
296			reg = <0x0 0xfd510000 0x0 0x1000>;
297			interrupt-parent = <&gic>;
298			interrupts = <0 125 4>;
299			clock-names = "clk_main", "clk_apb";
300			xlnx,bus-width = <128>;
301			#stream-id-cells = <1>;
302			iommus = <&smmu 0x14e9>;
303		};
304
305		fpd_dma_chan3: dma@fd520000 {
306			status = "disabled";
307			compatible = "xlnx,zynqmp-dma-1.0";
308			reg = <0x0 0xfd520000 0x0 0x1000>;
309			interrupt-parent = <&gic>;
310			interrupts = <0 126 4>;
311			clock-names = "clk_main", "clk_apb";
312			xlnx,bus-width = <128>;
313			#stream-id-cells = <1>;
314			iommus = <&smmu 0x14ea>;
315		};
316
317		fpd_dma_chan4: dma@fd530000 {
318			status = "disabled";
319			compatible = "xlnx,zynqmp-dma-1.0";
320			reg = <0x0 0xfd530000 0x0 0x1000>;
321			interrupt-parent = <&gic>;
322			interrupts = <0 127 4>;
323			clock-names = "clk_main", "clk_apb";
324			xlnx,bus-width = <128>;
325			#stream-id-cells = <1>;
326			iommus = <&smmu 0x14eb>;
327		};
328
329		fpd_dma_chan5: dma@fd540000 {
330			status = "disabled";
331			compatible = "xlnx,zynqmp-dma-1.0";
332			reg = <0x0 0xfd540000 0x0 0x1000>;
333			interrupt-parent = <&gic>;
334			interrupts = <0 128 4>;
335			clock-names = "clk_main", "clk_apb";
336			xlnx,bus-width = <128>;
337			#stream-id-cells = <1>;
338			iommus = <&smmu 0x14ec>;
339		};
340
341		fpd_dma_chan6: dma@fd550000 {
342			status = "disabled";
343			compatible = "xlnx,zynqmp-dma-1.0";
344			reg = <0x0 0xfd550000 0x0 0x1000>;
345			interrupt-parent = <&gic>;
346			interrupts = <0 129 4>;
347			clock-names = "clk_main", "clk_apb";
348			xlnx,bus-width = <128>;
349			#stream-id-cells = <1>;
350			iommus = <&smmu 0x14ed>;
351		};
352
353		fpd_dma_chan7: dma@fd560000 {
354			status = "disabled";
355			compatible = "xlnx,zynqmp-dma-1.0";
356			reg = <0x0 0xfd560000 0x0 0x1000>;
357			interrupt-parent = <&gic>;
358			interrupts = <0 130 4>;
359			clock-names = "clk_main", "clk_apb";
360			xlnx,bus-width = <128>;
361			#stream-id-cells = <1>;
362			iommus = <&smmu 0x14ee>;
363		};
364
365		fpd_dma_chan8: dma@fd570000 {
366			status = "disabled";
367			compatible = "xlnx,zynqmp-dma-1.0";
368			reg = <0x0 0xfd570000 0x0 0x1000>;
369			interrupt-parent = <&gic>;
370			interrupts = <0 131 4>;
371			clock-names = "clk_main", "clk_apb";
372			xlnx,bus-width = <128>;
373			#stream-id-cells = <1>;
374			iommus = <&smmu 0x14ef>;
375		};
376
377		gpu: gpu@fd4b0000 {
378			status = "disabled";
379			compatible = "arm,mali-400", "arm,mali-utgard";
380			reg = <0x0 0xfd4b0000 0x0 0x10000>;
381			interrupt-parent = <&gic>;
382			interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;
383			interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1";
384			clock-names = "gpu", "gpu_pp0", "gpu_pp1";
385		};
386
387		/* LPDDMA default allows only secured access. inorder to enable
388		 * These dma channels, Users should ensure that these dma
389		 * Channels are allowed for non secure access.
390		 */
391		lpd_dma_chan1: dma@ffa80000 {
392			status = "disabled";
393			compatible = "xlnx,zynqmp-dma-1.0";
394			reg = <0x0 0xffa80000 0x0 0x1000>;
395			interrupt-parent = <&gic>;
396			interrupts = <0 77 4>;
397			clock-names = "clk_main", "clk_apb";
398			xlnx,bus-width = <64>;
399			#stream-id-cells = <1>;
400			iommus = <&smmu 0x868>;
401		};
402
403		lpd_dma_chan2: dma@ffa90000 {
404			status = "disabled";
405			compatible = "xlnx,zynqmp-dma-1.0";
406			reg = <0x0 0xffa90000 0x0 0x1000>;
407			interrupt-parent = <&gic>;
408			interrupts = <0 78 4>;
409			clock-names = "clk_main", "clk_apb";
410			xlnx,bus-width = <64>;
411			#stream-id-cells = <1>;
412			iommus = <&smmu 0x869>;
413		};
414
415		lpd_dma_chan3: dma@ffaa0000 {
416			status = "disabled";
417			compatible = "xlnx,zynqmp-dma-1.0";
418			reg = <0x0 0xffaa0000 0x0 0x1000>;
419			interrupt-parent = <&gic>;
420			interrupts = <0 79 4>;
421			clock-names = "clk_main", "clk_apb";
422			xlnx,bus-width = <64>;
423			#stream-id-cells = <1>;
424			iommus = <&smmu 0x86a>;
425		};
426
427		lpd_dma_chan4: dma@ffab0000 {
428			status = "disabled";
429			compatible = "xlnx,zynqmp-dma-1.0";
430			reg = <0x0 0xffab0000 0x0 0x1000>;
431			interrupt-parent = <&gic>;
432			interrupts = <0 80 4>;
433			clock-names = "clk_main", "clk_apb";
434			xlnx,bus-width = <64>;
435			#stream-id-cells = <1>;
436			iommus = <&smmu 0x86b>;
437		};
438
439		lpd_dma_chan5: dma@ffac0000 {
440			status = "disabled";
441			compatible = "xlnx,zynqmp-dma-1.0";
442			reg = <0x0 0xffac0000 0x0 0x1000>;
443			interrupt-parent = <&gic>;
444			interrupts = <0 81 4>;
445			clock-names = "clk_main", "clk_apb";
446			xlnx,bus-width = <64>;
447			#stream-id-cells = <1>;
448			iommus = <&smmu 0x86c>;
449		};
450
451		lpd_dma_chan6: dma@ffad0000 {
452			status = "disabled";
453			compatible = "xlnx,zynqmp-dma-1.0";
454			reg = <0x0 0xffad0000 0x0 0x1000>;
455			interrupt-parent = <&gic>;
456			interrupts = <0 82 4>;
457			clock-names = "clk_main", "clk_apb";
458			xlnx,bus-width = <64>;
459			#stream-id-cells = <1>;
460			iommus = <&smmu 0x86d>;
461		};
462
463		lpd_dma_chan7: dma@ffae0000 {
464			status = "disabled";
465			compatible = "xlnx,zynqmp-dma-1.0";
466			reg = <0x0 0xffae0000 0x0 0x1000>;
467			interrupt-parent = <&gic>;
468			interrupts = <0 83 4>;
469			clock-names = "clk_main", "clk_apb";
470			xlnx,bus-width = <64>;
471			#stream-id-cells = <1>;
472			iommus = <&smmu 0x86e>;
473		};
474
475		lpd_dma_chan8: dma@ffaf0000 {
476			status = "disabled";
477			compatible = "xlnx,zynqmp-dma-1.0";
478			reg = <0x0 0xffaf0000 0x0 0x1000>;
479			interrupt-parent = <&gic>;
480			interrupts = <0 84 4>;
481			clock-names = "clk_main", "clk_apb";
482			xlnx,bus-width = <64>;
483			#stream-id-cells = <1>;
484			iommus = <&smmu 0x86f>;
485		};
486
487		mc: memory-controller@fd070000 {
488			compatible = "xlnx,zynqmp-ddrc-2.40a";
489			reg = <0x0 0xfd070000 0x0 0x30000>;
490			interrupt-parent = <&gic>;
491			interrupts = <0 112 4>;
492		};
493
494		nand0: nand@ff100000 {
495			compatible = "arasan,nfc-v3p10";
496			status = "disabled";
497			reg = <0x0 0xff100000 0x0 0x1000>;
498			clock-names = "clk_sys", "clk_flash";
499			interrupt-parent = <&gic>;
500			interrupts = <0 14 4>;
501			#address-cells = <2>;
502			#size-cells = <1>;
503			#stream-id-cells = <1>;
504			iommus = <&smmu 0x872>;
505		};
506
507		gem0: ethernet@ff0b0000 {
508			compatible = "cdns,zynqmp-gem";
509			status = "disabled";
510			interrupt-parent = <&gic>;
511			interrupts = <0 57 4>, <0 57 4>;
512			reg = <0x0 0xff0b0000 0x0 0x1000>;
513			clock-names = "pclk", "hclk", "tx_clk";
514			#address-cells = <1>;
515			#size-cells = <0>;
516			#stream-id-cells = <1>;
517			iommus = <&smmu 0x874>;
518		};
519
520		gem1: ethernet@ff0c0000 {
521			compatible = "cdns,zynqmp-gem";
522			status = "disabled";
523			interrupt-parent = <&gic>;
524			interrupts = <0 59 4>, <0 59 4>;
525			reg = <0x0 0xff0c0000 0x0 0x1000>;
526			clock-names = "pclk", "hclk", "tx_clk";
527			#address-cells = <1>;
528			#size-cells = <0>;
529			#stream-id-cells = <1>;
530			iommus = <&smmu 0x875>;
531		};
532
533		gem2: ethernet@ff0d0000 {
534			compatible = "cdns,zynqmp-gem";
535			status = "disabled";
536			interrupt-parent = <&gic>;
537			interrupts = <0 61 4>, <0 61 4>;
538			reg = <0x0 0xff0d0000 0x0 0x1000>;
539			clock-names = "pclk", "hclk", "tx_clk";
540			#address-cells = <1>;
541			#size-cells = <0>;
542			#stream-id-cells = <1>;
543			iommus = <&smmu 0x876>;
544		};
545
546		gem3: ethernet@ff0e0000 {
547			compatible = "cdns,zynqmp-gem";
548			status = "disabled";
549			interrupt-parent = <&gic>;
550			interrupts = <0 63 4>, <0 63 4>;
551			reg = <0x0 0xff0e0000 0x0 0x1000>;
552			clock-names = "pclk", "hclk", "tx_clk";
553			#address-cells = <1>;
554			#size-cells = <0>;
555			#stream-id-cells = <1>;
556			iommus = <&smmu 0x877>;
557		};
558
559		gpio: gpio@ff0a0000 {
560			compatible = "xlnx,zynqmp-gpio-1.0";
561			status = "disabled";
562			#gpio-cells = <0x2>;
563			interrupt-parent = <&gic>;
564			interrupts = <0 16 4>;
565			interrupt-controller;
566			#interrupt-cells = <2>;
567			reg = <0x0 0xff0a0000 0x0 0x1000>;
568			gpio-controller;
569		};
570
571		i2c0: i2c@ff020000 {
572			compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
573			status = "disabled";
574			interrupt-parent = <&gic>;
575			interrupts = <0 17 4>;
576			reg = <0x0 0xff020000 0x0 0x1000>;
577			#address-cells = <1>;
578			#size-cells = <0>;
579		};
580
581		i2c1: i2c@ff030000 {
582			compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
583			status = "disabled";
584			interrupt-parent = <&gic>;
585			interrupts = <0 18 4>;
586			reg = <0x0 0xff030000 0x0 0x1000>;
587			#address-cells = <1>;
588			#size-cells = <0>;
589		};
590
591		ocm: memory-controller@ff960000 {
592			compatible = "xlnx,zynqmp-ocmc-1.0";
593			reg = <0x0 0xff960000 0x0 0x1000>;
594			interrupt-parent = <&gic>;
595			interrupts = <0 10 4>;
596		};
597
598		pcie: pcie@fd0e0000 {
599			compatible = "xlnx,nwl-pcie-2.11";
600			status = "disabled";
601			#address-cells = <3>;
602			#size-cells = <2>;
603			#interrupt-cells = <1>;
604			msi-controller;
605			device_type = "pci";
606			interrupt-parent = <&gic>;
607			interrupts = <0 118 4>,
608				     <0 117 4>,
609				     <0 116 4>,
610				     <0 115 4>,	/* MSI_1 [63...32] */
611				     <0 114 4>;	/* MSI_0 [31...0] */
612			interrupt-names = "misc", "dummy", "intx",
613					  "msi1", "msi0";
614			msi-parent = <&pcie>;
615			reg = <0x0 0xfd0e0000 0x0 0x1000>,
616			      <0x0 0xfd480000 0x0 0x1000>,
617			      <0x80 0x00000000 0x0 0x1000000>;
618			reg-names = "breg", "pcireg", "cfg";
619			ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000	/* non-prefetchable memory */
620				  0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
621			bus-range = <0x00 0xff>;
622			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
623			interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
624					<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
625					<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
626					<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
627			pcie_intc: legacy-interrupt-controller {
628				interrupt-controller;
629				#address-cells = <0>;
630				#interrupt-cells = <1>;
631			};
632		};
633
634		qspi: spi@ff0f0000 {
635			u-boot,dm-pre-reloc;
636			compatible = "xlnx,zynqmp-qspi-1.0";
637			status = "disabled";
638			clock-names = "ref_clk", "pclk";
639			interrupts = <0 15 4>;
640			interrupt-parent = <&gic>;
641			num-cs = <1>;
642			reg = <0x0 0xff0f0000 0x0 0x1000>,
643			      <0x0 0xc0000000 0x0 0x8000000>;
644			#address-cells = <1>;
645			#size-cells = <0>;
646			#stream-id-cells = <1>;
647			iommus = <&smmu 0x873>;
648		};
649
650		rtc: rtc@ffa60000 {
651			compatible = "xlnx,zynqmp-rtc";
652			status = "disabled";
653			reg = <0x0 0xffa60000 0x0 0x100>;
654			interrupt-parent = <&gic>;
655			interrupts = <0 26 4>, <0 27 4>;
656			interrupt-names = "alarm", "sec";
657			calibration = <0x8000>;
658		};
659
660		serdes: zynqmp_phy@fd400000 {
661			compatible = "xlnx,zynqmp-psgtr";
662			status = "disabled";
663			reg = <0x0 0xfd400000 0x0 0x40000>,
664			      <0x0 0xfd3d0000 0x0 0x1000>,
665			      <0x0 0xff5e0000 0x0 0x1000>;
666			reg-names = "serdes", "siou", "lpd";
667			nvmem-cells = <&soc_revision>;
668			nvmem-cell-names = "soc_revision";
669			resets = <&rst 16>, <&rst 59>, <&rst 60>,
670				 <&rst 61>, <&rst 62>, <&rst 63>,
671				 <&rst 64>, <&rst 3>, <&rst 29>,
672				 <&rst 30>, <&rst 31>, <&rst 32>;
673			reset-names = "sata_rst", "usb0_crst", "usb1_crst",
674				      "usb0_hibrst", "usb1_hibrst", "usb0_apbrst",
675				      "usb1_apbrst", "dp_rst", "gem0_rst",
676				      "gem1_rst", "gem2_rst", "gem3_rst";
677			lane0: lane0 {
678				#phy-cells = <4>;
679			};
680			lane1: lane1 {
681				#phy-cells = <4>;
682			};
683			lane2: lane2 {
684				#phy-cells = <4>;
685			};
686			lane3: lane3 {
687				#phy-cells = <4>;
688			};
689		};
690
691		sata: ahci@fd0c0000 {
692			compatible = "ceva,ahci-1v84";
693			status = "disabled";
694			reg = <0x0 0xfd0c0000 0x0 0x2000>;
695			interrupt-parent = <&gic>;
696			interrupts = <0 133 4>;
697			#stream-id-cells = <4>;
698			iommus = <&smmu 0x4c0>, <&smmu 0x4c1>,
699				 <&smmu 0x4c2>, <&smmu 0x4c3>;
700			/* dma-coherent; */
701		};
702
703		sdhci0: mmc@ff160000 {
704			u-boot,dm-pre-reloc;
705			compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
706			status = "disabled";
707			interrupt-parent = <&gic>;
708			interrupts = <0 48 4>;
709			reg = <0x0 0xff160000 0x0 0x1000>;
710			clock-names = "clk_xin", "clk_ahb";
711			xlnx,device_id = <0>;
712			#stream-id-cells = <1>;
713			iommus = <&smmu 0x870>;
714			nvmem-cells = <&soc_revision>;
715			nvmem-cell-names = "soc_revision";
716		};
717
718		sdhci1: mmc@ff170000 {
719			u-boot,dm-pre-reloc;
720			compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
721			status = "disabled";
722			interrupt-parent = <&gic>;
723			interrupts = <0 49 4>;
724			reg = <0x0 0xff170000 0x0 0x1000>;
725			clock-names = "clk_xin", "clk_ahb";
726			xlnx,device_id = <1>;
727			#stream-id-cells = <1>;
728			iommus = <&smmu 0x871>;
729			nvmem-cells = <&soc_revision>;
730			nvmem-cell-names = "soc_revision";
731		};
732
733		pinctrl0: pinctrl@ff180000 {
734			compatible = "xlnx,pinctrl-zynqmp";
735			status = "disabled";
736			reg = <0x0 0xff180000 0x0 0x1000>;
737		};
738
739		smmu: smmu@fd800000 {
740			compatible = "arm,mmu-500";
741			reg = <0x0 0xfd800000 0x0 0x20000>;
742			#iommu-cells = <1>;
743			status = "disabled";
744			#global-interrupts = <1>;
745			interrupt-parent = <&gic>;
746			interrupts = <0 155 4>,
747				<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
748				<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
749				<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
750				<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;
751		};
752
753		spi0: spi@ff040000 {
754			compatible = "cdns,spi-r1p6";
755			status = "disabled";
756			interrupt-parent = <&gic>;
757			interrupts = <0 19 4>;
758			reg = <0x0 0xff040000 0x0 0x1000>;
759			clock-names = "ref_clk", "pclk";
760			#address-cells = <1>;
761			#size-cells = <0>;
762		};
763
764		spi1: spi@ff050000 {
765			compatible = "cdns,spi-r1p6";
766			status = "disabled";
767			interrupt-parent = <&gic>;
768			interrupts = <0 20 4>;
769			reg = <0x0 0xff050000 0x0 0x1000>;
770			clock-names = "ref_clk", "pclk";
771			#address-cells = <1>;
772			#size-cells = <0>;
773		};
774
775		ttc0: timer@ff110000 {
776			compatible = "cdns,ttc";
777			status = "disabled";
778			interrupt-parent = <&gic>;
779			interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
780			reg = <0x0 0xff110000 0x0 0x1000>;
781			timer-width = <32>;
782		};
783
784		ttc1: timer@ff120000 {
785			compatible = "cdns,ttc";
786			status = "disabled";
787			interrupt-parent = <&gic>;
788			interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
789			reg = <0x0 0xff120000 0x0 0x1000>;
790			timer-width = <32>;
791		};
792
793		ttc2: timer@ff130000 {
794			compatible = "cdns,ttc";
795			status = "disabled";
796			interrupt-parent = <&gic>;
797			interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
798			reg = <0x0 0xff130000 0x0 0x1000>;
799			timer-width = <32>;
800		};
801
802		ttc3: timer@ff140000 {
803			compatible = "cdns,ttc";
804			status = "disabled";
805			interrupt-parent = <&gic>;
806			interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
807			reg = <0x0 0xff140000 0x0 0x1000>;
808			timer-width = <32>;
809		};
810
811		uart0: serial@ff000000 {
812			u-boot,dm-pre-reloc;
813			compatible = "cdns,uart-r1p12", "xlnx,xuartps";
814			status = "disabled";
815			interrupt-parent = <&gic>;
816			interrupts = <0 21 4>;
817			reg = <0x0 0xff000000 0x0 0x1000>;
818			clock-names = "uart_clk", "pclk";
819		};
820
821		uart1: serial@ff010000 {
822			u-boot,dm-pre-reloc;
823			compatible = "cdns,uart-r1p12", "xlnx,xuartps";
824			status = "disabled";
825			interrupt-parent = <&gic>;
826			interrupts = <0 22 4>;
827			reg = <0x0 0xff010000 0x0 0x1000>;
828			clock-names = "uart_clk", "pclk";
829		};
830
831		usb0: usb0@ff9d0000 {
832			#address-cells = <2>;
833			#size-cells = <2>;
834			status = "disabled";
835			compatible = "xlnx,zynqmp-dwc3";
836			reg = <0x0 0xff9d0000 0x0 0x100>;
837			clock-names = "bus_clk", "ref_clk";
838			ranges;
839			nvmem-cells = <&soc_revision>;
840			nvmem-cell-names = "soc_revision";
841
842			dwc3_0: dwc3@fe200000 {
843				compatible = "snps,dwc3";
844				status = "disabled";
845				reg = <0x0 0xfe200000 0x0 0x40000>;
846				interrupt-parent = <&gic>;
847				interrupts = <0 65 4>, <0 69 4>;
848				#stream-id-cells = <1>;
849				iommus = <&smmu 0x860>;
850				snps,quirk-frame-length-adjustment = <0x20>;
851				snps,refclk_fladj;
852				/* dma-coherent; */
853			};
854		};
855
856		usb1: usb1@ff9e0000 {
857			#address-cells = <2>;
858			#size-cells = <2>;
859			status = "disabled";
860			compatible = "xlnx,zynqmp-dwc3";
861			reg = <0x0 0xff9e0000 0x0 0x100>;
862			clock-names = "bus_clk", "ref_clk";
863			ranges;
864			nvmem-cells = <&soc_revision>;
865			nvmem-cell-names = "soc_revision";
866
867			dwc3_1: dwc3@fe300000 {
868				compatible = "snps,dwc3";
869				status = "disabled";
870				reg = <0x0 0xfe300000 0x0 0x40000>;
871				interrupt-parent = <&gic>;
872				interrupts = <0 70 4>, <0 74 4>;
873				#stream-id-cells = <1>;
874				iommus = <&smmu 0x861>;
875				snps,quirk-frame-length-adjustment = <0x20>;
876				snps,refclk_fladj;
877				/* dma-coherent; */
878			};
879		};
880
881		watchdog0: watchdog@fd4d0000 {
882			compatible = "cdns,wdt-r1p2";
883			status = "disabled";
884			interrupt-parent = <&gic>;
885			interrupts = <0 113 1>;
886			reg = <0x0 0xfd4d0000 0x0 0x1000>;
887			timeout-sec = <60>;
888			reset-on-timeout;
889		};
890
891		xilinx_ams: ams@ffa50000 {
892			compatible = "xlnx,zynqmp-ams";
893			status = "disabled";
894			interrupt-parent = <&gic>;
895			interrupts = <0 56 4>;
896			interrupt-names = "ams-irq";
897			reg = <0x0 0xffa50000 0x0 0x800>;
898			reg-names = "ams-base";
899			#address-cells = <2>;
900			#size-cells = <2>;
901			#io-channel-cells = <1>;
902			ranges;
903
904			ams_ps: ams_ps@ffa50800 {
905				compatible = "xlnx,zynqmp-ams-ps";
906				status = "disabled";
907				reg = <0x0 0xffa50800 0x0 0x400>;
908			};
909
910			ams_pl: ams_pl@ffa50c00 {
911				compatible = "xlnx,zynqmp-ams-pl";
912				status = "disabled";
913				reg = <0x0 0xffa50c00 0x0 0x400>;
914			};
915		};
916
917		xlnx_dp: dp@fd4a0000 {
918			compatible = "xlnx,v-dp";
919			status = "disabled";
920			reg = <0x0 0xfd4a0000 0x0 0x1000>;
921			interrupts = <0 119 4>;
922			interrupt-parent = <&gic>;
923			clock-names = "aclk", "aud_clk";
924			xlnx,dp-version = "v1.2";
925			xlnx,max-lanes = <2>;
926			xlnx,max-link-rate = <540000>;
927			xlnx,max-bpc = <16>;
928			xlnx,enable-ycrcb;
929			xlnx,colormetry = "rgb";
930			xlnx,bpc = <8>;
931			xlnx,audio-chan = <2>;
932			xlnx,dp-sub = <&xlnx_dp_sub>;
933			xlnx,max-pclock-frequency = <300000>;
934		};
935
936		xlnx_dp_sub: dp_sub@fd4aa000 {
937			compatible = "xlnx,dp-sub";
938			status = "disabled";
939			reg = <0x0 0xfd4aa000 0x0 0x1000>,
940			      <0x0 0xfd4ab000 0x0 0x1000>,
941			      <0x0 0xfd4ac000 0x0 0x1000>;
942			reg-names = "blend", "av_buf", "aud";
943			xlnx,output-fmt = "rgb";
944			xlnx,vid-fmt = "yuyv";
945			xlnx,gfx-fmt = "rgb565";
946		};
947
948		xlnx_dpdma: dma@fd4c0000 {
949			compatible = "xlnx,dpdma";
950			status = "disabled";
951			reg = <0x0 0xfd4c0000 0x0 0x1000>;
952			interrupts = <0 122 4>;
953			interrupt-parent = <&gic>;
954			clock-names = "axi_clk";
955			dma-channels = <6>;
956			#dma-cells = <1>;
957			dma-video0channel {
958				compatible = "xlnx,video0";
959			};
960			dma-video1channel {
961				compatible = "xlnx,video1";
962			};
963			dma-video2channel {
964				compatible = "xlnx,video2";
965			};
966			dma-graphicschannel {
967				compatible = "xlnx,graphics";
968			};
969			dma-audio0channel {
970				compatible = "xlnx,audio0";
971			};
972			dma-audio1channel {
973				compatible = "xlnx,audio1";
974			};
975		};
976	};
977};
978