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Searched refs:rate (Results 1 – 25 of 375) sorted by relevance

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/openbmc/u-boot/drivers/clk/renesas/
H A Dclk-rcar-gen3.c110 static int gen3_clk_setup_sdif_div(struct clk *clk, ulong rate) in gen3_clk_setup_sdif_div() argument
136 writel((rate == 400000000) ? 0x4 : 0x1, priv->base + core->offset); in gen3_clk_setup_sdif_div()
164 u64 rate = 0; in gen3_clk_get_rate64() local
176 rate = gen3_clk_get_rate64(&parent); in gen3_clk_get_rate64()
178 __func__, __LINE__, parent.id, rate); in gen3_clk_get_rate64()
179 return rate; in gen3_clk_get_rate64()
189 rate = clk_get_rate(&priv->clk_extal); in gen3_clk_get_rate64()
191 __func__, __LINE__, rate); in gen3_clk_get_rate64()
192 return rate; in gen3_clk_get_rate64()
196 rate = clk_get_rate(&priv->clk_extalr); in gen3_clk_get_rate64()
[all …]
H A Dclk-rcar-gen2.c82 u32 value, mult, div, rate = 0; in gen2_clk_get_rate() local
94 rate = gen2_clk_get_rate(&parent); in gen2_clk_get_rate()
96 __func__, __LINE__, parent.id, rate); in gen2_clk_get_rate()
97 return rate; in gen2_clk_get_rate()
107 rate = clk_get_rate(&priv->clk_extal); in gen2_clk_get_rate()
109 __func__, __LINE__, rate); in gen2_clk_get_rate()
110 return rate; in gen2_clk_get_rate()
114 rate = clk_get_rate(&priv->clk_extal_usb); in gen2_clk_get_rate()
116 __func__, __LINE__, rate); in gen2_clk_get_rate()
117 return rate; in gen2_clk_get_rate()
[all …]
/openbmc/u-boot/arch/mips/mach-pic32/
H A Dcpu.c25 static ulong rate(int id) in rate() function
30 ulong rate; in rate() local
43 rate = clk_get_rate(&clk); in rate()
47 return rate; in rate()
52 return rate(PB7CLK); in clk_get_cpu_rate()
61 ulong rate; in prefetch_init() local
64 rate = clk_get_cpu_rate() / 1000000; in prefetch_init()
71 if (rate < 66) in prefetch_init()
73 else if (rate < 133) in prefetch_init()
78 if (rate <= 83) in prefetch_init()
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/openbmc/openbmc/meta-openembedded/meta-multimedia/recipes-multimedia/sox/sox/
H A DCVE-2022-31651.patch4 Subject: [PATCH] formats: reject implausible rate
23 - if (rate && ft->signal.rate && ft->signal.rate != rate)
24 + if (rate && ft->signal.rate && ft->signal.rate != rate) {
25 lsx_warn("`%s': overriding sample rate", ft->filename);
26 - else ft->signal.rate = rate;
28 + } else if (!(rate > 0)) {
29 + lsx_fail_errno(ft, EINVAL, "invalid rate value");
32 + ft->signal.rate = rate;
/openbmc/u-boot/arch/arm/mach-imx/mx7ulp/
H A Dscg.c54 u32 reg, val, rate; in scg_sircdiv_get_rate() local
84 rate = scg_src_get_rate(SCG_SIRC_CLK); in scg_sircdiv_get_rate()
85 rate = rate / (1 << (val - 1)); in scg_sircdiv_get_rate()
87 return rate; in scg_sircdiv_get_rate()
92 u32 reg, val, rate; in scg_fircdiv_get_rate() local
122 rate = scg_src_get_rate(SCG_FIRC_CLK); in scg_fircdiv_get_rate()
123 rate = rate / (1 << (val - 1)); in scg_fircdiv_get_rate()
125 return rate; in scg_fircdiv_get_rate()
130 u32 reg, val, rate; in scg_soscdiv_get_rate() local
160 rate = scg_src_get_rate(SCG_SOSC_CLK); in scg_soscdiv_get_rate()
[all …]
/openbmc/qemu/audio/
H A Drate_template.h33 struct rate *rate = opaque; in NAME() local
49 if (rate->opos_inc == (1ULL + UINT_MAX)) { in NAME()
66 ilast = rate->ilast; in NAME()
71 while (rate->ipos <= (rate->opos >> 32)) { in NAME()
73 rate->ipos++; in NAME()
89 if (rate->ipos >= 0x10001) { in NAME()
90 rate->ipos = 1; in NAME()
91 rate->opos &= 0xffffffff; in NAME()
97 t = (rate->opos & UINT_MAX) * (1.f / UINT_MAX); in NAME()
99 t = (rate->opos & UINT_MAX) / (mixeng_real) UINT_MAX; in NAME()
[all …]
H A Dmixeng.c468 struct rate { struct
480 struct rate *rate = g_new0(struct rate, 1); in st_rate_start() argument
482 rate->opos = 0; in st_rate_start()
485 rate->opos_inc = ((uint64_t) inrate << 32) / outrate; in st_rate_start()
487 rate->ipos = 0; in st_rate_start()
488 rate->ilast.l = 0; in st_rate_start()
489 rate->ilast.r = 0; in st_rate_start()
490 return rate; in st_rate_start()
519 struct rate *rate = opaque; in st_rate_frames_out() local
524 if (rate->opos_inc == 1ULL << 32) { in st_rate_frames_out()
[all …]
H A Dnoaudio.c36 RateCtl rate; member
41 RateCtl rate; member
47 return audio_rate_get_bytes(&no->rate, &hw->info, len); in no_write()
56 audio_rate_start(&no->rate); in no_init_out()
70 audio_rate_start(&no->rate); in no_enable_out()
80 audio_rate_start(&no->rate); in no_init_in()
92 int64_t bytes = audio_rate_get_bytes(&no->rate, &hw->info, size); in no_read()
103 audio_rate_start(&no->rate); in no_enable_in()
/openbmc/u-boot/arch/arm/mach-zynq/
H A Dclk.c37 ulong rate; in set_cpu_clk_info() local
51 rate = clk_get_rate(&clk) / 1000000; in set_cpu_clk_info()
53 gd->bd->bi_ddr_freq = rate; in set_cpu_clk_info()
55 gd->bd->bi_arm_freq = rate; in set_cpu_clk_info()
85 unsigned long rate; in soc_clk_dump() local
92 rate = clk_get_rate(&clk); in soc_clk_dump()
96 if ((rate == (unsigned long)-ENOSYS) || in soc_clk_dump()
97 (rate == (unsigned long)-ENXIO)) in soc_clk_dump()
100 printf("%10s%20lu\n", name, rate); in soc_clk_dump()
/openbmc/u-boot/drivers/clk/aspeed/
H A Dclk_ast2400.c118 u16 rate = (hpll_reg >> 8) & 3; in ast2400_get_hpll_rate() local
120 clkin = hpll_rates[1][rate]; in ast2400_get_hpll_rate()
123 clkin = hpll_rates[0][rate]; in ast2400_get_hpll_rate()
125 clkin = hpll_rates[0][rate]; in ast2400_get_hpll_rate()
181 u32 rate = ast2400_get_hpll_rate(scu); in ast2400_get_hclk() local
185 return (rate / ahb_div); in ast2400_get_hclk()
190 u32 rate = 0; in ast2400_get_pclk() local
191 rate = ast2400_get_hpll_rate(scu); in ast2400_get_pclk()
196 return (rate / apb_div); in ast2400_get_pclk()
223 ulong rate; in ast2400_clk_get_rate() local
[all …]
H A Dclk_ast2500.c140 u32 rate = 0; in ast2500_get_hclk() local
142 rate = ast2500_get_hpll_rate(scu); in ast2500_get_hclk()
143 return (rate / axi_div / ahb_div); in ast2500_get_hclk()
148 u32 rate = 0; in ast2500_get_pclk() local
152 rate = ast2500_get_hpll_rate(scu); in ast2500_get_pclk()
154 return (rate / apb_div); in ast2500_get_pclk()
194 ulong rate; in ast2500_clk_get_rate() local
198 rate = ast2500_get_hpll_rate(priv->scu); in ast2500_clk_get_rate()
201 rate = ast2500_get_mpll_rate(priv->scu); in ast2500_clk_get_rate()
204 rate = ast2500_get_dpll_rate(priv->scu); in ast2500_clk_get_rate()
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/openbmc/u-boot/drivers/clk/
H A Dclk-hsdk-cgu.c183 u32 rate; member
241 int (*update_rate)(struct hsdk_cgu_clk *clk, unsigned long rate,
280 ulong (*set_rate)(struct clk *clk, ulong rate);
372 u64 rate; in pll_get() local
395 rate = (u64)PARENT_RATE * fbdiv; in pll_get()
396 do_div(rate, idiv * odiv); in pll_get()
398 return rate; in pll_get()
401 static unsigned long hsdk_pll_round_rate(struct clk *sclk, unsigned long rate) in hsdk_pll_round_rate() argument
408 if (pll_cfg[0].rate == 0) in hsdk_pll_round_rate()
411 best_rate = pll_cfg[0].rate; in hsdk_pll_round_rate()
[all …]
H A Dclk_pic32.c170 int parent_rate, int rate, int parent_id) in pic32_set_refclk() argument
181 if (parent_rate <= rate) { in pic32_set_refclk()
185 div = parent_rate / (rate << 1); in pic32_set_refclk()
188 do_div(frac, rate); in pic32_set_refclk()
284 u64 rate; in pic32_get_mpll_rate() local
292 rate = (SYS_POSC_CLK_HZ / idiv) * mul; in pic32_get_mpll_rate()
293 do_div(rate, odiv1); in pic32_get_mpll_rate()
294 do_div(rate, odiv2); in pic32_get_mpll_rate()
296 return (ulong)rate; in pic32_get_mpll_rate()
321 ulong rate, pll_hz; in pic32_clk_init() local
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H A Dclk_meson.c74 static ulong meson_div_set_rate(struct clk *clk, unsigned long id, ulong rate,
80 ulong rate, ulong current_rate);
271 unsigned int rate, parent_rate; in meson_div_get_rate() local
308 rate = parent_rate / (reg + 1); in meson_div_get_rate()
310 debug("%s: rate of %ld is %d\n", __func__, id, rate); in meson_div_get_rate()
312 return rate; in meson_div_get_rate()
315 static ulong meson_div_set_rate(struct clk *clk, unsigned long id, ulong rate, in meson_div_set_rate() argument
325 if (current_rate == rate) in meson_div_set_rate()
329 __func__, id, current_rate, rate); in meson_div_set_rate()
359 if (!parent_rate || rate > parent_rate) in meson_div_set_rate()
[all …]
H A Dclk_sandbox.c13 ulong rate[SANDBOX_CLK_ID_COUNT]; member
24 return priv->rate[clk->id]; in sandbox_clk_get_rate()
27 static ulong sandbox_clk_set_rate(struct clk *clk, ulong rate) in sandbox_clk_set_rate() argument
35 if (!rate) in sandbox_clk_set_rate()
38 old_rate = priv->rate[clk->id]; in sandbox_clk_set_rate()
39 priv->rate[clk->id] = rate; in sandbox_clk_set_rate()
95 return priv->rate[id]; in sandbox_clk_query_rate()
H A Dclk_fixed_factor.c24 uint64_t rate; in clk_fixed_factor_get_rate() local
30 rate = clk_get_rate(&ff->parent); in clk_fixed_factor_get_rate()
31 if (IS_ERR_VALUE(rate)) in clk_fixed_factor_get_rate()
32 return rate; in clk_fixed_factor_get_rate()
34 do_div(rate, ff->div); in clk_fixed_factor_get_rate()
36 return rate * ff->mult; in clk_fixed_factor_get_rate()
/openbmc/u-boot/arch/arm/cpu/armv7/bcm281xx/
H A Dclk-core.c96 __func__, c->name, c->rate, c->div, c->sel, in peri_clk_enable()
97 c->parent->rate); in peri_clk_enable()
160 static int peri_clk_set_rate(struct clk *c, unsigned long rate) in peri_clk_set_rate() argument
171 diff = rate; in peri_clk_set_rate()
182 div = ref->clk.rate / rate; in peri_clk_set_rate()
186 new_rate = ref->clk.rate / div; in peri_clk_set_rate()
189 if (abs(new_rate - rate) < diff) { in peri_clk_set_rate()
190 diff = abs(new_rate - rate); in peri_clk_set_rate()
193 c->rate = new_rate; in peri_clk_set_rate()
199 c->name, c->rate, c->div, c->sel, c->parent->rate); in peri_clk_set_rate()
[all …]
/openbmc/u-boot/arch/arm/cpu/armv7/bcm235xx/
H A Dclk-core.c96 __func__, c->name, c->rate, c->div, c->sel, in peri_clk_enable()
97 c->parent->rate); in peri_clk_enable()
160 static int peri_clk_set_rate(struct clk *c, unsigned long rate) in peri_clk_set_rate() argument
171 diff = rate; in peri_clk_set_rate()
182 div = ref->clk.rate / rate; in peri_clk_set_rate()
186 new_rate = ref->clk.rate / div; in peri_clk_set_rate()
189 if (abs(new_rate - rate) < diff) { in peri_clk_set_rate()
190 diff = abs(new_rate - rate); in peri_clk_set_rate()
193 c->rate = new_rate; in peri_clk_set_rate()
199 c->name, c->rate, c->div, c->sel, c->parent->rate); in peri_clk_set_rate()
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/openbmc/u-boot/drivers/adc/
H A Dstm32-adc-core.c62 unsigned long rate; in stm32h7_adc_clk_sel() local
81 rate = clk_get_rate(&common->aclk); in stm32h7_adc_clk_sel()
82 if (!rate) { in stm32h7_adc_clk_sel()
95 if ((rate / div) <= STM32H7_ADC_MAX_CLK_RATE) in stm32h7_adc_clk_sel()
101 rate = clk_get_rate(&common->bclk); in stm32h7_adc_clk_sel()
102 if (!rate) { in stm32h7_adc_clk_sel()
115 if ((rate / div) <= STM32H7_ADC_MAX_CLK_RATE) in stm32h7_adc_clk_sel()
124 common->rate = rate / div; in stm32h7_adc_clk_sel()
133 ckmode ? "bus" : "adc", div, common->rate / 1000); in stm32h7_adc_clk_sel()
/openbmc/u-boot/drivers/clk/rockchip/
H A Dclk_rk3368.c159 u32 div, con, con_id, rate; in rk3368_mmc_get_clk() local
192 rate = DIV_TO_RATE(pll_rate, div); in rk3368_mmc_get_clk()
194 debug("%s: raw rate %d (post-divide by 2)\n", __func__, rate); in rk3368_mmc_get_clk()
195 return rate >> 1; in rk3368_mmc_get_clk()
199 ulong rate, in rk3368_mmc_find_best_rate_and_parent() argument
208 ulong rate; in rk3368_mmc_find_best_rate_and_parent() member
210 { .mux = MMC_PLL_SEL_CPLL, .rate = CPLL_HZ }, in rk3368_mmc_find_best_rate_and_parent()
211 { .mux = MMC_PLL_SEL_GPLL, .rate = GPLL_HZ }, in rk3368_mmc_find_best_rate_and_parent()
212 { .mux = MMC_PLL_SEL_24M, .rate = 24 * MHz } in rk3368_mmc_find_best_rate_and_parent()
215 debug("%s: target rate %ld\n", __func__, rate); in rk3368_mmc_find_best_rate_and_parent()
[all …]
/openbmc/u-boot/arch/arm/mach-omap2/
H A Dpipe3-phy.c69 u32 rate; in omap_pipe3_get_dpll_params() local
72 rate = get_sys_clk_freq(); in omap_pipe3_get_dpll_params()
74 for (; dpll_map->rate; dpll_map++) { in omap_pipe3_get_dpll_params()
75 if (rate == dpll_map->rate) in omap_pipe3_get_dpll_params()
80 __func__, rate); in omap_pipe3_get_dpll_params()
148 u32 val, rate; in omap_control_phy_power() local
152 rate = get_sys_clk_freq(); in omap_control_phy_power()
153 rate = rate/1000000; in omap_control_phy_power()
160 val |= rate << in omap_control_phy_power()
/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dcommproc.c121 m8560_cpm_setbrg(uint brg, uint rate) in m8560_cpm_setbrg() argument
136 *bp = (((((BRG_UART_CLK+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN; in m8560_cpm_setbrg()
143 m8560_cpm_fastbrg(uint brg, uint rate, int div16) in m8560_cpm_fastbrg() argument
158 *bp = (((((BRG_INT_CLK+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN; in m8560_cpm_fastbrg()
168 m8560_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel) in m8560_cpm_extcbrg() argument
181 *bp = ((((((extclk/16)+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN; in m8560_cpm_extcbrg()
/openbmc/u-boot/arch/arm/mach-tegra/
H A Demc.c25 unsigned rate; in board_emc_init() local
30 rate = EMC_SDRAM_RATE_T20; in board_emc_init()
33 rate = EMC_SDRAM_RATE_T25; in board_emc_init()
36 return tegra_set_emc(gd->fdt_blob, rate); in board_emc_init()
/openbmc/u-boot/board/synopsys/hsdk/
H A Dclk-lib.c15 int soc_clk_ctl(const char *name, ulong *rate, enum clk_ctl_ops ctl) in soc_clk_ctl() argument
39 if ((ctl & CLK_SET) && rate) { in soc_clk_ctl()
40 priv_rate = ctl & CLK_MHZ ? (*rate) * HZ_IN_MHZ : *rate; in soc_clk_ctl()
63 if ((ctl & CLK_GET) && rate) in soc_clk_ctl()
64 *rate = priv_rate; in soc_clk_ctl()
/openbmc/u-boot/drivers/usb/dwc3/
H A Dti_usb_phy.c81 unsigned long rate; member
118 unsigned long rate; in ti_usb3_get_dpll_params() local
121 rate = get_sys_clk_freq(); in ti_usb3_get_dpll_params()
123 for (; dpll_map->rate; dpll_map++) { in ti_usb3_get_dpll_params()
124 if (rate == dpll_map->rate) in ti_usb3_get_dpll_params()
128 dev_err(phy->dev, "No DPLL configuration for %lu Hz SYS CLK\n", rate); in ti_usb3_get_dpll_params()
227 u32 rate; in ti_usb3_phy_power() local
228 rate = get_sys_clk_freq(); in ti_usb3_phy_power()
229 rate = rate/1000000; in ti_usb3_phy_power()
240 val |= rate << in ti_usb3_phy_power()

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