1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3 * Clock drivers for Qualcomm APQ8016
4 *
5 * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
6 *
7 * Based on Little Kernel driver, simplified
8 */
9
10 #include <common.h>
11 #include <clk-uclass.h>
12 #include <dm.h>
13 #include <errno.h>
14 #include <asm/io.h>
15 #include <linux/bitops.h>
16 #include "clock-snapdragon.h"
17
18 /* GPLL0 clock control registers */
19 #define GPLL0_STATUS_ACTIVE BIT(17)
20
21 static const struct bcr_regs sdc_regs[] = {
22 {
23 .cfg_rcgr = SDCC_CFG_RCGR(1),
24 .cmd_rcgr = SDCC_CMD_RCGR(1),
25 .M = SDCC_M(1),
26 .N = SDCC_N(1),
27 .D = SDCC_D(1),
28 },
29 {
30 .cfg_rcgr = SDCC_CFG_RCGR(2),
31 .cmd_rcgr = SDCC_CMD_RCGR(2),
32 .M = SDCC_M(2),
33 .N = SDCC_N(2),
34 .D = SDCC_D(2),
35 }
36 };
37
38 static struct pll_vote_clk gpll0_vote_clk = {
39 .status = GPLL0_STATUS,
40 .status_bit = GPLL0_STATUS_ACTIVE,
41 .ena_vote = APCS_GPLL_ENA_VOTE,
42 .vote_bit = BIT(0),
43 };
44
45 static struct vote_clk gcc_blsp1_ahb_clk = {
46 .cbcr_reg = BLSP1_AHB_CBCR,
47 .ena_vote = APCS_CLOCK_BRANCH_ENA_VOTE,
48 .vote_bit = BIT(10),
49 };
50
51 /* SDHCI */
clk_init_sdc(struct msm_clk_priv * priv,int slot,uint rate)52 static int clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate)
53 {
54 int div = 8; /* 100MHz default */
55
56 if (rate == 200000000)
57 div = 4;
58
59 clk_enable_cbc(priv->base + SDCC_AHB_CBCR(slot));
60 /* 800Mhz/div, gpll0 */
61 clk_rcg_set_rate_mnd(priv->base, &sdc_regs[slot], div, 0, 0,
62 CFG_CLK_SRC_GPLL0);
63 clk_enable_gpll0(priv->base, &gpll0_vote_clk);
64 clk_enable_cbc(priv->base + SDCC_APPS_CBCR(slot));
65
66 return rate;
67 }
68
69 static const struct bcr_regs uart2_regs = {
70 .cfg_rcgr = BLSP1_UART2_APPS_CFG_RCGR,
71 .cmd_rcgr = BLSP1_UART2_APPS_CMD_RCGR,
72 .M = BLSP1_UART2_APPS_M,
73 .N = BLSP1_UART2_APPS_N,
74 .D = BLSP1_UART2_APPS_D,
75 };
76
77 /* UART: 115200 */
clk_init_uart(struct msm_clk_priv * priv)78 static int clk_init_uart(struct msm_clk_priv *priv)
79 {
80 /* Enable AHB clock */
81 clk_enable_vote_clk(priv->base, &gcc_blsp1_ahb_clk);
82
83 /* 7372800 uart block clock @ GPLL0 */
84 clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 1, 144, 15625,
85 CFG_CLK_SRC_GPLL0);
86
87 /* Vote for gpll0 clock */
88 clk_enable_gpll0(priv->base, &gpll0_vote_clk);
89
90 /* Enable core clk */
91 clk_enable_cbc(priv->base + BLSP1_UART2_APPS_CBCR);
92
93 return 0;
94 }
95
msm_set_rate(struct clk * clk,ulong rate)96 ulong msm_set_rate(struct clk *clk, ulong rate)
97 {
98 struct msm_clk_priv *priv = dev_get_priv(clk->dev);
99
100 switch (clk->id) {
101 case 0: /* SDC1 */
102 return clk_init_sdc(priv, 0, rate);
103 break;
104 case 1: /* SDC2 */
105 return clk_init_sdc(priv, 1, rate);
106 break;
107 case 4: /* UART2 */
108 return clk_init_uart(priv);
109 break;
110 default:
111 return 0;
112 }
113 }
114