183 	u32 rate;  member
241 	int (*update_rate)(struct hsdk_cgu_clk *clk, unsigned long rate,
280 	ulong (*set_rate)(struct clk *clk, ulong rate);
372 	u64 rate;  in pll_get()  local
395 	rate = (u64)PARENT_RATE * fbdiv;  in pll_get()
396 	do_div(rate, idiv * odiv);  in pll_get()
398 	return rate;  in pll_get()
401 static unsigned long hsdk_pll_round_rate(struct clk *sclk, unsigned long rate)  in hsdk_pll_round_rate()  argument
408 	if (pll_cfg[0].rate == 0)  in hsdk_pll_round_rate()
411 	best_rate = pll_cfg[0].rate;  in hsdk_pll_round_rate()
413 	for (i = 1; pll_cfg[i].rate != 0; i++) {  in hsdk_pll_round_rate()
414 		if (abs(rate - pll_cfg[i].rate) < abs(rate - best_rate))  in hsdk_pll_round_rate()
415 			best_rate = pll_cfg[i].rate;  in hsdk_pll_round_rate()
424 				     unsigned long rate,  in hsdk_pll_comm_update_rate()  argument
444 				     unsigned long rate,  in hsdk_pll_core_update_rate()  argument
451 	if (rate > CORE_IF_CLK_THRESHOLD_HZ)  in hsdk_pll_core_update_rate()
471 	if (rate <= CORE_IF_CLK_THRESHOLD_HZ)  in hsdk_pll_core_update_rate()
477 static ulong pll_set(struct clk *sclk, ulong rate)  in pll_set()  argument
484 	best_rate = hsdk_pll_round_rate(sclk, rate);  in pll_set()
486 	for (i = 0; pll_cfg[i].rate != 0; i++) {  in pll_set()
487 		if (pll_cfg[i].rate == best_rate) {  in pll_set()
524 static ulong cpu_clk_set(struct clk *sclk, ulong rate)  in cpu_clk_set()  argument
528 	ret = pll_set(sclk, rate);  in cpu_clk_set()
529 	idiv_set(sclk, rate);  in cpu_clk_set()
535 static ulong axi_clk_set(struct clk *sclk, ulong rate)  in axi_clk_set()  argument
545 		if (axi_clk_cfg.clk_rate[i] == rate) {  in axi_clk_set()
552 		pr_err("axi clk: invalid rate=%ld Hz\n", rate);  in axi_clk_set()
573 static ulong tun_clk_set(struct clk *sclk, ulong rate)  in tun_clk_set()  argument
583 		if (tun_clk_cfg.clk_rate[i] == rate) {  in tun_clk_set()
590 		pr_err("tun clk: invalid rate=%ld Hz\n", rate);  in tun_clk_set()
611 static ulong idiv_set(struct clk *sclk, ulong rate)  in idiv_set()  argument
617 	div_factor = parent_rate / rate;  in idiv_set()
618 	if (abs(rate - parent_rate / (div_factor + 1)) <=  in idiv_set()
619 	    abs(rate - parent_rate / div_factor)) {  in idiv_set()
625 		       rate, parent_rate, div_factor, CGU_IDIV_MASK);  in idiv_set()
632 		       rate, parent_rate, div_factor);  in idiv_set()
665 static ulong hsdk_cgu_set_rate(struct clk *sclk, ulong rate)  in hsdk_cgu_set_rate()  argument
670 	return clock_map[sclk->id].set_rate(sclk, rate);  in hsdk_cgu_set_rate()